Datasheet MC54HCT374AJ, MC74HCT374AN, MC74HCT374ADW, MC74HCT374ASD, MC74HCT374ADT Datasheet (Motorola)



SEMICONDUCTOR TECHNICAL DATA

1

REV 7

 Motorola, Inc. 1997

2/97

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High–Performance Silicon–Gate CMOS

The MC54/74HCT374A may be used as a level converter for

interfacing TTL or NMOS outputs to High–Speed CMOS inputs.

The HCT374A is identical in pinout to the LS374.

Data meeting the setup and hold time is clocked to the outputs with the
rising edge of Clock. The Output Enable does not affect the state of the
flip–flops, but when Output Enable is high, the outputs are forced to the
high–impedance state. Thus, data may be stored even when the outputs
are not enabled.

The HCT374A is identical in function to the HCT574A, which has the
input pins on the opposite side of the package from the output pins. This
device is similar in function to the HCT534A, which has inverting outputs.

• Output Drive Capability: 15 LSTTL Loads

• TTL/NMOS–Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1.0 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 276 FETs or 69 Equivalent Gates

• Improvements over HCT374

— Improved Propagation Delays
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity

Design Criteria

Value

ÎÎÎ

Units

Internal Gate Count*

69

ÎÎÎ

ea.

Internal Gate Propagation Delay

1.5

ÎÎÎ

ns

Internal Gate Power Dissipation

5.0

ÎÎÎ

µW

Speed Power Product

.0075

ÎÎÎ

pJ

*Equivalent to a two–input NAND gate.



PIN ASSIGNMENT

FUNCTION TABLE

Inputs Output

Output
Enable Clock D Q

LHH
LLL
L L,H, X No Change
HXXZ

X = don’t care
Z = high impedance

Q2

D1

D0

Q0

OUTPUT

ENABLE

GND

Q3

D3

D2

Q1 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q6

D6

D7

Q7

V

CC

CLOCK

Q4

D4

D5

Q5

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ORDERING INFORMATION

MC54HCTXXXAJ
MC74HCTXXXAN
MC74HCTXXXADW
MC74HCTXXXASD
MC74HCTXXXADT

Ceramic
Plastic
SOIC
SSOP
TSSOP

DT SUFFIX

TSSOP PACKAGE

CASE 948E–02

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

1

20

1

20

SD SUFFIX

SSOP PACKAGE

CASE 940C–03

1

20

1

20

1

20

LOGIC DIAGRAM

DATA

INPUTS

D0

11

CLOCK

D1
D2
D3
D4
D5
D6
D7

18

17

14

13

8

7

4

3

1

OUTPUT ENABLE

19

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

16

15

12

9

6

5

2

PIN 20 = V

CC

PIN 10 = GND

NONINVERTING

OUTPUTS

MC54/74HCT374A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

Î

Î

Î

P

D

ОООООООООООО

Î

ОООООООООООО

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

SSOP or TSSOP Package†

ÎÎÎÎ

Î

ÎÎÎÎ

750
500
450

Î

Î

Î

mW

Î

T

stg

ОООООООООООО

Storage Temperature

ÎÎÎÎ

– 65 to + 150

Î

_

C

Î

Î

Î

Î

T

L

ОООООООООООО

Î

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC, SSOP or TSSOP Package)

(Ceramic DIP)

ÎÎÎÎ

Î

ÎÎÎÎ

Î

260
300

Î

Î

Î

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
SSOP or TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

4.5

5.5

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time (Figure 1)

0

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Symbol

ООООООО

Parameter

ООООООО

Test Conditions

ÎÎ

V

CC

V

ÎÎ

– 55 to

25_C

ÎÎ

v

85_C

ÎÎ

v

125_C

Î

Unit

ÎÎ

Î

V

IH

ООООООО

Î

Minimum High–Level Input
Voltage

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

4.5

5.5

ÎÎ

2.0

2.0

ÎÎ

Î

2.0

2.0

ÎÎ

Î

2.0

2.0

Î

Î

V

ÎÎ

Î

V

IL

ООООООО

Î

Maximum Low–Level Input
Voltage

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

4.5

5.5

ÎÎ

0.8

0.8

ÎÎ

Î

0.8

0.8

ÎÎ

Î

0.8

0.8

Î

Î

V

ÎÎ

Î

V

OH

ООООООО

Î

Minimum High–Level Output
Voltage

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

4.5

5.5

ÎÎ

4.4

5.4

ÎÎ

Î

4.4

5.4

ÎÎ

Î

4.4

5.4

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or V

IL

|I

out

| v 6.0 mA

ÎÎ

Î

4.5

ÎÎ

3.98

ÎÎ

Î

3.84

ÎÎ

Î

3.7

Î

Î

ÎÎ

Î

V

OL

ООООООО

Î

Maximum Low–Level Output
Voltage

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

4.5

5.5

ÎÎ

0.1

0.1

ÎÎ

Î

0.1

0.1

ÎÎ

Î

0.1

0.1

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or V

IL

|I

out

| v 6.0 mA

ÎÎ

Î

4.5

ÎÎ

0.26

ÎÎ

Î

0.33

ÎÎ

Î

0.4

Î

Î

I

in

Maximum Input Leakage Current

Vin = VCC or GND

5.5

± 0.1

± 1.0

± 1.0

µA

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC54/74HCT374A

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

V

CC

V

Test Conditions

Parameter

Symbol

Unit

v

125_C

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

ÎÎ

Î

I

OZ

ООООООО

Î

Maximum Three–State
Leakage Current

ООООООО

Î

Output in High–Impedance State
Vin = VIL or V

IH

V

out

= VCC or GND

ÎÎ

Î

5.5

ÎÎ

± 0.5

ÎÎ

Î

± 5.0

ÎÎ

Î

± 10

Î

Î

µA

ÎÎ

Î

I

CC

ООООООО

Î

Maximum Quiescent Supply
Current (per Package)

ООООООО

Î

Vin = VCC or GND
I

out

= 0 µA

ÎÎ

Î

5.5

ÎÎ

4.0

ÎÎ

Î

40

ÎÎ

Î

160

Î

Î

µA

∆I

CC

Additional Quiescent Supply
Current

Vin = 2.4 V, Any One Input
V

= V

or GND

Other In

uts

≥ –55_C

25_C to 125_C

ÎÎÎООООООО

Î

Current

ООООООО

Î

V

i

n

= V

CC

or

GND, Other Inputs

l

out

= 0 µA

ÎÎ

Î

5.5

ÎÎÎ

Î

2.9

ÎÎÎ

Î

2.4

Î

Î

mA

NOTE: 1. Total Supply Current = ICC + Σ∆ICC.
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (V

CC

= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)

ÎÎÎОООООООООООООООООÎОООООООО

Î

Guaranteed Limit

Î

Î

ÎÎ

Î

Symbol

ООООООООООООООООО

Î

Parameter

ÎÎ

Î

– 55 to

25_C

ÎÎ

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎ

Î

f

max

ООООООООООООООООО

Î

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

ÎÎ

Î

30

ÎÎ

Î

24

ÎÎ

Î

20

Î

Î

MHz

ÎÎ

Î

t

PLH

,

t

PHL

ООООООООООООООООО

Î

Maximum Propagation Delay, Clock to Q

(Figures 1 and 4)

ÎÎ

Î

31

ÎÎ

Î

39

ÎÎ

Î

47

Î

Î

ns

t

PLZ

,

t

PHZ

Maximum Propagation Delay, Output Enable to Q

(Figures 2 and 5)

30

38

45

ns

ÎÎ

Î

t

PZL

,

t

PZH

ООООООООООООООООО

Î

Maximum Propagation Delay, Output Enable to Q

(Figures 2 and 5)

ÎÎ

Î

30

ÎÎ

Î

38

ÎÎ

Î

45

Î

Î

ns

ÎÎ

Î

t

TLH

,

t

THL

ООООООООООООООООО

Î

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

ÎÎ

Î

12

ÎÎ

Î

15

ÎÎ

Î

18

Î

Î

ns

C

in

Maximum Input Capacitance

10

10

10

pF

C

out

Maximum Three–State Output Capacitance
(Output in High–Impedance State)

15

15

15

pF

NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Flip–Flop)*

65

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (V

CC

= 5.0 V ± 10%, Input tr = tf = 6.0 ns)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООООООООООООО

Î

Parameter

ÎÎ

Î

– 55 to

25_C

ÎÎ

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Î

Unit

ÎÎ

Î

t

su

ООООООООООООООООО

Î

Minimum Setup Time, Data to Clock

(Figure 3)

ÎÎ

Î

12

ÎÎ

Î

15

ÎÎ

Î

18

Î

Î

ns

t

h

Minimum Hold Time, Clock to Data

(Figure 3)

5.0

5.0

5.0

ns

ÎÎ

Î

t

w

ООООООООООООООООО

Î

Minimum Pulse Width, Clock

(Figure 1)

ÎÎ

Î

12

ÎÎ

Î

15

ÎÎ

Î

18

Î

Î

ns

ÎÎ

Î

tr, t

f

ООООООООООООООООО

Î

Maximum Input Rise and Fall Times

(Figure 1)

ÎÎ

Î

500

ÎÎ

Î

500

ÎÎ

Î

500

Î

Î

ns

MC54/74HCT374A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

SWITCHING W AVEFORMS

Figure 1.

t

r

t

f

V

CC

GND

t

THL

t

TLH

90%

1.3 V

10%

2.7 V

1.3 V

0.3 V

CLOCK

t

PLH

t

PHL

Q

t

w

1/f

max

1.3 V

1.3 V

1.3 V

OUTPUT

ENABLE

Q

t

PZL

t

PLZ

t

PZHtPHZ

10%

90%

3 V

GND
HIGH

IMPEDANCE
V

OL

V

OH

HIGH
IMPEDANCE

1.3 V

DATA

CLOCK

3 V

3 V

GND

GND

VALID

t

h

t

su

1.3 V

Figure 2.

Figure 3.

Q

TEST CIRCUITS

Figure 4.

EXPANDED LOGIC DIAGRAM

C

D0 D1 D2 D3 D4 D5 D6 D7

347813141718

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

256912151619

DQ

CLOCK

OUTPUT

ENABLE

11

1

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN
TESTING t

PLZ

AND t

PZL

CONNECT TO GND WHEN
TESTING t

PHZ

AND t

PZH

1 k

Ω

Figure 5.

C

DQCDQCDQCDQCDQCDQCDQ

MC54/74HCT374A

High–Speed CMOS Logic Data
DL129 — Rev 6

5 MOTOROLA

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

ISSUE E

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ISSUE E

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

ISSUE E

NOTES:

1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSIONS A AND B INCLUDE MENISCUS.

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 23.88 25.15 0.940 0.990
B 6.60 7.49 0.260 0.295
C 3.81 5.08 0.150 0.200
D 0.38 0.56 0.015 0.022
F 1.40 1.65 0.055 0.065
G 2.54 BSC 0.100 BSC
H 0.51 1.27 0.020 0.050
J 0.20 0.30 0.008 0.012
K 3.18 4.06 0.125 0.160
L 7.62 BSC 0.300 BSC
M 0 15 0 15
N 0.25 1.02 0.010 0.040

____

A

20

110

11

B

F

C

SEATING
PLANE

D

H

G

K

N

J

M

L

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

M

L

J

20 PL

M

B

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022

G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040

____

E

1.27 1.770.050 0.070

1

11

10

20

–A–

SEATING
PLANE

K

N

FG

D

20 PL

–T–

M

A

M

0.25 (0.010) T

E

B

C

F

1.27 BSC0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.

–A–

–B–

20

1

11

10

S

A

M

0.010 (0.25) B

S

T

D20X

M

B

M

0.010 (0.25)

P10X

J

F

G

18X

K

C

–T–

SEATING
PLANE

M

R

X 45

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029

__

__

MC54/74HCT374A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948E–02

ISSUE A

DIMAMIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030

G 0.65 BSC 0.026 BSC

H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.

110

1120

PIN 1
IDENT

A

B

–T–

0.100 (0.004)

C

D

G

H

SECTION N–N

K

K1

JJ1

N

N

M

F

–W–

SEATING
PLANE

–V–

–U–

S

U

M

0.10 (0.004) V

S

T

20X REFK

L

L/2

2X

S

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252
––– –––

S

U0.15 (0.006) T

SD SUFFIX

PLASTIC SSOP PACKAGE

CASE 940C–03

ISSUE B

20 11

101

H

A

B

F

M

K20X REF

S

U

M

0.12 (0.005) V

S

T

L

L/2

PIN 1
IDENT

S

U

M

0.20 (0.008) T

–V–

–U–

D

C

0.076 (0.003)

G

–T–

SEATING
PLANE

DETAIL E

N

N

0.25 (0.010)

K

J

J1

K1

SECTION N–N

DIMAMIN MAX MIN MAX

INCHES

7.07 7.33 0.278 0.288

MILLIMETERS

B 5.20 5.38 0.205 0.212
C 1.73 1.99 0.068 0.078
D 0.05 0.21 0.002 0.008
F 0.63 0.95 0.024 0.037
G 0.65 BSC 0.026 BSC
H 0.59 0.75 0.023 0.030
J 0.09 0.20 0.003 0.008

J1 0.09 0.16 0.003 0.006

K 0.25 0.38 0.010 0.015

K1 0.25 0.33 0.010 0.013

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF K DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR INTRUSION SHALL NOT
REDUCE DIMENSION K BY MORE THAN 0.07 (0.002)
AT LEAST MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.

L 7.65 7.90 0.301 0.311

M 0 8 0 8

DETAIL E

–W–

MC54/74HCT374A

High–Speed CMOS Logic Data
DL129 — Rev 6

7 MOTOROLA

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MC74HCT374A/D

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