Datasheet MC54HCT163AJ, MC74HCT163AN, MC74HCT161AD, MC74HCT161AN, MC74HCT163AD Datasheet (Motorola)



SEMICONDUCTOR TECHNICAL DATA

1

REV 2

 Motorola, Inc. 1995

10/95

 

High–Performance Silicon–Gate CMOS

The MC54/74HCT161A and HCT163A are identical in pinout to the LS161A and LS163A. These devices may be used as level converters for interfacing TTL or NMOS outputs to high speed CMOS inputs.

The HCT161A and HCT163A are programmable 4–bit binary counters with asynchronous and synchronous reset, respectively.

• Output Drive Capability: 10 LSTTL Loads

• TTL, NMOS Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 200 FETs or 50 Equivalent Gates

LOGIC DIAGRAM

Reset

Preset

Data

Inputs

Pin 16 = VCC Pin 8 = GND

1

P

3

6

P

2

5

P

1

4

P

0

3

Clock

2

Q

3

11

Q

2

12

Q

1

13

Q

0

14

Reset

1

Load

9

Enable P

7

Enable T

10

BCD or Binary Outputs

Count

Enables

Ripple Carry Out

15

FUNCTION TABLE

Inputs

Clock Reset* Load Enable P Enable T

Output

Q

L H H H H

X L H H H

X X H L X

X X H X L

Reset Load Preset Data Count No Count No Count

H = High Level; L = Low Level; X = Don’t Care * = HCT163A only. HCT161A is an “Asynchronous–Reset” device.

 

Device Count Mode Reset Mode

HCT161A HCT163A

Binary Binary

Asynchronous

Synchronous

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD

Ceramic Plastic SOIC

1

16

1

16

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

1

16

Pinout: 16–Lead Package (Top View)

1516 14 13 12 11 10

21 3 4 5 6 7

V

CC

9

8

RCO* Q0Q1Q2Q

3

Enable

T

Load

Reset Clock P0P1P2P3EnablePGND

* RCO = Ripple Carry Out

MC54/74HCT161A MC54/74HCT163A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

Positive DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

P

D

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

750 500

mW

T

stg

Storage Temperature Range

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP or SOIC Package

Ceramic DIP

260 300

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

4.5

5.5

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time (Figure 1)

0

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages referenced to GND)

V

CC

Guaranteed Limit

Symbol Parameter Test Conditions V

– 55 to 25_C

≤ 85°C ≤ 125°C Unit

V

IH

Minimum High–Level Input Voltage

V

out

= 0.1 V or VCC = –1.0V

|I

out

| v 20 µA

4.5

5.5

2.0

V

IL

Maximum Low–Level Input Voltage

V

out

= 0.1 V

|I

out

| v 20 µA

4.5

5.5

0.80

V

OH

Minimum High–Level Output Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

4.5

5.5

4.4

5.4

4.4

5.4

4.4

5.4

V

Vin = VIH or V

IL

|I

out

| v 4.0 mA

4.5 3.98 3.84 3.70 V

V

OL

Maximum Low–Level Output Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

4.5

5.5

0.10

V

Vin = VIH or V

IL

|I

out

| v 4.0 mA

4.5 0.26 0.33 0.40 V

I

in

Maximum Input Leakage Current Vin = VCC or GND 5.5 ± 0.10 ± 1.00 ± 1.00 µA

I

CC

Maximum Quiescent Supply Current (Per Package)

Vin = VCC or GND I

out

– 0 µA

5.5 4 40 160 µA

I

CC

Additional Quiescent Supply

Vin = 2.4V, Any One Input

≥–55°C 25 to +125°C

ICCAdditional Quiescent Supply

Current

Any One Input VIN = VCC or GND Other Inputs I

out

– 0 µA

5.5

2.9 2.4 mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

MC54/74HCT161A MC54/74HCT163A

High–Speed CMOS Logic Data DL129 — Rev 6

3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (V

CC

= 5.0 V ±10%: CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

Symbol Parameter Fig

– 55 to 25_C

≤85°C ≤125°C Unit

f

max

Maximum Clock Frequency (50% Duty Cycle)* 1,7 30 24 20 MHz

t

PLH

Maximum Propagation Delay Clock to Q 1,7 20 23 28 ns

t

PHL

1,7 25 30 32 ns

t

PHL

Maximum Propagation Delay Reset to Q (HCT161A Only) 2,7 25 29 33 ns

t

PLH

Maximum Propagation Delay Enable T to Ripple Carry Out 3,7 16 18 20 ns

t

PHL

3,7 21 24 28 ns

t

PLH

Maximum Propagation Delay Clock to Ripple Carry Out 1,7 22 25 28 ns

t

PHL

1,7 28 33 35 ns

t

PHL

Maximum Propagation Delay Reset to Ripple Carry Out (HCT161A Only)

2,7 24 28 32 ns

t

TLH, t

THL

Maximum Output Transition Time, Any Output 2,7 15 19 22 ns

C

in

Maximum Input Capacitance 1,7 10 10 10 pF

*Applies to noncascaded/nonsynchronous clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out

propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine f

max

. However,

if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the f

max

in the table above is applicable. See

Applications information in this data sheet.

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Gate)*

60

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (V

CC

= 5.0 V ±10%: CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

Symbol

Parameter

Fig.

– 55 to

25_C

≤85°C ≤125°C

Unit

t

su

Minimum Setup Time, Preset Data Inputs to Clock 5 12 18 20 ns Minimum Setup Time, Load to Clock 5 12 18 20 ns Minimum Setup Time, Reset to Clock (HCT163A Only) 4 12 18 20 ns Minimum Setup Time, Enable T or Enable P to Clock 6 12 18 20 ns

t

h

Minimum Hold Time, Clock to Preset Data Inputs 5 3 3 3 ns Minimum Hold Time, Clock to Load 5 3 3 3 ns Minimum Hold Time, Clock to Reset (HCT163A Only) 4 3 3 3 ns Minimum Hold Time, Clock to En T or En P 6 3 3 3 ns

t

rec

Minimum Recovery Time, Reset Inactive to Clock (HCT161A Only) 2 12 17 23 ns Minimum Recovery Time, Load Inactive to Clock 2 12 17 23 ns

t

w

Minimum Pulse Width, Clock 1 12 15 18 ns Minimum Pulse Width, Reset (HCT161A Only) 1 12 15 18 ns

tr, t

f

Maximum Input Rise and Fall Times 500 500 500 ns

MC54/74HCT161A MC54/74HCT163A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

FUNCTION DESCRIPTION

The HCT161A/163A are programmable 4–bit synchronous counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading and count–enable controls.

The HCT161A and HCT163A are binary counters with asynchronous Reset and synchronous Reset, respectively.

INPUTS

Clock (Pin 2)

The internal flip–flops toggle and the output count advances with the rising edge of the Clock input. In addition, control functions, such as resetting and loading occur with the rising edge of the Clock input. In addition, control functions, such as resetting (HCT163A) and loading occur with the rising edge of the Clock Input.

Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)

These are the data inputs for programmable counting. Data on these pins may be synchronously loaded into the internal flip–flops and appear at the counter outputs. P0 (Pin 3) is the least–significant bit and P3 (Pin 6) is the most–significant bit.

OUTPUTS

Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)

These are the counter outputs. Q0 (Pin 14) is the least–significant bit and Q3 (Pin 11) is the most–significant bit.

Ripple Carry Out (Pin 15)

When the counter is in its maximum state 1 111, this output goes high, providing an external look–ahead carry pulse that may be used to enable successive cascaded counters. Ripple Carry Out remains high only during the maximum count state. The logic equation for this output is:

Ripple Carry Out = Enable T • Q0 • Q1 • Q2 • Q3

CONTROL FUNCTIONS Resetting

A low level on the Reset pin (pin 1) resets the internal flip– flops and sets the outputs (Q0 through Q3) to a low level. The HCT161A resets asynchronously, and the HCT163A resets with the rising edge of the Clock input (synchronous reset).

Loading

With the rising edge of the Clock, a low level on Load (pin

9) loads the data from the Preset Data input pins (P0, P1, P2, P3) into the internal flip–flops and onto the output pins, Q0 through Q3. The count function is disabled as long as Load is low.

Count Enable/Disable

These devices have two count–enable control pins: Enable P (Pin 7) and Enable T (Pin 10). The devices count when these two pins and the Load pin are high. The logic equation is:

Count Enable = Enable P • Enable T • Load

The count is either enabled or disabled by the control inputs according to Table 1. In general, Enable P is a count–enable control: Enable T is both a count–enable and a Ripple–Carry Output control.

Table 1. Count Enable/Disable

Control Inputs

Result at Outputs

Load EnablePEnableTQ0–Q3 Ripple Carry Out

H H H Count High when Q0–Q3

L H H No Count

are maximum*

X L H No Count High when Q0–Q3

are maximum*

X X L No Count L

Q0 through Q3 are maximum when Q3 Q2 Q1 Q0 = 1111.

OUTPUT STATE DIAGRAM

Binary Counters

0

15

14

13

12

1 2 3 4

5

6

7

811 10 9

MC54/74HCT161A MC54/74HCT163A

High–Speed CMOS Logic Data DL129 — Rev 6

5 MOTOROLA

SWITCHING WAVEFORMS

t

r

Figure 1.

Clock

Any

Output

3.0V

GND

90%

1.3V

10%

t

f

t

w

90%

1.3V

10%

t

PHL

1/f

MAX

t

PLH

t

TLH

t

THL

Reset

3.0V

GND

t

w

Any

Output

3.0V

GND

Clock

Figure 2.

t

PHL

t

rec

1.3V

Figure 3.

t

r

Enable T

3.0V

GND

90%

1.3V

10%

t

f

Ripple

Carry Out

90%

1.3V

10%

t

THL

t

TLH

t

PHL

t

PLH

Figure 4. HCT163A Only

Reset

3.0V

GND

t

h

3.0V

GND

Clock

t

su

1.3V

Load

3.0V

GND

3.0V

GND

Clock

t

su

1.3V

Figure 5.

Inputs P0,

P1, P2, P

3

3.0V

GND

1.3V

t

su

t

h

t

h

t

rec

3.0V

GND

1.3V

Enable T

or

Enable P

3.0V

GND

1.3V

t

h

t

su

Valid

Clock

Figure 6.

Figure 7. Test Circuit

CL*

*Includes all probe and jig capacitance

TEST

POINT

DEVICE UNDER

TEST

OUTPUT

MC54/74HCT161A MC54/74HCT163A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

14

Q

0

3

P

0

T0 R C C Load Load P0

Q0

13

Q

1

T1 R C C Load Load P1

Q1

12

Q

2

T2 R C C Load Load P2

Q2

4

P

1

5

P

2

11

Q

3

T3 R C C Load Load P3

Q3

6

P

3

15

Ripple Carry Out

7

Enable P

10

Enable T

1

Reset

9

Load

2

Clock

R

Load Load

C C

The flip–flops shown in the circuit diagrams are Toggle– Enable flip–flops. A Toggle–Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data from Preset inputs P0, P1, P2 and P3, the Load signal is used to disable the Toggle input (Tn) of the flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flop on the next rising edge of the clock.

A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip–flop low.

Figure 8. 4–Bit Binary Counter with Asynchronous Reset (MC54/74HCT161A)

MC54/74HCT161A MC54/74HCT163A

High–Speed CMOS Logic Data DL129 — Rev 6

7 MOTOROLA

Figure 9. Timing Diagram

Reset (HCT161A)

Reset (HCT163A)

Load

P0

P1

P2

P3

Clock (HCT161A)

Clock (HCT163A)

Enable P

Enable T

Q0

Q1

Q2

Q3

Ripple Carry Out

Count Inhibit

Reset Load

12 13 14 15 0 1 2

(Asynchronous)

(Synchronous)

Preset

Data

Inputs

Outputs

Count

Enables

MC54/74HCT161A MC54/74HCT163A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

8

14

Q

0

3

P

0

T0 R C C Load Load P0

Q0

13

Q

1

T1 R C C Load Load P1

Q1

12

Q

2

T2 R C C Load Load P2

Q2

4

P

1

5

P

2

11

Q

3

T3 R C C Load Load P3

Q3

6

P

3

15

Ripple Carry Out

7

Enable P

10

Enable T

1

Reset

9

Load

2

Clock

R

Load Load

C C

The flip–flops shown in the circuit diagrams are Toggle– Enable flip–flops. A Toggle–Enable flip–flop is a combination of a D flip–flop and a T flip–flop. When loading data from Preset inputs P0, P1, P2 and P3, the Load signal is used to disable the Toggle input (Tn) of the flip–flop. The logic level at the Pn input is then clocked to the Q output of the flip–flop on the next rising edge of the clock.

A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip–flop low.

Figure 10. 4–Bit Binary Counter with Synchronous Reset (MC54/74HCT163A)

MC54/74HCT161A MC54/74HCT163A

High–Speed CMOS Logic Data DL129 — Rev 6

9 MOTOROLA

TYPICAL APPLICATIONS CASCADING

Figure 11. N–Bit Synchronous Counters

Enable P Enable T Clock

Reset Q0Q1Q2Q

3

Load Q0Q1Q2Q

3

Ripple

Carry

Out

Inputs

Outputs

Enable P Enable T Clock

Reset Q0Q1Q2Q

3

Load Q0Q1Q2Q

3

Ripple

Carry

Out

Inputs

Outputs

Enable P Enable T Clock

Reset Q0Q1Q2Q

3

Load Q0Q1Q2Q

3

Ripple

Carry

Out

Inputs

Outputs

To More Significant Stages

Load

H=Count

L=Disable

H=Count

L=Disable

Reset

Clock

NOTE: When used in these cascaded configurations the clock f

max

guaranteed limits may not apply. Actual performance will

depend on number of stages. This limitation is due to set–up times between Enable (port) and clock.

Figure 12. Nibble Ripple Counter

Enable P Enable T Clock

Reset Q0Q1Q2Q

3

Load Q0Q1Q2Q

3

Ripple

Carry

Out

Inputs

Outputs

Enable P Enable T Clock

Reset Q0Q1Q2Q

3

Load Q0Q1Q2Q

3

Ripple

Carry

Out

Inputs

Outputs

Enable P Enable T Clock

Reset Q0Q1Q2Q

3

Load Q0Q1Q2Q

3

Ripple

Carry

Out

Inputs

Outputs

To More Significant Stages

Enable P

Reset

Clock

Enable T

Load

MC54/74HCT161A MC54/74HCT163A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

10

TYPICAL APPLICATIONS VARYING THE MODULUS

Figure 13. Modulo–5 Counter Figure 14. Modulo–11 Counter

Other Inputs

Q0 Q1 Q2 Q3

Reset

Output

HCT163A

Optional Buffer

for Noise Rejection

Other Inputs

Q0 Q1 Q2 Q3

Reset

Output

HCT163A

Optional Buffer

for Noise Rejection

The HCT163A facilitates designing counters of any modulus with minimal external logic. The output is glitch–

free due to the synchronous Reset.

MC54/74HCT161A MC54/74HCT163A

High–Speed CMOS Logic Data DL129 — Rev 6

11 MOTOROLA

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

ISSUE V

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

19.05

6.10 —

0.39

1.40

0.21

3.18

19.93

7.49

5.08

0.50

1.65

0.38

4.31

0

°

0.51

15

°

1.01

1.27 BSC

2.54 BSC

7.62 BSC

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

0.750

0.240 —

0.015

0.055

0.008

0.125

0.785

0.295

0.200

0.020

0.065

0.015

0.170

0.050 BSC

0.100 BSC

0.300 BSC

A B C D E F G

J K L M N

0

°

0.020

15

°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.

1 8

916

–A

–

–B

–

C

K

N

G

E

F

D 16 PL

–T

–

SEATING

PLANE

M

L

J 16 PL

0.25 (0.010) T A

M

S

0.25 (0.010) T B

M

S

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A B C D

F G H

J K

L M

S

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50 0

°

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74 10

°

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295 0

°

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305 10

°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

B

1 8

916

F

H

G

D

16 PL

S

C

–T

–

SEATING PLANE

K

J

M

L

T A0.25 (0.010)

M M

0.25 (0.010) T B A

M

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A B C D F G J K M P R

9.80

3.80

1.35

0.35

0.40

0.19

0.10 0

°

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

0.25 7

°

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004 0

°

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.009 7

°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

1

8

916

–A

–

–B

–

D 16 PL

K

C

G

–T

–

SEATING

PLANE

R X 45°

M

J

F

P 8 PL

0.25 (0.010) B

M M

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

MC54/74HCT161A MC54/74HCT163A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

12

How to reach us: USA/EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: RMFAX0@email.sps.mot.com –TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MC54/74HCT161A/D

*MC54/74HCT161A/D*

◊

CODELINE

Datasheet MC54HCT163AJ, MC74HCT163AN, MC74HCT161AD, MC74HCT161AN, MC74HCT163AD Datasheet (Motorola)

Specifications and Main Features

Frequently Asked Questions

User Manual