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MC54HC597AJ
Datasheet (Motorola)
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Datasheet MC54HC597AJ, MC74HC597AD, MC74HC597ADT, MC74HC597AN Datasheet (Motorola)

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Page 1

SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1995
10/95
 
High–Performance Silicon–Gate CMOS
The MC54/74HC597A is identical in pinout to the LS597. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of an 8–bit input latch which feeds parallel data to an 8–bit shift register. Data can also be loaded serially (see Function Table).
The HC597A is similar i n function to the HC589A, which is a 3–state device.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 516 FETs or 129 Equivalent Gates
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
15 1 2 3 4 5 6 7
12
11 13 10
S
A
A B C D E
F G H
LATCH CLOCK
SHIFT CLOCK
SERIAL SHIFT/
PARALLEL LOAD
RESET
PARALLEL
DATA
INPUTS
INPUT LATCH
SHIFT
REGISTER
PIN 16 = V
CC
PIN 8 = GND
9
Q
H
SERIAL
DATA
OUTPUT
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
LATCH CLOCK
SERIAL SHIFT/ PARALLEL LOAD
S
A
A
V
CC
Q
H
RESET
SHIFT CLOCK
E
D
C
B
GND
H
G
F
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT
Ceramic Plastic SOIC TSSOP
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
1
16
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
Page 2
MC54/74HC597A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
P
D
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
TSSOP Package†
750 500 450
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)
260 300
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
— Ceramic DIP: – 10 mW/_C from 100_ to 125_C — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 3.0 V
VCC = 4.5 V VCC = 6.0 V
0 0 0 0
1000
600 500 400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC V
– 55 to
25_C
v
85_Cv 125_C
Unit
V
IH
Minimum High–Level Input Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum Low–Level Input Voltage
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
OH
Minimum High–Level Output Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9 4 4
5.9
1.9 4 4
5.9
V
Vin = VIH or VIL|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance cir­cuit. For proper operation, Vin and V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Page 3
MC54/74HC597A
High–Speed CMOS Logic Data DL129 — Rev 6
3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Unit
Guaranteed Limit
V
CC
V
Test Conditions
Parameter
Symbol
Unit
v
125_C
v
85_C
– 55 to
25_C
V
CC
V
Test Conditions
Parameter
Symbol
V
OL
Maximum Low–Level Output Voltage
Vin = VIH or V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
I
CC
Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND I
out
= 0 µA
6.0
4
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC V
– 55 to
25_C
v
85_Cv 125_C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 2 and 8)
2.0
3.0
4.5
6.0
10 15 30 50
9 14 28 45
8 12 25 40
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Latch Clock to Q
H
(Figures 1 and 8)
2.0
3.0
4.5
6.0
175 100
40 30
225 110
50 40
275 125
60 50
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Shift Clock to Q
H
(Figures 2 and 8)
2.0
3.0
4.5
6.0
160
90 30 25
200 130
40 30
240 160
48 40
ns
t
PHL
Maximum Propagation Delay, Reset to Q
H
(Figures 3 and 8)
2.0
3.0
4.5
6.0
160
90 30 25
200 130
40 30
240 160
48 40
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Serial Shift/Parallel Load to Q
H
(Figures 4 and 8)
2.0
3.0
4.5
6.0
160
90 30 25
200 130
40 30
240 160
48 40
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 8)
2.0
3.0
4.5
6.0
75 27 15 13
95 32 19 16
110
36 22 19
ns
C
in
Maximum Input Capacitance
—
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
40
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Page 4
MC54/74HC597A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
PIN DESCRIPTIONS
DATA INPUTS A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Parallel data inputs. Data on these inputs is stored in the
input latch on the rising edge of the Latch Clock input.
SA (Pin 14)
Serial data input. Data on this input is shifted into the shift register on the rising edge of the Shift Clock input it Serial Shift/Parallel Load
is high. Data on this input is ignored when
Serial Shift/Parallel Load
is low.
CONTROL INPUTS Serial Shift/Parallel Load
(Pin 13)
Shift register mode control. When a high level is applied to this pin, the shift register is allowed to serially shift data. When a low level is applied to this pin, the shift register accepts parallel data from the input latch, and serial shifting is inhibited.
Reset (Pin 10)
Asynchronous, Active–low shift register reset. A low level applied to this input resets the shift register to a low level, but does not change the data in the input latch.
Shift Clock (Pin 11)
Serial shift register clock. A low–to–high transition on this input shifts data on the Serial Data Input into the shift register and data in stage H is shifted out QH, being replaced by the data previously stored in stage G.
Latch Clock (Pin 12)
Latch clock. A low–to–high transition on this input loads the parallel data on inputs A–H into the input latch.
OUTPUT QH (Pin 9)
Serial data output. This pin is the output from the last stage of the shift register.
Page 5
MC54/74HC597A
High–Speed CMOS Logic Data DL129 — Rev 6
5 MOTOROLA
TIMING REQUIREMENTS (Input t
r
= tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC V
– 55 to
25_C
v
85_Cv 125_C
Unit
t
su
Minimum Setup Time, Parallel Data inputs A–H to Latch Clock
(Figure 5)
2.0
3.0
4.5
6.0
70 40 15 13
80 45 19 16
90 50 24 20
ns
t
su
Minimum Setup Time, Serial Data Input SA to Shift Clock
(Figure 6)
2.0
3.0
4.5
6.0
70 40 15 13
80 45 19 16
90 50 24 20
ns
t
su
Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock
(Figure 7)
2.0
3.0
4.5
6.0
70 40 15 13
80 45 19 16
90 50 24 20
ns
t
h
Minimum Hold Time, Latch Clock to Parallel Data Inputs A–H
(Figure 5)
2.0
3.0
4.5
6.0
15 10
2 2
20 15
3 3
30 25
5 4
ns
t
h
Minimum Hold Time, Shift Clock to Serial Data Input S
A
(Figure 6)
2.0
3.0
4.5
6.0
2 2 2 2
2 2 2 2
2 2 2 2
ns
t
rec
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 3)
2.0
3.0
4.5
6.0
70 40 15 13
80 45 19 16
90 50 24 20
ns
t
w
Minimum Pulse Width, Latch Clock and Shift Clock
(Figures 1 and 2)
2.0
3.0
4.5
6.0
60 35 12 10
70 40 15 13
80 45 19 16
ns
t
w
Minimum Pulse Width, Reset
(Figure 3)
2.0
3.0
4.5
6.0
60 35 12 10
70 40 15 13
80 45 19 16
ns
t
w
Minimum Pulse Width, Serial Shift/Parallel Load
(Figure 4)
2.0
3.0
4.5
6.0
60 35 12 10
70 40 15 13
80 45 19 16
ns
tr, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800 500 400
1000
800 500 400
1000
800 500 400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Page 6
MC54/74HC597A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
6
FUNCTION TABLE
Inputs Resulting Function
Operation
Reset
Serial Shift/
Parallel Load
Latch Clock
Shift
Clock
Serial
Input
S
A
Parallel
Inputs
A–H
Latch
Contents
Shift
Register
Contents
Output
Q
H
Reset shift register L X L, H, X X X U L L Reset shift register; load
parallel data into data latch
L X X X a–h a–h L L
Load parallel data into data latch
H H L,H, X a–h a–h U U
Transfer latch contents to shift register
H L L, H, X X X U LRN → SR
N
LR
H
Contents of data latch and shift register are unchanged
H H L, H, L,H, X X U U U
Load parallel data into data latch and shift register
H L X X a–h a–h a–h h
Shift serial data into shift register
H H X D X * SRA = D;
SRN → SR
N+1
SRG → SR
H
Load parallel data into data latch and shift serial data into shift register
H H D a–h a–h SRA = D;
SRN → SR
N+1
SRG → SR
H
LR = latch register contents a–h = data at parallel data inputs A–H U = remains unchanged SR = shift register contents D = data (L, H) at serial data input S
A
X = don’t care
* = depends on latch clock input
Page 7
MC54/74HC597A
High–Speed CMOS Logic Data DL129 — Rev 6
7 MOTOROLA
SWITCHING WAVEFORMS
SERIAL SHIFT/
PARALLEL LOAD
Q
H
50%
t
PLH
50%
V
CC
GND
t
PHL
50%
t
w
Figure 4.
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 8. Test Circuit
Figure 3.
Figure 7.
50%
50%
RESET
Q
H
SHIFT CLOCK
t
PHL
t
rec
V
CC
GND
SERIAL SHIFT/
PARALLEL LOAD
SHIFT CLOCK
50%
50%
t
su
V
CC
GND
V
CC
GND
t
w
Figure 1. (Serial Shift/Parallel Load = L) Figure 2. (Serial Shift/Parallel Load = H)
Figure 5. Figure 6.
LATCH CLOCK
Q
H
t
r
t
f
V
CC
GND
90%
50%
10%
t
PLH
t
PHL
t
TLH
t
THL
SHIFT CLOCK
Q
H
V
CC
GND
50%
50%
t
PLH
t
PHL
1/f
max
90% 50% 10%
t
w
50%LATCH CLOCK
V
CC
VALID
GND
V
CC
GND
t
su
t
h
50%
PARALLEL DATA
A/H
50%SHIFT CLOCK
V
CC
VALID
GND
V
CC
GND
t
su
t
h
50%
SERIAL DATA
INPUT S
A
t
w
Page 8
MC54/74HC597A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
8
PARALLEL
DATA
INPUTS
14
11
13
12
15
1
2
3
4
5
6
7
SERIAL DATA
INPUT, S
A
SHIFT CLOCK
SERIAL SHIFT/
PARALLEL LOAD
LATCH CLOCK
A
B
C
D
E
F
G
H
STAGE A
STAGE B
STAGE C*
STAGE D*
STAGE E*
STAGE F*
STAGE G*
STAGE H
DCQ
DCQ
D
C Q
S
R
D
C Q
S
R
DCQ
D
C Q
S
R
*NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.
EXPANDED LOGIC DIAGRAM
9
Q
H
10
RESET
Page 9
MC54/74HC597A
High–Speed CMOS Logic Data DL129 — Rev 6
9 MOTOROLA
SHIFT CLOCK
SERIAL DATA
INPUT, S
A
RESET
SERIAL SHIFT
PARALLEL LOAD
LATCH CLOCK
A
B
C
D
E
F
G
H
Q
H
PARALLEL
DATA
INPUTS
RESET
SHIFT
REGISTER
SERIAL
SHIFT
SERIAL SHIFT
SERIAL
SHIFT
SERIAL
SHIFT
LOAD LATCH PARALLEL LOAD
SHIFT REGISTER
LOAD LATCH PARALLEL LOAD
SHIFT REGISTER
PARALLEL LOAD LATCH
AND SHIFT REGISTER
H
L
H
L
H
H
L
H
L L H L H H L H L H L H L L L H L H H
L
L
L
L
L
L
L
H
L
L
L
L
H
H
L
H
TIMING DIAGRAM
Page 10
MC54/74HC597A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
10
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
19.05
6.10 —
0.39
1.40
0.21
3.18
19.93
7.49
5.08
0.50
1.65
0.38
4.31
0
°
0.51
15
°
1.01
1.27 BSC
2.54 BSC
7.62 BSC
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
0.750
0.240 —
0.015
0.055
0.008
0.125
0.785
0.295
0.200
0.020
0.065
0.015
0.170
0.050 BSC
0.100 BSC
0.300 BSC
A B C D E
F G J K L M N
0
°
0.020
15
°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.
1 8
916
–A
–
–B
–
C
K
N
G
E
F
D 16 PL
–T
–
SEATING
PLANE
M
L
J 16 PL
0.25 (0.010) T A
M
S
0.25 (0.010) T B
M
S
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A B C D F G H J K L M S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50 0
°
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74 10
°
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295 0
°
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305 10
°
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
–A
–
B
1 8
916
F
H
G
D
16 PL
S
C
–T
–
SEATING PLANE
K
J
M
L
T A0.25 (0.010)
M M
0.25 (0.010) T B A
M
S S
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A B C D F G J
K M P R
9.80
3.80
1.35
0.35
0.40
0.19
0.10 0
°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25 7
°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004 0
°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009 7
°
0.244
0.019
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
1
8
916
–A
–
–B
–
D 16 PL
K
C
G
–T
–
SEATING
PLANE
R X 45°
M
J
F
P 8 PL
0.25 (0.010) B
M M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
Page 11
MC54/74HC597A
High–Speed CMOS Logic Data DL129 — Rev 6
11 MOTOROLA
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
ÇÇ
ÇÇ
ÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C ––– 1.20 ––– 0.047 D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.
_ _ _ _
SECTION N–N
SEATING PLANE
IDENT.
PIN 1
1
8
16
9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X L/2
–U–
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V
S
T
0.10 (0.004)
–T–
–V–
–W–
0.25 (0.010)
16X REFK
N
N
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MC54/74HC597A/D
*MC54/74HC597A/D*
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