Datasheet MC54HC589J, MC74HC589N, MC74HC589D Datasheet (Motorola)



SEMICONDUCTOR TECHNICAL DATA

3–1

REV 6

 Motorola, Inc. 1995

10/95

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$" "" #"#"

High–Performance Silicon–Gate CMOS

The MC54/74HC589 is similar in function to the HC597, which is not a
3–state device. The device i nputs are compatible with standard CMOS
outputs, with pullup resistors, they are compatible with LSTTL outputs.

This device consists of an 8–bit storage latch which feeds parallel data to
an 8–bit shift register. Data can also be loaded serially (see Function Table).
The shift register output, QH, is a three–state output, allowing this device to
be used in bus–oriented systems.

The HC589 directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 526 FETs or 131.5 Equivalent Gates

LOGIC DIAGRAM

SERIAL

DATA

INPUT

14

15
1
2
3

4
5
6
7

12

11
13
10

S

A

A
B
C
D
E

F
G
H

LATCH CLOCK

SHIFT CLOCK

SERIAL SHIFT/

PARALLEL LOAD

OUTPUT ENABLE

PARALLEL

DATA

INPUTS

DATA

LATCH

SHIFT

REGISTER

VCC = PIN 16
GND = PIN 8

9

Q

H

SERIAL

DATA

OUTPUT



PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

LATCH CLOCK

SERIAL SHIFT/
PARALLEL LOAD

S

A

A

V

CC

Q

H

OUTPUT ENABLE

SHIFT CLOCK

E

D

C

B

GND

H

G

F

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD

Ceramic
Plastic
SOIC

1

16

1

16

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

1

16

MC54/74HC589

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

3–2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

P

D

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

750
500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

(Ceramic DIP)

260
300

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: –10 mW/_C from 65_ to 125_C

Ceramic DIP: –10 mW/_C from 100_ to 125_C
SOIC Package: –7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

0
0
0

1000

500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

V

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin = VIH or VIL|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

Vin = V

IH

|I

out

| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

Vin = VIH or VIL|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

4.5

6.0

0.26

0.26

0.33

0.33

0.40

0.40

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

I

OZ

Maximum Three–State Leakage
Current

Output in High–Impedance State
Vin = VIL or V

IH

V

out

= VCC or GND

6.0

± 0.5

± 5.0

± 10

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

8

80

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

V

OH

V

OL

Minimum High–Level Output
Voltage

Maximum Low–Level Output
Voltage

V

V

MC54/74HC589

High–Speed CMOS Logic Data
DL129 — Rev 6

3–3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

f

max

Maximum Clock Frequency (50% Duty Cycle)

(Figures 2 and 8)

2.0

4.5

6.0

6.0
30
35

4.8
24
28

4.0
20
24

MHz

t

PLH

,

t

PHL

Maximum Propagation Delay, Latch Clock to Q

H

(Figures 1 and 8)

2.0

4.5

6.0

210

42
36

265

53
45

315

63
54

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Shift Clock to Q

H

(Figures 2 and 8)

2.0

4.5

6.0

175

35
30

220

44
37

265

53
45

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Serial Shift/Parallel Load to Q

H

(Figures 4 and 8)

2.0

4.5

6.0

175

35
30

220

44
37

265

53
45

ns

t

PLZ

,

t

PHZ

Maximum Propagation Delay, Output Enable to Q

H

(Figures 3 and 9)

2.0

4.5

6.0

150

30
26

190

38
33

225

45
38

ns

t

PZL

,

t

PZH

Maximum Propagation Delay, Output Enable to Q

H

(Figures 3 and 9)

2.0

4.5

6.0

150

30
26

190

38
33

225

45
38

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 1 and 8)

2.0

4.5

6.0

60
12
10

75
15
13

90
18
15

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

C

out

Maximum Three–State Output Capacitance (Output in
High–Impedance State)

—

15

15

15

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

50

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

C

PD

Power Dissipation Capacitance (Per Package)*

pF

MC54/74HC589

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

3–4

TIMING REQUIREMENTS (Input t

r

= tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

t

su

Minimum Setup Time, A–H to Latch Clock

(Figure 5)

2.0

4.5

6.0

100

20
17

125

25
21

150

30
26

ns

t

su

Minimum Setup Time, Serial Data Input SA to Shift Clock

(Figure 6)

2.0

4.5

6.0

100

20
17

125

25
21

150

30
26

ns

t

su

Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock

(Figure 7)

2.0

4.5

6.0

100

20
17

125

25
21

150

30
26

ns

t

h

Minimum Hold Time, Latch Clock to A–H

(Figure 5)

2.0

4.5

6.0

25

5
5

30

6
6

40

8
7

ns

t

h

Minimum Hold Time, Shift Clock to Serial Data Input S

A

(Figure 6)

2.0

4.5

6.0

5
5
5

5
5
5

5
5
5

ns

t

w

Minimum Pulse Width, Shift Clock

(Figure 2)

2.0

4.5

6.0

80
16
14

100

20
17

120

24
20

ns

t

w

Minimum Pulse Width, Latch Clock

(Figure 1)

2.0

4.5

6.0

80
16
14

100

20
17

120

24
20

ns

t

w

Minimum Pulse Width, Serial Shift/Parallel Load

(Figure 4)

2.0

4.5

6.0

80
16
14

100

20
17

120

24
20

ns

tr, t

f

Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

1000

500
400

1000

500
400

1000

500
400

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

FUNCTION TABLE

Inputs Resulting Function

Operation

Output
Enable

Serial Shift/

Parallel Load

Latch
Clock

Shift

Clock

Serial

Input

S

A

Parallel

Inputs

A–H

Data

Latch

Contents

Shift

Register

Contents

Output

Q

H

Force output into high
impedance state

H X X X X X X X Z

Load parallel data into
data latch

L H L, H, X a–h a–h U U

Transfer latch contents to
shift register

L L L, H, X X X U LRN → SR

N

LR

H

Contents of input latch
and shift register are
unchanged

L H L, H, L, H, X X U U U

Load parallel data into
data latch and shift
register

L L X X a–h a–h a–h h

Shift serial data into shift
register

L H X D X * SRA = D,

SRN → SR

N+1

SRG → SR

H

Load parallel data in data
latch and shift serial data
into shift register

L H D a–h a–h SRA = D,

SRN → SR

N+1

SRG → SR

H

LR = latch register contents U = remains unchanged
SR = shift register contents X = don’t care
a–h = data at parallel data inputs A–H Z = high impedance
D = data (L, H) at serial data input S

A

* = depends on Latch Clock input

MC54/74HC589

High–Speed CMOS Logic Data
DL129 — Rev 6

3–5 MOTOROLA

SWITCHING WAVEFORMS

Figure 1. (Serial Shift/Parallel Load = L) Figure 2. (Serial Shift/Parallel Load = H)

LATCH CLOCK

Q

H

t

r

t

f

V

CC

GND

90%

50%

10%

t

PLH

t

PHL

t

TLH

t

THL

t

w

SHIFT CLOCK

Q

H

V

CC

GND

50%

50%

t

PLH

t

PHL

1/f

max

90%

50%
10%

t

w

Figure 3.

Q

H

Q

H

50%

50%

90%

10%

t

PZL

t

PLZ

t

PZHtPHZ

V

CC

GND
HIGH

IMPEDANCE
V

OL

V

OH

HIGH
IMPEDANCE

OUTPUT

ENABLE

50%

SERIAL SHIFT/

PARALLEL LOAD

Q

H

50%

t

PLH

50%

V

CC

GND

t

PHL

50%

t

w

Figure 4.

A–H

50%

50%

LATCH CLOCK

V

CC

GND

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

DATA VALID

t

su

t

h

S

A

50%

50%

SHIFT CLOCK

V

CC

GND

DATA VALID

t

su

t

h

SERIAL SHIFT/

PARALLEL LOAD

50%

50%

SHIFT CLOCK

V

CC

GND

t

su

Figure 5. Figure 6.

Figure 7. Figure 8. Test Circuit

MC54/74HC589

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

3–6

TEST CIRCUIT

Figure 9.

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE
UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN
TESTING t

PLZ

AND t

PZL

.
CONNECT TO GND WHEN
TESTING t

PHZ

AND t

PZH

.

1 k

Ω

PIN DESCRIPTIONS

DATA INPUTS

A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)

Parallel data inputs. Data on these inputs are stored in the

data latch on the rising edge of the Latch Clock input.

SA (Pin 14)

Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input if Serial
Shift/Parallel Load

is high. Data on this input is ignored when

Serial Shift/Parallel Load

is low.

CONTROL INPUTS

Serial Shift/Parallel Load (Pin 13)

Shift register mode control. When a high level is applied to
this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register ac­cepts parallel data from the data latch.

Shift Clock (Pin 11)

Serial shift clock. A low–to–high transition on this input
shifts data on the serial data input into the shift register and
data in stage H is shifted out QH, being replaced by the data
previously stored in stage G.

Latch Clock (Pin 12)

Data latch clock. A l ow–to–high transition on t his input
loads the parallel data on inputs A–H into the data latch.

Output Enable (Pin 10)

Active–low output enable A high level applied to this pin
forces the QH output into the high impedance state. A low
level enables the output. This control d oes not affect the
state of the input latch or the shift register.

OUTPUT
QH (Pin 9)

Serial data output. This pin is the output from the last stage
of the shift register. This is a 3–state output.

MC54/74HC589

High–Speed CMOS Logic Data
DL129 — Rev 6

3–7 MOTOROLA

TIMING DIAGRAM

SHIFT CLOCK

SERIAL DATA

INPUT, S

A

OUTPUT ENABLE

SERIAL SHIFT/

PARALLEL LOAD

LATCH CLOCK

A

B

C

D

E

F

G

H

Q

H

PARALLEL

DATA

INPUTS

SERIAL SHIFT SERIAL SHIFT SERIAL SHIFT

SERIAL

SHIFT

RESET LATCH

AND SHIFT REGISTER

LOAD LATCH PARALLEL LOAD

SHIFT REGISTER

LOAD LATCH PARALLEL LOAD

SHIFT REGISTER

PARALLEL LOAD, LATCH

AND SHIFT REGISTER

HIGH IMPEDANCE

H L H H HL L

H

L H L L L

H

L

H H

L

L

L

L

L

L

L

L

H

L

H

L

H

H

L

H

L

L

L

L

L

L

L

H

L

L

L

L

H

H

L

H

MC54/74HC589

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

3–8

PARALLEL

DATA

INPUTS

10
14

11

13

12

15

1

2

3

4

5

6

7

OUTPUT ENABLE

S

A

SHIFT CLOCK

SERIAL SHIFT/

PARALLEL LOAD

LATCH CLOCK

A

B

C

D

E

F

G

H

STAGE A

STAGE B

STAGE C*

STAGE D*

STAGE E*

STAGE F*

STAGE G*

STAGE H

V

CC

9

Q

H

DCQ

DCQ

D

C Q

S

R

D

C Q

S

R

DCQ

D

C Q

S

R

*NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.

LOGIC DETAIL

MC54/74HC589

High–Speed CMOS Logic Data
DL129 — Rev 6

3–9 MOTOROLA

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

ISSUE V

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

19.05

6.10
—

0.39

1.40

0.21

3.18

19.93

7.49

5.08

0.50

1.65

0.38

4.31

0

°

0.51

15

°

1.01

1.27 BSC

2.54 BSC

7.62 BSC

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

0.750

0.240
—

0.015

0.055

0.008

0.125

0.785

0.295

0.200

0.020

0.065

0.015

0.170

0.050 BSC

0.100 BSC

0.300 BSC

A
B
C
D
E
F
G
J
K
L
M
N

0

°

0.020

15

°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.

1 8

916

–A

–

–B

–

C

K

N

G

E

F

D 16 PL

–T

–

SEATING

PLANE

M

L

J 16 PL

0.25 (0.010) T A

M

S

0.25 (0.010) T B

M

S

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A
B
C
D
F
G
H
J
K
L
M
S

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50
0

°

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74
10

°

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295
0

°

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305
10

°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

B

1 8

916

F

H

G

D

16 PL

S

C

–T

–

SEATING
PLANE

K

J

M

L

T A0.25 (0.010)

M M

0.25 (0.010) T B A

M

S S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G
J
K
M
P
R

9.80

3.80

1.35

0.35

0.40

0.19

0.10
0

°

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

0.25
7

°

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004
0

°

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.009
7

°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

1

8

916

–A

–

–B

–

D 16 PL

K

C

G

–T

–

SEATING

PLANE

R X 45°

M

J

F

P 8 PL

0.25 (0.010) B

M M

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

MC54/74HC589

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

3–10

How to reach us:
USA/EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

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INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

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MC54/74HC589/D

*MC54/74HC589/D*

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