Page 1
SEMICONDUCTOR TECHNICAL DATA
1
REV 7
Motorola, Inc. 1996
10/96
High–Performance Silicon–Gate CMOS
The MC54/74HC573A is identical in pinout to the LS573. The devices are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes low,
data meeting the setup and hold time becomes latched.
The HC573A is identical in function to the HCT373A but has the data
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
The HC573A is the noninverting version of the HC563A.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 218 FETs or 54.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
LATCH ENABLE
OUTPUT ENABLE
11
1
9
8
7
6
5
4
3
219
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIN 20 = V
CC
PIN 10 = GND
NONINVERTING
OUTPUTS
Design Criteria
Value
ÎÎÎ
Units
Internal Gate Count*
54.5
ÎÎÎ
ea.
ОООООООО
Î
Internal Gate Propagation Delay
ÎÎ
Î
1.5
ÎÎÎ
ÎÎ
Î
ns
Internal Gate Power Dissipation
5.0
ÎÎÎ
µW
Speed Power Product
0.0075
ÎÎÎ
pJ
*Equivalent to a two–input NAND gate.
PIN ASSIGNMENT
D4
D2
D1
D0
OUTPUT
ENABLE
GND
D7
D6
D5
D3 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
V
CC
LATCH
ENABLE
Q7
Q6
Q5
Q4
FUNCTION TABLE
Inputs Output
Output Latch
Enable Enable D Q
LHHH
LHLL
L L X No Change
HXXZ
X = Don’t Care
Z = High Impedance
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
1
20
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
1
20
Page 2
MC54/74HC573A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 35
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
Î
Î
P
D
ОООООООООООО
Î
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
TSSOP Package†
ÎÎÎÎ
Î
750
500
450
Î
Î
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
Î
Î
Î
Î
T
L
ОООООООООООО
Î
ОООООООООООО
Î
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, TSSOP or SOIC Package)
(Ceramic DIP)
ÎÎÎÎ
Î
ÎÎÎÎ
Î
260
300
Î
Î
Î
Î
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: –10 mW/_C from 65_ to 125_C
Ceramic DIP: –10 mW/_C from 100_ to 125_C
SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: –6.1 mW/°C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
ÎÎ
Î
tr, t
f
ОООООООООООО
Î
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
Î
Î
0
0
0
Î
Î
1000
500
400
Î
Î
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
ÎÎ
Î
Symbol
ООООООО
Î
Parameter
ООООООО
Î
Test Conditions
ÎÎ
Î
V
CC
V
ÎÎ
– 55 to
25_C
ÎÎ
Î
v
85_C
ÎÎ
Î
v
125_C
Î
Î
Unit
ÎÎ
Î
V
IH
ООООООО
Î
Minimum High–Level Input
Voltage
ООООООО
Î
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
1.5
2.1
3.15
4.2
ÎÎ
Î
1.5
2.1
3.15
4.2
ÎÎ
Î
1.5
2.1
3.15
4.2
Î
Î
V
ÎÎ
Î
ÎÎ
Î
V
IL
ООООООО
Î
ООООООО
Î
Maximum Low–Level Input
Voltage
ООООООО
Î
ООООООО
Î
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
0.5
0.9
1.35
1.8
ÎÎ
Î
ÎÎ
Î
0.5
0.9
1.35
1 8
ÎÎ
Î
ÎÎ
Î
0.5
0.9
1.35
1.8
Î
Î
Î
Î
V
ÎÎ
Î
V
OH
ООООООО
Î
Minimum High–Level Output
Voltage
ООООООО
Î
Vin = VIH or V
IL
|I
out
| v 20 µA
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
1.9
4.4
5.9
ÎÎ
Î
1.9
4.4
5.9
ÎÎ
Î
1.9
4.4
5.9
Î
Î
V
ÎÎÎОООООООÎООООООО
Î
Vin = VIH or VIL|I
out
| ≤ 2.4mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
ÎÎ
Î
3.0
4.5
6.0
ÎÎ
2.48
3.98
5.48
ÎÎ
Î
2.34
3.84
5.34
ÎÎ
Î
2.2
3.7
5.2
Î
Î
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Page 3
MC54/74HC573A
High–Speed CMOS Logic Data
DL129 — Rev 6
3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
ÎÎ
Î
Symbol
ООООООО
Î
Parameter
ООООООО
Î
Test Conditions
ÎÎ
Î
V
CC
V
ÎÎ
– 55 to
25_C
ÎÎ
Î
v
85_C
ÎÎ
Î
v
125_C
Î
Î
Unit
ÎÎ
Î
V
OL
ООООООО
Î
Maximum Low–Level Output
Voltage
ООООООО
Î
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
0.1
0.1
0.1
ÎÎ
Î
0.1
0.1
0.1
ÎÎ
Î
0.1
0.1
0.1
Î
Î
V
ÎÎÎОООООООÎООООООО
Î
Vin = VIH or VIL|I
out
| ≤ 2.4mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
ÎÎ
Î
3.0
4.5
6.0
ÎÎ
0.26
0.26
0.26
ÎÎ
Î
0.33
0.33
0.33
ÎÎ
Î
0.4
0.4
0.4
Î
Î
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
ÎÎ
Î
I
OZ
ООООООО
Î
Maximum Three–State Leakage
Current
ООООООО
Î
Output in High–Impedance State
Vin = VIL or V
IH
V
out
= VCC or GND
ÎÎ
Î
6.0
ÎÎ
– 0.5
ÎÎ
Î
– 5.0
ÎÎ
Î
– 10
Î
Î
µA
ÎÎ
Î
I
CC
ООООООО
Î
Maximum Quiescent Supply
Current (per Package)
ООООООО
Î
Vin = VCC or GND
II
out
I = 0 µA
ÎÎ
Î
6.0
ÎÎ
4.0
ÎÎ
Î
40
ÎÎ
Î
160
Î
Î
µA
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
ÎÎ
Î
Symbol
ООООООООООООООО
Î
Parameter
ÎÎ
Î
V
CC
V
ÎÎ
– 55 to
25_C
ÎÎ
Î
v
85_C
ÎÎ
Î
v
125_C
Î
Î
Unit
ÎÎ
Î
ÎÎ
Î
t
PLH
,
t
PHL
ООООООООООООООО
Î
ООООООООООООООО
Î
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
150
100
30
26
ÎÎ
Î
ÎÎ
Î
190
140
38
33
ÎÎ
Î
ÎÎ
Î
225
180
45
38
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
PLH
,
t
PHL
ООООООООООООООО
Î
ООООООООООООООО
Î
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
160
105
32
27
ÎÎ
Î
ÎÎ
Î
200
145
40
34
ÎÎ
Î
ÎÎ
Î
240
190
48
41
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
PLZ
,
t
PHZ
ООООООООООООООО
Î
ООООООООООООООО
Î
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
150
100
30
26
ÎÎ
Î
ÎÎ
Î
190
125
38
33
ÎÎ
Î
ÎÎ
Î
225
150
45
38
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
PZL
,
t
PZH
ООООООООООООООО
Î
ООООООООООООООО
Î
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
150
100
30
26
ÎÎ
Î
ÎÎ
Î
190
125
38
33
ÎÎ
Î
ÎÎ
Î
225
150
45
38
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
TLH
,
t
THL
ООООООООООООООО
Î
ООООООООООООООО
Î
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
60
27
12
10
ÎÎ
Î
ÎÎ
Î
75
32
15
13
ÎÎ
Î
ÎÎ
Î
90
36
18
15
Î
Î
Î
Î
ns
C
in
Maximum Input Capacitance
10
10
10
pF
C
out
Maximum Three–State Output Capacitance (Output in High–Impedance State)
15
15
15
pF
NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
23
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Page 4
MC54/74HC573A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
TIMING REQUIREMENTS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
V
– 55 to 25_C
v
85_C
v
125_C
Symbol
Parameter
Fig.
V
CC
Volts
Min
Max
Min
Max
Min
ÎÎ
Max
Unit
ÎÎ
Î
ÎÎ
Î
t
su
ООООООООООО
Î
ООООООООООО
Î
Minimum Setup Time, Input D to Latch Enable
Î
Î
Î
Î
4
Î
Î
Î
Î
2.0
3.0
4.5
6.0
Î
Î
Î
Î
50
40
10
9.0
Î
Î
Î
Î
Î
Î
Î
Î
65
50
13
11
Î
Î
Î
Î
Î
Î
Î
Î
75
60
15
13
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
h
ООООООООООО
Î
ООООООООООО
Î
Minimum Hold Time, Latch Enable to Input D
Î
Î
Î
Î
4
Î
Î
Î
Î
2.0
3.0
4.5
6.0
Î
Î
Î
Î
5.0
5.0
5.0
5.0
Î
Î
Î
Î
Î
Î
Î
Î
5.0
5.0
5.0
5.0
Î
Î
Î
Î
Î
Î
Î
Î
5.0
5.0
5.0
5.0
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
t
w
ООООООООООО
Î
ООООООООООО
Î
Minimum Pulse Width, Latch Enable
Î
Î
Î
Î
2
Î
Î
Î
Î
2.0
3.0
4.5
6.0
Î
Î
Î
Î
75
60
15
13
Î
Î
Î
Î
Î
Î
Î
Î
95
80
19
16
Î
Î
Î
Î
Î
Î
Î
Î
110
90
22
19
ÎÎ
ÎÎ
ÎÎ
Î
Î
Î
Î
ns
ÎÎ
Î
ÎÎ
Î
tr, t
f
ООООООООООО
Î
ООООООООООО
Î
Maximum Input Rise and Fall Times
Î
Î
Î
Î
1
Î
Î
Î
Î
2.0
3.0
4.5
6.0
Î
Î
Î
Î
Î
Î
Î
Î
1000
800
500
400
Î
Î
Î
Î
Î
Î
Î
Î
1000
800
500
400
Î
Î
Î
Î
ÎÎ
ÎÎ
ÎÎ
1000
800
500
400
Î
Î
Î
Î
ns
Page 5
MC54/74HC573A
High–Speed CMOS Logic Data
DL129 — Rev 6
5 MOTOROLA
SWITCHING W AVEFORMS
V
CC
GND
t
f
t
r
INPUT D
Q
10%
50%
90%
10%
50%
90%
t
TLH
t
PLH
t
PHL
t
THL
OUTPUT
ENABLE
Q
Q
50%
50%
1.3 V
90%
10%
t
PZLtPLZ
t
PZHtPHZ
3.0 V
GND
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO VCC WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
1 k
Ω
Figure 1. Figure 2.
Figure 3. Figure 4.
V
CC
GND
50%
50%
LATCH
ENABLE
t
PLH
t
PHL
Q
t
w
Figure 5. Test Circuit
Figure 6. Test Circuit
EXPANDED LOGIC DIAGRAM
D
LE
Q
D0
2
19
Q0
D
LE
Q
D1
3
18
Q1
D
LE
Q
D2
4
17
Q2
D
LE
Q
D3
5
16
Q3
D
LE
Q
D4
6
15
Q4
D
LE
Q
D5
7
14
Q5
D
LE
Q
D6
8
13
Q6
D
LE
Q
D7
9
12
Q7
LATCH ENABLE
OUTPUT ENABLE
11
1
V
CC
GND
V
CC
GND
50%
50%
VALID
t
SU
t
h
INPUT D
LATCH
ENABLE
Page 6
MC54/74HC573A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
6
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 23.88 25.15 0.940 0.990
B 6.60 7.49 0.260 0.295
C 3.81 5.08 0.150 0.200
D 0.38 0.56 0.015 0.022
F 1.40 1.65 0.055 0.065
G 2.54 BSC 0.100 BSC
H 0.51 1.27 0.020 0.050
J 0.20 0.30 0.008 0.012
K 3.18 4.06 0.125 0.160
L 7.62 BSC 0.300 BSC
M 0 15 0 15
N 0.25 1.02 0.010 0.040
____
A
20
110
11
B
F
C
SEATING
PLANE
D
H
G
K
N
J
M
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J
20 PL
M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022
G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040
____
E
1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D
20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F
1.27 BSC0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
S
A
M
0.010 (0.25) B
S
T
D20X
M
B
M
0.010 (0.25)
P10X
J
F
G
18X
K
C
–T–
SEATING
PLANE
M
R
X 45
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
__
__
Page 7
MC54/74HC573A
High–Speed CMOS Logic Data
DL129 — Rev 6
7 MOTOROLA
OUTLINE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
DIMAMIN MAX MIN MAX
INCHES
6.60 0.260
MILLIMETERS
B 4.30 4.50 0.169 0.177
C 1.20 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
110
1120
PIN 1
IDENT
A
B
–T–
0.100 (0.004)
C
D
G
H
SECTION N–N
K
K1
JJ1
N
N
M
F
–W–
SEATING
PLANE
–V–
–U–
S
U
M
0.10 (0.004) V
S
T
20X REFK
L
L/2
2X
S
U0.15 (0.006) T
DETAIL E
0.25 (0.010)
DETAIL E
6.40 0.252
––– –––
S
U0.15 (0.006) T
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MC74HC573A/D
*MC74HC573A/D*
◊
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