Datasheet MC54HC573A, MC74HC573A Datasheet (MOTOROLA)

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查询MC54/74HC573A供应商



SEMICONDUCTOR TECHNICAL DATA

    

High–Performance Silicon–Gate CMOS

The MC54/74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.

The HC573A is identical in function to the HCT373A but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout.

The HC573A is the noninverting version of the HC563A.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 218 FETs or 54.5 Equivalent Gates



J SUFFIX

20

1

20

1

20

1

20

1

ORDERING INFORMATION

MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW MC74HCXXXADT

CERAMIC PACKAGE

CASE 732–03

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

DT SUFFIX

TSSOP PACKAGE

CASE 948E–02

Ceramic Plastic SOIC TSSOP

LOGIC DIAGRAM

219

D0

3

D1

4

D2

DATA

INPUTS

LATCH ENABLE

OUTPUT ENABLE

Internal Gate Count* Internal Gate Propagation Delay

ОООООООО

Internal Gate Power Dissipation Speed Power Product

*Equivalent to a two–input NAND gate.

5

D3

6

D4

7

D5

8

D6

9

D7

11 1

Design Criteria

Q0

18

Q1

17

Q2

16 15

14 13

12

PIN 20 = V PIN 10 = GND

NONINVERTING

Q3 Q4

Q5 Q6 Q7

CC

Value

54.5

1.5

ÎÎ

5.0

0.0075

OUTPUTS

Units

ea.

ns

ÎÎ

µW

pJ

PIN ASSIGNMENT

OUTPUT

ENABLE

D0 D1

D2 D3 5

D4 D5 D6 D7

GND

1 2

3 4

6 7 8 9 10

20 19

18 17 16 15 14 13 12

11

V

CC Q0 Q1

Q2 Q3

Q4 Q5 Q6 Q7

LATCH ENABLE

FUNCTION TABLE

Inputs Output

Output Latch Enable Enable D Q

LHHH LHLL L L X No Change

HXXZ

X = Don’t Care Z = High Impedance

10/96

 Motorola, Inc. 1996

1

REV 7

MC54/74HC573A

Î

MAXIMUM RATINGS*

Symbol

V

I I

Î

T

Î

DC Supply Voltage (Referenced to GND)

CC

V

DC Input Voltage (Referenced to GND)

in

DC Output Voltage (Referenced to GND)

out

I

DC Input Current, per Pin

in

DC Output Current, per Pin

out

DC Supply Current, VCC and GND Pins

CC

P

Power Dissipation in Still Air, Plastic or Ceramic DIP†

D

ОООООООООООО

Storage Temperature

stg

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

ОООООООООООО

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: –10 mW/_C from 65_ to 125_C

Ceramic DIP: –10 mW/_C from 100_ to 125_C SOIC Package: –7 mW/_C from 65_ to 125_C TSSOP Package: –6.1 mW/°C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Parameter

SOIC Package†

TSSOP Package†

(Plastic DIP, TSSOP or SOIC Package)

(Ceramic DIP)

Value

– 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5

± 20 ± 35 ± 75

750 500

ÎÎÎÎ

450

– 65 to + 150

ÎÎÎÎ

260 300

ÎÎÎÎ

Unit

V V

V mA mA mA

mW

Î

_

C

_

C

Î

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

should be constrained to the

out

range GND v (Vin or V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

) v VCC.

out

RECOMMENDED OPERATING CONDITIONS

Symbol

V

CC

Vin, V

T

A

tr, t

ÎÎ

DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND)

out

Operating Temperature, All Package Types Input Rise and Fall Time VCC = 2.0 V

f

(Figure 1) VCC = 4.5 V

ОООООООООООО

Parameter

VCC = 6.0 V

Min

2.0 0

– 55

0 0

Î

0

Max

6.0

V

CC

+ 125

1000

500

Î

400

Unit

V V

_

C

ns

Î

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

V

Symbol

ÎÎ

V

IH

ÎÎ

ООООООО

Parameter

Minimum High–Level Input Voltage

ООООООО

Test Conditions

ООООООО

V

= 0.1 V or VCC – 0.1 V

out

|I

| v 20 µA

out

ООООООО

CC

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

V

ÎÎ

V

OH

ÎÎ

ÎÎÎОООООООÎООООООО

Maximum Low–Level Input

IL

ООООООО

Voltage

ООООООО

Minimum High–Level Output Voltage

ООООООО

V

= 0.1 V or VCC – 0.1 V

out

ООООООО

|I

| v 20 µA

out

ООООООО

Vin = VIH or V |I

| v 20 µA

out

ООООООО

Vin = VIH or V

IL

IL|Iout

|I

out

|I

out

| ≤ 2.4mA | v 6.0 mA | v 7.8 mA

2.0

ÎÎ

3.0

4.5

ÎÎ

6.0

2.0

4.5

ÎÎ

6.0

3.0

4.5

ÎÎ

6.0

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

– 55 to

V

25_C

ÎÎ

1.5

2.1

ÎÎ

3.15

4.2

0.5

ÎÎ

0.9

1.35

ÎÎ

1.8

1.9

4.4

ÎÎ

5.9

2.48

3.98

ÎÎ

5.48

v

85_C

ÎÎ

1.5

2.1

ÎÎ

3.15

4.2

0.5

ÎÎ

0.9

1.35

ÎÎ

1 8

1.9

4.4

ÎÎ

5.9

2.34

3.84

ÎÎ

5.34

v

125_C

ÎÎ

1.5

2.1

ÎÎ

3.15

4.2

0.5

ÎÎ

0.9

1.35

ÎÎ

1.8

1.9

4.4

ÎÎ

5.9

2.2

3.7

ÎÎ

5.2

Î

Unit

V

MOTOROLA High–Speed CMOS Logic Data

2

DL129 — Rev 6

MC54/74HC573A

Î

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

V

ÎÎ

Symbol

V

OL

ÎÎ

ÎÎÎОООООООÎООООООО

I

in

I

OZ

ÎÎ

I

CC

ÎÎ

ООООООО

Parameter

Maximum Low–Level Output Voltage

ООООООО

Maximum Input Leakage Current Maximum Three–State Leakage

Current

ООООООО

Maximum Quiescent Supply

ООООООО

Current (per Package)

ООООООО

Test Conditions

V

= 0.1 V or VCC – 0.1 V

out

|I

| v 20 µA

out

ООООООО

Vin = VIH or V

IL|Iout

|I

| v 6.0 mA

out

|I

| v 7.8 mA

out

| ≤ 2.4mA

Vin = VCC or GND

Output in High–Impedance State

Vin = VIL or V

ООООООО

V

= VCC or GND

out

Vin = VCC or GND

ООООООО

II

I = 0 µA

out

IH

CC

ÎÎ

2.0

4.5

ÎÎ

6.0

3.0

4.5

ÎÎ

6.0

ÎÎ

6.0

ÎÎ

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

– 55 to

V

25_C

ÎÎ

0.1

ÎÎ

0.1

0.26

ÎÎ

0.26

± 0.1

– 0.5

ÎÎ

4.0

ÎÎ

v

85_C

0.1

ÎÎ

0.1

0.33

ÎÎ

0.33 ± 1.0 – 5.0

ÎÎ

40

ÎÎ

v

125_C

0.1

ÎÎ

0.1

0.4

ÎÎ

0.4

± 1.0

– 10

ÎÎ

160

ÎÎ

Î

Unit

V

µA µA

µA

AC ELECTRICAL CHARACTERISTICS (C

= 50 pF, Input tr = tf = 6.0 ns)

L

Guaranteed Limit

ÎÎ

Symbol

t

,

PLH

t

PHL

ÎÎ

t

,

PLH

t

PHL

ÎÎ

t

,

PLZ

t

PHZ

ÎÎ

t

,

PZL

t

PZH

ÎÎ

t

,

TLH

t

THL

ÎÎ

C

in

C

out

V

ООООООООООООООО

Parameter

Maximum Propagation Delay, Input D to Q

(Figures 1 and 5)

ООООООООООООООО

Maximum Propagation Delay, Latch Enable to Q

(Figures 2 and 5)

ООООООООООООООО

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ООООООООООООООО

Maximum Propagation Delay, Output Enable to Q

(Figures 3 and 6)

ООООООООООООООО

Maximum Output Transition Time, Any Output

(Figures 1 and 5)

ООООООООООООООО

CC

ÎÎ

2.0

3.0

ÎÎ

4.5

ÎÎ

6.0

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

2.0

3.0

ÎÎ

4.5

6.0

ÎÎ

Maximum Input Capacitance Maximum Three–State Output Capacitance (Output in High–Impedance State)

– 55 to

V

ÎÎ

25_C

ÎÎ

150 100

30 26

160 105

32 27

150 100

30 26

150 100

30 26

60 27 12 10

10 15

ÎÎ

v

85_C

190 140

ÎÎ

38

ÎÎ

33

200 145

ÎÎ

40 34

ÎÎ

190 125

ÎÎ

38 33

ÎÎ

190 125

ÎÎ

38 33

ÎÎ

75 32

ÎÎ

15 13

ÎÎ

10 15

ÎÎ

v

125_C

225 180

ÎÎ

45

ÎÎ

38

240 190

ÎÎ

48 41

ÎÎ

225 150

ÎÎ

45 38

ÎÎ

225 150

ÎÎ

45 38

ÎÎ

90 36

ÎÎ

18 15

ÎÎ

10 15

Î

Unit

Î

pF pF

ns

NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

C

PD

Power Dissipation Capacitance (Per Enabled Output)*

*Used to determine the no–load dynamic power consumption: PD = CPD V

Motorola High–Speed CMOS Data Book (DL129/D).

High–Speed CMOS Logic Data DL129 — Rev 6

Typical @ 25°C, VCC = 5.0 V

23

2

f + ICC VCC. For load considerations, see Chapter 2 of the

CC

pF

3 MOTOROLA

MC54/74HC573A

V

CC

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

ÎÎ

Î

TIMING REQUIREMENTS (C

Symbol

t

ÎÎ

t

ÎÎ

tr, t

ÎÎ

Minimum Setup Time, Input D to Latch Enable

su

ООООООООООО

t

Minimum Hold Time, Latch Enable to Input D

h

ООООООООООО

Minimum Pulse Width, Latch Enable

w

ООООООООООО

Maximum Input Rise and Fall Times

f

ООООООООООО

= 50 pF, Input tr = tf = 6.0 ns)

L

Parameter

Fig.

4

Î

4

Î

2

Î

1

Î

V

Volts

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

Î

4.5

6.0

Î

2.0

3.0

Î

4.5

6.0

Î

– 55 to 25_C

Min

Max

50 40

Î

10

9.0

Î

5.0

Î

5.0

Î

75 60

Î

15 13

Î

1000

800

Î

500 400

Î

Guaranteed Limit

v

85_C

Min

Max

65 50

Î

13 11

Î

5.0

Î

5.0

Î

95 80

Î

19 16

Î

1000

800

Î

500 400

Î

v

Min

75 60

Î

15 13

Î

5.0

Î

5.0

Î

110

90

Î

22 19

Î

125_C

Max

ÎÎ

1000

ÎÎ

800 500 400

Unit

ns

Î

ns

Î

ns

Î

ns

Î

MOTOROLA High–Speed CMOS Logic Data

4

DL129 — Rev 6

INPUT D

MC54/74HC573A

SWITCHING WAVEFORMS

V

t

r

90%

50%

10%

t

PLH

Q

t

TLH

90%

50%

10%

t

f

t

PHL

t

THL

V

CC

GND

LATCH

ENABLE

Q

50%

t

w

t

PLH

t

PHL

Figure 1. Figure 2.

CC

GND

OUTPUT ENABLE

DEVICE UNDER

TEST

50%

t

PZLtPLZ

Q

50%

t

PZHtPHZ

1.3 V

Figure 3. Figure 4.

TEST POINT

OUTPUT

DEVICE UNDER

TEST

*Includes all probe and jig capacitance

CL*

Figure 5. T est Circuit

TEST POINT

OUTPUT

1 k

CL*

CONNECT TO VCC WHEN

Ω

TESTING t

CONNECT TO GND WHEN

TESTING t

10%

90%

PLZ

PHZ

3.0 V

GND HIGH

IMPEDANCE V

OL

V

OH

HIGH IMPEDANCE

AND t

PZL

AND t

PZH

INPUT D

LATCH

ENABLE

50%

t

SU

VALID

50%

t

h

V

CC

GND

V

CC

GND

EXPANDED LOGIC DIAGRAM

2

D0

3

D1

4

D2

5

D3

6

D4

7

D5

.

D6

D7

8

9

D LE

Q

19

18

17

16

15

14

13

12

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

*Includes all probe and jig capacitance

Figure 6. T est Circuit

High–Speed CMOS Logic Data DL129 — Rev 6

LATCH ENABLE

OUTPUT ENABLE

5 MOTOROLA

11

1

MC54/74HC573A

OUTLINE DIMENSIONS

–T–

SEATING PLANE

CERAMIC PACKAGE

20

110

A

F

H

D

SEATING PLANE

–A–

20

1

E

FG

11

B

C

K

G

D

20 PL

N

11

J

B

10

K

N

0.25 (0.010) T

M

PLASTIC PACKAGE

J SUFFIX

CASE 732–03

ISSUE E

L

M

N SUFFIX

CASE 738–03

ISSUE E

C

M

A

L

J

20 PL

0.25 (0.010) T

NOTES:

1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

3. DIMENSIONS A AND B INCLUDE MENISCUS.

DIM MIN MAX MIN MAX

A 23.88 25.15 0.940 0.990 B 6.60 7.49 0.260 0.295 C 3.81 5.08 0.150 0.200 D 0.38 0.56 0.015 0.022 F 1.40 1.65 0.055 0.065

G 2.54 BSC 0.100 BSC

H 0.51 1.27 0.020 0.050 J 0.20 0.30 0.008 0.012 K 3.18 4.06 0.125 0.160 L 7.62 BSC 0.300 BSC

M 0 15 0 15

____

N 0.25 1.02 0.010 0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

DIM MIN MAX MIN MAX

A 25.66 27.171.010 1.070 B 6.10 6.600.240 0.260 C 3.81 4.570.150 0.180 D 0.39 0.550.015 0.022

M

B

E F G 2.54 BSC0.100 BSC J 0.21 0.380.008 0.015 K 2.80 3.550.110 0.140 L 7.62 BSC0.300 BSC

M

M 0 15 0 15 N 0.51 1.010.020 0.040

INCHESMILLIMETERS

MILLIMETERSINCHES

1.27 BSC0.050 BSC

1.27 1.770.050 0.070

____

DW SUFFIX

–A–

20

11

–B–

1

10

D20X

0.010 (0.25) B

M

S

A

T

S

PLASTIC SOIC PACKAGE

CASE 751D–04

ISSUE E

P10X

M

0.010 (0.25)

B

J

F

R

X 45

_

C

SEATING

–T–

18X

G

K

PLANE

MOTOROLA High–Speed CMOS Logic Data

M

6

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019

F 0.50 0.90 0.020 0.035

G 1.27 BSC 0.050 BSC

J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0 7 0 7

__

P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029

INCHESMILLIMETERS

__

DL129 — Rev 6

MC54/74HC573A

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948E–02

ISSUE A

20X REFK

S

U0.15 (0.006) T

0.10 (0.004) V

M

S

U

T

S

K

2X

L/2

L

PIN 1 IDENT

110

1120

B

JJ1

–U–

N

S

U0.15 (0.006) T

A

K1

SECTION N–N

0.25 (0.010)

M

–V–

N

F

DETAIL E

C

G

H

DETAIL E

0.100 (0.004)

SEATING

–T–

PLANE

D

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–.

INCHES

6.60 0.260

–W–

MILLIMETERS

DIMAMIN MAX MIN MAX

6.40 0.252

B 4.30 4.50 0.169 0.177 C 1.20 0.047

––– –––

D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030

G 0.65 BSC 0.026 BSC

H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

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MFAX: RMF AX0@email.sps.mot.com – T OUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://Design–NET .com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

High–Speed CMOS Logic Data DL129 — Rev 6

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7 MOTOROLA

*MC74HC573A/D*

MC74HC573A/D

Datasheet MC54HC573A, MC74HC573A Datasheet (MOTOROLA)

Specifications and Main Features

Frequently Asked Questions

User Manual