Page 1
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 7
Motorola, Inc. 1997
3/97
High–Performance Silicon–Gate CMOS
The MC54/74HC534A is identical in pinout to the LS534. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Data meeting the setup time is clocked, in inverted form, to the outputs
with the rising edge of the Clock. The Output Enable input does not affect the
states of the flip–flops, but when Output Enable is high, the outputs are
forced to the high impedance state. Thus, data may be stored even when the
outputs are not enabled.
The HC534A is identical in function to the HC564 which has the data
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
This device is similar in function to the HC374A, which has noninverting
outputs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 282 FETs or 68.5 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0
11
CLOCK
D1
D2
D3
D4
D5
D6
D7
18
17
14
13
8
7
4
3
1
OUTPUT ENABLE
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
16
15
12
9
6
5
2
PIN 20 = V
CC
PIN 10 = GND
INVERTING
OUTPUTS
PIN ASSIGNMENT
Q2
D1
D0
Q0
OUTPUT
ENABLE
GND
Q3
D3
D2
Q1 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q6
D6
D7
Q7
V
CC
CLOCK
Q4
D4
D5
Q5
FUNCTION TABLE
Inputs Output
Output
Enable Clock D Q
LHL
LLH
L L,H, X No Change
HXXZ
X = Don’t Care
Z = High Impedance
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Ceramic
Plastic
SOIC
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
1
20
Page 2
MC54/74HC534A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 35
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
Î
Î
P
D
ОООООООООООО
Î
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
ÎÎÎÎ
Î
750
500
Î
Î
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
Î
Î
T
L
ОООООООООООО
Î
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
ÎÎÎÎ
Î
260
300
Î
Î
_
C
*Maximum Ratings are those values beyond which damage to the device may occur .
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
ÎÎ
Î
tr, t
f
ОООООООООООО
Î
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
Î
Î
0
0
0
Î
Î
1000
500
400
Î
Î
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
ÎÎ
Î
ÎÎ
Î
V
IH
ООООООО
Î
ООООООО
Î
Minimum High–Level Input
Voltage
ООООООО
Î
ООООООО
Î
V
out
= VCC – 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
1.5
2.1
3.15
4.2
ÎÎ
Î
ÎÎ
Î
1.5
2.1
3.15
4.2
ÎÎ
Î
ÎÎ
Î
1.5
2.1
3.15
4.2
Î
Î
Î
Î
V
ÎÎ
Î
ÎÎ
Î
V
IL
ООООООО
Î
ООООООО
Î
Maximum Low–Level Input
Voltage
ООООООО
Î
ООООООО
Î
V
out
= 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
0.5
0.9
1.35
1.8
ÎÎ
Î
ÎÎ
Î
0.5
0.9
1.35
1.8
ÎÎ
Î
ÎÎ
Î
0.5
0.9
1.35
1.8
Î
Î
Î
Î
V
ÎÎ
Î
V
OH
ООООООО
Î
Minimum High–Level Output
Voltage
ООООООО
Î
Vin = V
IH
|I
out
| v 20 µA
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
1.9
4.4
5.9
ÎÎ
Î
1.9
4.4
5.9
ÎÎ
Î
1.9
4.4
5.9
Î
Î
V
ÎÎÎОООООООÎООООООО
Î
Vin = V
IH
|I
out
| v 2.4 mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
ÎÎ
Î
3.0
4.5
6.0
ÎÎ
2.48
3.98
5.48
ÎÎ
Î
2.34
3.84
5.34
ÎÎ
Î
2.2
3.7
5.2
Î
Î
ÎÎ
Î
V
OL
ООООООО
Î
Maximum Low–Level Output
Voltage
ООООООО
Î
Vin = V
IL
|I
out
| v 20 µA
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
0.1
0.1
0.1
ÎÎ
Î
0.1
0.1
0.1
ÎÎ
Î
0.1
0.1
0.1
Î
Î
V
ÎÎ
Î
ÎÎ
Î
ООООООО
Î
ООООООО
Î
ООООООО
Î
ООООООО
Î
Vin = V
IL
|I
out
| v 2.4 mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
ÎÎ
Î
ÎÎ
Î
3.0
4.5
6.0
ÎÎ
ÎÎ
0.26
0.26
0.26
ÎÎ
Î
ÎÎ
Î
0.33
0.33
0.33
ÎÎ
Î
ÎÎ
Î
0.4
0.4
0.4
Î
Î
Î
Î
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Page 3
MC54/74HC534A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Unit
v
125_C
v
85_C
– 55 to
25_C
V
CC
V
Test Conditions
Parameter
Symbol
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
ÎÎ
Î
ÎÎ
Î
I
OZ
ООООООО
Î
ООООООО
Î
Maximum Three–State Leakage
Current
ООООООО
Î
ООООООО
Î
Output in High–Impedance State
Vin = VIL or V
IH
V
out
= VCC or GND
ÎÎ
Î
ÎÎ
Î
6.0
ÎÎ
ÎÎ
± 0.5
ÎÎ
Î
ÎÎ
Î
± 5.0
ÎÎ
Î
ÎÎ
Î
± 10
Î
Î
Î
Î
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0 µA
6.0
4.0
40
160
µA
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Î
Î
Symbol
ОООООООООООООО
Î
Parameter
Î
Î
Fig.
ÎÎ
Î
V
CC
V
ÎÎ
– 55 to
25_C
ÎÎ
Î
v
85_C
ÎÎ
Î
v
125_C
Î
Î
Unit
Î
Î
Î
Î
f
max
ОООООООООООООО
Î
ОООООООООООООО
Î
Maximum Clock Frequency (50% Duty Cycle)
Î
Î
Î
Î
1, 4
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
6.0
15
30
35
ÎÎ
Î
ÎÎ
Î
5.0
10
24
28
ÎÎ
Î
ÎÎ
Î
4.0
8.0
20
24
Î
Î
Î
Î
MHz
Î
Î
Î
Î
t
PLH
t
PHL
ОООООООООООООО
Î
ОООООООООООООО
Î
Maximum Propagation Delay, Clock to Q
Î
Î
Î
Î
1, 4
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
125
80
25
21
ÎÎ
Î
ÎÎ
Î
155
110
31
26
ÎÎ
Î
ÎÎ
Î
190
130
38
32
Î
Î
Î
Î
ns
Î
Î
Î
Î
t
PLZ
t
PHZ
ОООООООООООООО
Î
ОООООООООООООО
Î
Maximum Propagation Delay, Output Enable to Q
Î
Î
Î
Î
2, 5
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
150
100
30
26
ÎÎ
Î
ÎÎ
Î
190
125
38
33
ÎÎ
Î
ÎÎ
Î
225
150
45
38
Î
Î
Î
Î
ns
Î
Î
Î
Î
t
PZL
t
PZH
ОООООООООООООО
Î
ОООООООООООООО
Î
Maximum Propagation Delay, Output Enable to Q
Î
Î
Î
Î
2, 5
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
150
100
30
26
ÎÎ
Î
ÎÎ
Î
190
125
38
33
ÎÎ
Î
ÎÎ
Î
225
150
45
38
Î
Î
Î
Î
ns
Î
Î
Î
Î
t
TLH
t
THL
ОООООООООООООО
Î
ОООООООООООООО
Î
Maximum Output Transition Time, Any Output
Î
Î
Î
Î
1, 4
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
75
27
15
13
ÎÎ
Î
ÎÎ
Î
95
32
19
16
ÎÎ
Î
ÎÎ
Î
110
36
22
19
Î
Î
Î
Î
ns
C
in
Maximum Input Capacitance
10
10
10
pF
C
OUT
Maximum Tri–State Output Capacitance (Output in Hi–Impedance State)
15
15
15
pF
NOTE:For propagation delays with loads other than 50 pF , and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Flip–Flop)*
34
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Page 4
MC54/74HC534A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–4
TIMING REQUIREMENTS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
V
– 55 to 25_C
v
85_C
v
125_C
Symbol
Parameter
Fig.
V
CC
Volts
Min
Max
Min
Max
Min
Max
Unit
Î
Î
Î
Î
t
su
ОООООООООООО
Î
ОООООООООООО
Î
Minimum Setup Time, Data to Clock
Î
Î
Î
Î
3
Î
Î
Î
Î
2.0
3.0
4.5
6.0
Î
Î
Î
Î
50
20
10
9.0
Î
Î
Î
Î
Î
Î
Î
Î
65
25
13
11
Î
Î
Î
Î
Î
Î
75
27
15
13
Î
Î
Î
Î
Î
Î
Î
Î
ns
Î
Î
Î
t
h
ОООООООООООО
Î
ОООООООООООО
Minimum Hold Time, Clock to Data
Î
Î
Î
3
Î
Î
Î
2.0
3.0
4.5
6.0
Î
Î
Î
5.0
5.0
5.0
5.0
Î
Î
Î
Î
Î
Î
5.0
5.0
5.0
5.0
Î
Î
ÎÎÎ
5.0
5.0
5.0
5.0
Î
Î
Î
Î
Î
Î
ns
Î
Î
Î
Î
t
w
ОООООООООООО
Î
ОООООООООООО
Î
Minimum Pulse Width, Clock
Î
Î
Î
Î
1
Î
Î
Î
Î
2.0
3.0
4.5
6.0
Î
Î
Î
Î
60
23
12
10
Î
Î
Î
Î
Î
Î
Î
Î
75
27
15
13
Î
Î
Î
Î
Î
Î
90
32
18
15
Î
Î
Î
Î
Î
Î
Î
Î
ns
Î
Î
Î
Î
tr, t
f
ОООООООООООО
Î
ОООООООООООО
Î
Maximum Input Rise and Fall Times
Î
Î
Î
Î
1
Î
Î
Î
Î
2.0
3.0
4.5
6.0
Î
Î
Î
Î
Î
Î
Î
Î
1000
800
500
400
Î
Î
Î
Î
Î
Î
Î
Î
1000
800
500
400
ÎÎÎ
Î
Î
Î
1000
800
500
400
Î
Î
Î
Î
ns
SWITCHING W AVEFORMS
Figure 1.
t
r
t
f
V
CC
GND
t
THL
t
TLH
90%
50%
10%
90%
50%
10%
CLOCK
t
PLH
t
PHL
Q
t
W
1/f
max
50%
50%
50%
OUTPUT
ENABLE
Q
t
PZL
t
PLZ
t
PZHtPHZ
10%
90%
V
CC
GND
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
50%
DATA
CLOCK
V
CC
V
CC
GND
GND
VALID
t
h
t
su
50%
Q
Figure 2.
Figure 3.
Page 5
MC54/74HC534A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–5 MOTOROLA
TEST CIRCUITS
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO VCC WHEN
TESTING t
PLZ
AND t
PZL
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
1 k
Ω
Figure 4. Figure 5.
EXPANDED LOGIC DIAGRAM
C
D0 D1 D2 D3 D4 D5 D6 D7
347813141718
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
256912151619
DQ
CLOCK
OUTPUT
ENABLE
11
1
C
DQCDQCDQCDQCDQCDQCDQ
Page 6
MC54/74HC534A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
3–6
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 23.88 25.15 0.940 0.990
B 6.60 7.49 0.260 0.295
C 3.81 5.08 0.150 0.200
D 0.38 0.56 0.015 0.022
F 1.40 1.65 0.055 0.065
G 2.54 BSC 0.100 BSC
H 0.51 1.27 0.020 0.050
J 0.20 0.30 0.008 0.012
K 3.18 4.06 0.125 0.160
L 7.62 BSC 0.300 BSC
M 0 15 0 15
N 0.25 1.02 0.010 0.040
____
A
20
110
11
B
F
C
SEATING
PLANE
D
H
G
K
N
J
M
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J
20 PL
M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022
G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040
____
E
1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D
20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F
1.27 BSC0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
S
A
M
0.010 (0.25) B
S
T
D20X
M
B
M
0.010 (0.25)
P10X
J
F
G
18X
K
C
–T–
SEATING
PLANE
M
R
X 45
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
__
__
Page 7
MC54/74HC534A
High–Speed CMOS Logic Data
DL129 — Rev 6
3–7 MOTOROLA
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE /Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315
Mfax: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
INTERNET: http://www.mot.com/SPS/
MC74HC534A/D
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