Datasheet MC54HC4060J, MC74HC4060DT, MC74HC4060N Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

1

REV 6

 Motorola, Inc. 1995

10/95

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High–Performance Silicon–Gate CMOS

The MC54/74HC4060 is i dentical i n pinout t o the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.

This device consists of 14 master–slave flip–flops and an oscillator with a
frequency that is controlled either by a crystal or by an RC circuit connected
externally. The output of each flip–flop feeds the next, and the frequency at
each output is half that of the preceding one. The state of the counter
advances on the negative–going edge of Osc In. The active–high Reset is
asynchronous and disables the oscillator to allow very low power consump­tion during standby operation.

State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may need to be gated with Osc Out 2 of the HC4060.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 390 FETs or 97.5 Equivalent Gates

LOGIC DIAGRAM

OSC IN

RESET

12

11

OSC OUT 1 OSC OUT 2

10 9

Q14

Q13

Q12

Q10

Q9

Q8

Q7

Q6

Q5

Q4

7
5
4

6
14
13
15

1

2

3

PIN 16 = V

CC

PIN 8 = GND



PIN ASSIGNMENT

FUNCTION TABLE

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

RESET

Q9

Q8

Q10

V

CC

OSC OUT 2

OSC OUT 1

OSC IN

Q6

Q14

Q13

Q12

GND

Q4

Q7

Q5

Clock Reset Output State

L No Change
L Advance to Next State

X H All Outputs are Low

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

1

16

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

1

16

ORDERING INFORMATION

MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXDT

Ceramic
Plastic
TSSOP

1

16

DT SUFFIX

TSSOP PACKAGE

CASE 948F–01

MC54/74HC4060

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

P

D

Power Dissipation in Still Air,Plastic or Ceramic DIP†

TSSOP Package†

750
450

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or TSSOP Package)

(Ceramic DIP)

260
300

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.5**

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

0
0
0

1000

500
400

ns

**The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested at

2.0 V by driving Pin 11 with an external clock source.

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15
4 2

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

V

V

OH

Minimum High–Level Output
Voltage (Q4–Q10, Q12–Q14)

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin = VIH or VIL|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

V

OL

Maximum Low–Level Output
Voltage (Q4–Q10, Q12–Q14)

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or VIL|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

0.26

0.26

0.33

0.33

0.40

0.40

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC54/74HC4060

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) (Continued)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

V

OH

Minimum High–Level Output
Voltage (Osc Out 1, Osc Out 2)

Vin = VCC or GND
II

out

I v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin = VCC or GNDII

out

Iv1.0 mA

II

out

Iv1.3 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

V

OL

Maximum Low–Level Output
Voltage (Osc Out 1, Osc Out 2)

Vin = VCC or GND
II

out

I v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VCC or GNDII

out

Iv1.0 mA

II

out

Iv1.3 mA

4.5

6.0

0.26

0.26

0.33

0.33

0.40

0.40

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

8

80

160

µA

NOTE: Information on typical parametric values can be found in Chapter 4.

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

f

max

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4)

2.0

4.5

6.0

5.0
25
29

4.0
20
24

3.4
17
20

MHz

t

PLH

,

t

PHL

Maximum Propagation Delay, Osc In to Q4*

(Figures 1 and 4)

2.0

4.5

6.0

530
106

91

665
133
114

795
159
135

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Osc In to Q14*

(Figures 1 and 4)

2.0

4.5

6.0

1600

320
272

2000

400
344

2400

480
408

ns

t

PHL

Maximum Propagation Delay, Reset to Any Q

(Figures 2 and 4)

2.0

4.5

6.0

240

48
41

300

60
51

360

72
61

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, QN to QN + 1

(Figures 3 and 4)

2.0

4.5

6.0

125

25
21

155

31
26

190

38
32

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 1 and 4)

2.0

4.5

6.0

75
15
13

95
19
16

110

22
19

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

*For TA = 25_C and CL = 50 pF, typical propagation delay from Osc In to other Q outputs may be calculated with the following equations:

VCC = 2.0 V: tP = [205 + 107.5(N – 1)] ns
VCC = 4.5 V: tP = [41 + 21.5(N – 1)] ns
VCC = 6.0 V: tP = [35 + 18.3(N – 1)] ns

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Package)*

35

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC4060

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

TIMING REQUIREMENTS (Input t

r

= tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

– 55 to

25_C

v

85_Cv 125_C

Unit

t

rec

Minimum Recovery Time, Reset Inactive to Osc In*

(Figure 2)

2.0

4.5

6.0

100

20
17

125

25
21

150

30
26

ns

t

w

Minimum Pulse Width, Osc In

(Figure 1)

2.0

4.5

6.0

80
16
14

100

20
17

120

24
20

ns

t

w

Minimum Pulse Width, Reset

(Figure 2)

2.0

4.5

6.0

80
16
14

100

20
17

120

24
20

ns

tr, t

f

Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

1000

500
400

1000

500
400

1000

500
400

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
*Osc In driven with external clock.

PIN DESCRIPTIONS

INPUTS

Osc In (Pin 11)

Negative–edge triggering clock input. A high–to–low tran­sition on this input advances the state of the counter. Osc In
may be driven by an external clock source.

Reset (Pin 12)

Active–high reset. A high level applied to this input asynch­ronously resets the counter to its zero state (forcing all Q out­puts low) and disables the oscillator.

OUTPUTS
Q4–Q10, Q12–Q14 (Pins 7, 5, 4, 6, 14, 13, 15, 1, 2, 3)

Active–high outputs. Each QN output divides the oscillator
frequency by 2N. The user should note that Q1, Q2, Q3, and
Q11 are not available as outputs.

Osc Out 1, Osc Out 2 (Pins 10, 9)

Oscillator outputs. These pins are used in conjunction with
Osc In and the external components to form an oscillator.
(See Figures 4 and 5). When Osc In is being driven with an
external clock source, Osc Out 1 and Osc Out 2 must be left
open circuited. With the crystal oscillator configuration in Fig­ure 6, Osc Out 2 must be left open circuited.

SWITCHING WAVEFORMS

RESET

Q

CLOCK

V

CC

GND

V

CC

GND

50%

50%

50%

t

PHL

t

rec

Figure 1.

Figure 2.

Figure 3.

OSC IN

Q1

90%

50%

10%

V

CC

GND

t

f

t

r

t

PLH

t

PHL

t

TLH

t

THL

QN

QN + 1

90%

50%

10%

V

CC

GND

50%

50%

t

PLH

t

PHL

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

t

w

1/f

max

t

w

Figure 4. Test Circuit

MC54/74HC4060

High–Speed CMOS Logic Data
DL129 — Rev 6

5 MOTOROLA

R

Q

Q

C

C

C

CRQ

Q C

CRQ

Q

R

CCQC

CRQ

Q C

CRQ

Q

RESET

EXPANDED LOGIC DIAGRAM

OSC IN

OSC OUT 1

OSC OUT 2

R

Q

Q

3

12

11

10

9

Q14

2

Q13

1

Q12

5

Q5

7

Q4

R

Q6 = PIN 4
Q7 = PIN 6
Q8 = PIN 14
Q9 = PIN 13

Q10 = PIN 15
VCC = PIN 16
GND = PIN 8

RESET

12

OSC IN 11 OSC OUT 1 10 OSC OUT 2 9

R

tc

R

S

C

tc

For 2.0 V ≤ VCC ≤ 6.0 V

10 Rtc > RS > 2 R

tc

400 Hz ≤ f ≤ 400 kHz

1

3 RtcC

tc

f ≈ (f in Hz, Rtc in ohms, Ctc in farads)

The formula may vary for other frequen­cies.

Figure 5. Oscillator Circuit Using RC Configuration

MC54/74HC4060

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

Figure 6. Pierce Crystal Oscillator Circuit

RESET

12

11 OSC IN 10 OSC OUT 1 9 OSC OUT 2

R

f

R1

C1 C2

Table 1. Crystal Oscillator Amplifier Specifications

TA = 25_C (Input = Pin 11, Output = Pin 10)

Type
Input Resistance, R

in

Output Impedance, Z

out

(4.5 V supply)

Input Capacitance, C

in

Output Capacitance, C

out

Series Capacitance, C

a

3 Vdc supply
Open loop voltage 4 Vdc supply
gain with output at 5 Vdc supply
full swing, α 6 Vdc supply

Positive Reactance (Pierce)
60 MΩ minimum
200 Ω (see text)
5 pF typical
7 pF typical
5 pF typical

5.0 expected minimum

4.0 expected minimum

3.3 expected minimum

3.1 expected minimum

PIERCE CRYSTAL OSCILLATOR DESIGN

Figure 7. Equivalent Crystal Networks

21 2121

R

S

XeRe

L

S

C

S

C

O

Values are supplied by crystal manufacturer (parallel resonant crys­tal)

Figure 8. Series Equivalent Crystal Load Figure 9. Parasitic Capacitances

of the Amplifier

NOTE: C = C1 + Cin and R = R1 + R

out

. Co is considered as part of the

load. Ca and Rf typically have minimal effect below 2 MHz.

Values are listed in Table 1.

R

s

jX

Ls

–jX

Cs

Z

load

–jX

Co

–jX

C2

–jX

C

R

R

load

X

load

C

in

C

out

C

a

MC54/74HC4060

High–Speed CMOS Logic Data
DL129 — Rev 6

7 MOTOROLA

DESIGN PROCEDURES

The following procedure applies for oscillators operating below 2 MHz where Z is a resistor R1. Above 2 MHz, additional im-

pedance elements should be considered: C

out

and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from 180_.

Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation.

– jX

Co (Rs + jXLs – jXC

s

– jX

Co + Rs + jXLs – jXC

s

Ze = = Re + jX

e

Reactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency
The maximum Rs for the crystal should be used in the equation.

Step 2: Determine β, the attenuation, of the feedback network. For a closed–loop gain of 2, Aνβ = 2,β = 2/Aν where Aν is

the gain of the HC4060 amplifier.

Step 3: Determine the manufacturer’s loading capacitance. For example: A manufacturer may specify an external load capaci-

tance of 32 pF at the required frequency.

Step 4: Determine the required Q of the system, and calculate R

load

. For example, a manufacturer specifies a crystal Q

of 100,000. In–circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then R

load

= (2πfoLs/Q) – Rs where Ls and Rs are

crystal parameters.

Step 5: Simultaneously solve, using a computer,

(with feedback phase shift = 180_)

XC • X

C2

β =

R • Re + XC2 (Xe – XC)

(1)

= X

C

load

(where the loading capacitor is an external load, not including Co)

ReXC

2

(2)

Xe = XC2 + XC +

R

(3)

RX

C

o

XC2[(XC + XC2) (XC + X

C

o

) – XC(XC + X

Co + XC2

)]

R

load

=

X

2

C2(XC

+

X

Co)

2

+ R2(XC +

X

C

o

+ XC2)

2

Here R = R

out

+ R1. R

out

is amp output resistance, R1 is Z. The C corresponding to XC is given by C = C1 + Cin.

Alternately, pick a value for R1 (i.e., let R1 = Rs). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact that

Q = 2πfoLs/(Rs + R

load

) to find in–circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure.

CHOOSING R1

Power is dissipated in the effective series resistance of the
crystal. The drive level specified by the crystal manufacturer
is the maximum stress that a crystal can withstand without
damage or excessive shift in frequency R1 limits the drive
level.

To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a func­tion of voltage at Osc Out 2 (Pin 9). The frequency should
increase very slightly as the dc supply voltage is increased.
An overdriven crystal will decrease in frequency or become
unstable with an increase in supply voltage. The operating
supply voltage must be reduced or R1 must be increased in
value it the overdriven condition exists. The user should note
that the oscillator start–up time is proportional to the value of
R1.

SELECTING R

f

The feedback resistor, Rf, typically ranges up to 20 MΩ. R

f

determines the gain and bandwidth of the amplifier. Proper
bandwidth insures oscillation at the correct frequency plus
roll–off to minimize gain at undesirable frequencies, such as

the first overtone. Rf must be large enough so as to not affect
the phase of the feedback network in an appreciable manner.

ACKNOWLEDGEMENTS AND RECOMMENDED

REFERENCES

The following publications were used in preparing this data
sheet and are hereby acknowledged and recommended for
reading:

Technical Note TN–24, Statek Corp.

Technical Note TN–7, Statek Corp.

D. Babin, “Designing Crystal Oscillators”, Machine Design,
March 7, 1985.

D. Babin, “Guidelines for Crystal Oscillator Design”,
Machine Design, April 25, 1985.

ALSO RECOMMENDED FOR READING:

E. Hafner, “The Piezoelectric Crystal Unit – Definitions and
Method of Measurement”, Proc. IEEE, Vol. 57, No. 2, Feb.

1969.

D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro–Technology, June, 1969.

P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May, 1966.

MC54/74HC4060

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

8

TIMING DIAGRAM

1 2 4 8 16 32 64 128 256 512 1024 2048

OSC IN
RESET

Q4
Q5
Q6
Q7
Q8
Q9

Q10
Q11

Q12

4096 8192 16,384

Q13
Q14

MC54/74HC4060

High–Speed CMOS Logic Data
DL129 — Rev 6

9 MOTOROLA

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

ISSUE V

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

19.05

6.10
—

0.39

1.40

0.21

3.18

19.93

7.49

5.08

0.50

1.65

0.38

4.31

0

°

0.51

15

°

1.01

1.27 BSC

2.54 BSC

7.62 BSC

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

0.750

0.240
—

0.015

0.055

0.008

0.125

0.785

0.295

0.200

0.020

0.065

0.015

0.170

0.050 BSC

0.100 BSC

0.300 BSC

A
B
C
D
E

F
G
J
K
L
M
N

0

°

0.020

15

°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.

1 8

916

–A

–

–B

–

C

KN

G

E

F

D 16 PL

–T

–

SEATING

PLANE

M

L

J 16 PL

0.25 (0.010) T A

M

S

0.25 (0.010) T B

M

S

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

A
B
C
D
F
G
H
J
K

L
M
S

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50
0

°

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74
10

°

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295
0

°

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305
10

°

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

B

1 8

916

F

H

G

D

16 PL

S

C

–T

–

SEATING
PLANE

K

J

M

L

T A0.25 (0.010)

M M

MC54/74HC4060

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

10

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

ÇÇ

ÇÇ

ÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006

F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC
M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.

_ _ _ _

SECTION N–N

SEATING
PLANE

IDENT.

PIN 1

1

8

16

9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

DETAIL E

F

M

L

2X L/2

–U–

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V

S

T

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

N

N

How to reach us:
USA/EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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MC54/74HC4060/D

*MC54/74HC4060/D*

◊

CODELINE