Datasheet MC54HC354J, MC74HC354N Datasheet (Motorola)



SEMICONDUCTOR TECHNICAL DATA

1

REV 7

 Motorola, Inc. 1995

10/95

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!! "!"!

High–Performance Silicon–Gate CMOS

The MC54/74HC354 is identical in pinout to the LS354. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.

The HC354 selects one of eight latched binary Data Inputs, as deter­mined by the Address Inputs. The information at the Data Inputs is stored
in the transparent 8–bit Data Latch when the Data–Latch Enable pin is
held high. The Address information may be stored in the transparent
Address Latch, which is enabled by the active–high Address–Enable pin.

The device outputs are placed in high–impedance states when Output
Enable 1 is high, Output Enable 2 is high, or Output Enable 3 is low.

The HC354 has a clocked Data Latch that is not transparent.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2 to 6V

• Low Input Current: 1µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance With the JEDEC Standard No. 7A Requirements

• Chip Complexity: 326 FETs or 81.5 Equivalent Gates

LOGIC DIAGRAM

D0

8

D1

7

D2

6

D3

5

D4

4

D5

3

D6

2

D7

1

8–BIT
DATA

LATCH
(TRANS–
PARENT)

8–BIT

MULTI–

PLEXER

DATA

INPUTS

3–STATE
OUTPUT

CONTROL

Y

19

Y

18

3–STATE
DATA
OUTPUTS

DATA–LATCH

ENABLE

9

A0

14

A1

13

A2

12

ADDRESS

INPUTS

ADDRESS–LATCH

ENABLE

11

OE1

15

OE2

16

OE3

17

OUTPUT

ENABLES

ADDRESS

LATCH
(TRANS–
PARENT)

PIN 20 = V

CC

PIN 10 = GND



201
192
183
174

V

CC

D7

165
156
147
138

129
1110

YD6
Y

D5

OE3D4
OE2D3
OE1D2
A0D1
A1D0
A2

Data–Latch

Enable

Address–Latch
Enable

GND

Pinout: 20–Lead Package (Top View)

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ORDERING INFORMATION

MC54HCXXXJ
MC74HCXXXN
MC74HCXXXDW

Ceramic
Plastic
SOIC

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

1

20

1

20

1

20

MC54/74HC354

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

P

D

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

750
500

mW

T

stg

Storage Temperature Range

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP or SOIC Package

Ceramic DIP

260
300

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature Range, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise/Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

0
0
0

1000

500
400

ns

DC CHARACTERISTICS (Voltages Referenced to GND)

V

Guaranteed Limit

Symbol

Parameter

Condition

V

CC
V

–55 to 25°C ≤85°C ≤125°C

Unit

V

IH

Minimum High–Level Input Voltage V

out

= 0.1V or VCC –0.1V

|I

out

| ≤ 20µA

2.0

4.5

6.0

1.50

3.15

4.20

1.50

3.15

4.20

1.50

3.15

4.20

V

V

IL

Maximum Low–Level Input Voltage V

out

= 0.1V or VCC – 0.1V

|I

out

| ≤ 20µA

2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

V

V

OH

Minimum High–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| ≤ 20µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin =VIH or V

IL

|I

out

| ≤ 6.0mA

|I

out

| ≤ 7.8mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

V

OL

Maximum Low–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| ≤ 20µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or V

IL

|I

out

| ≤ 6.0mA

|I

out

| ≤ 7.8mA

4.5

6.0

0.26

0.26

0.33

0.33

0.40

0.40

I

in

Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC54/74HC354

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol Unit

Guaranteed Limit

V

CC
V

ConditionParameter

Symbol Unit≤125°C≤85°C–55 to 25°C

V

CC
V

ConditionParameter

I

OZ

Maximum Three–State Leakage
Current

Output in High–Impedance State
Vin = VIL or V

IH

V

out

= VCC or GND

6.0 ±0.5 ±5.0 ±10.0 µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0µA

6.0 8 80 160 µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

–55 to 25°C ≤85°C ≤125°C

Unit

t

PLH

,

t

PHL

Maximum Propagation Delay, D0–D7 to Y or Y
(Figures 2 and 6)

2.0

4.5

6.0

210

42
36

265

53
45

315

63
54

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Data–Latch Enable to Y or Y
(Figures 3 and 6)

2.0

4.5

6.0

260

52
44

325

65
55

390

78
66

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, A0–A2 to Y or Y
(Figures 2 and 6)

2.0

4.5

6.0

270

54
46

340

68
58

405

81
69

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Address–Latch Enable to Y or Y
(Figures 3 and 6)

2.0

4.5

6.0

270

54
46

340

68
58

405

81
69

ns

t

PLZ

,

t

PHZ

Maximum Propagation Delay, OE1–OE3 to Y or Y
(Figures 4 and 7)

2.0

4.5

6.0

160

32
27

200

40
34

240

48
41

ns

t

PZL

,

t

PZH

Maximum Propagation Delay, OE1–OE3 to Y or Y
(Figures 4 and 7)

2.0

4.5

6.0

125

25
21

155

31
26

190

38
32

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output
(Figures 1 and 6)

2.0

4.5

6.0

60
12
10

75
15
13

90
18
15

ns

C

in

Maximum Input Capacitance 10 10 10 pF

C

out

Maximum Three–State Output Capacitance (Output in High Impedance
State)

15 15 15 pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Package)*

48

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC354

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

PIN DESCRIPTIONS

D0–D7 (Pins 8–1) DATA INPUTS

These eight data bits are stored in a transparent latch when
the Data–Latch Enable pin is active (high). Once enabled,
changing inputs will not change the contents of the latch.

A0, A1, A2 (Pins 14,13,12) ADDRESS INPUTS

Selects which data bit stored in the Data Latch is routed to
the outputs Y and Y

.

DATA–LATCH ENABLE (Pin 9)

The latch is transparent to D0–D7 when enable is inactive
(low). The Data–Latch contents are unaffected when enable
is held active (high).

ADDRESS–LATCH ENABLE (Pin 11)

The latch is transparent to A0, A1 and A2 when enable is
inactive (low). The Address–Latch contents are unaffected
when enable is held active (high).

OE1, OE2, OE3 (Pins 15,16,17) OUTPUT ENABLES

Any of the output enable pins inactive (OE1=High or
OE2=High or OE3=Low) causes the outputs (Y and Y

) to be

in high–impedance states.

Y, Y

(Pins 19,18)

These 3–state outputs (when not 3–stated) represent the
data bit in the Data Latch selected by the Address Latch.

TIMING REQUIREMENTS

(Input tr = tf = 6 ns)

V

Guaranteed Limit

Symbol Parameter

V

CC
V

–55 to 25°C ≤85°C ≤125°C Unit

t

su

Minimum Setup Time, D0–D7 to Data–Latch Enable
(Figure 5)

2.0

4.5

6.0

50
10

9

65
13
11

75
15
13

ns

t

su

Minimum Setup Time, A0–A2 to Address–Latch Enable
(Figure 5)

2.0

4.5

6.0

50
10

9

65
13
11

75
15
13

ns

t

h

Minimum Hold Time, Data–Latch Enable to D0–D7
(Figure 5)

2.0

4.5

6.0

5
5
5

5
5
5

5
5
5

ns

t

h

Minimum Hold Time, Address–Latch Enable to A0–A2
(Figure 5)

2.0

4.5

6.0

5
5
5

5
5
5

5
5
5

ns

t

w

Minimum Pulse Width, Data–Latch Enable
(Figure 3)

2.0

4.5

6.0

80
16
14

100

20
17

120

24
20

ns

t

w

Minimum Pulse Width, Address–Latch Enable
(Figure 3)

2.0

4.5

6.0

80
16
14

100

20
17

120

24
20

ns

tr, t

f

Maximum Input Rise and Fall Times
(Figure 1)

2.0

4.5

6.0

1000

500
400

1000

500
400

1000

500
400

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC354

High–Speed CMOS Logic Data
DL129 — Rev 6

5 MOTOROLA

FUNCTION TABLE

Address Latch Contents # Inputs Outputs

A2 A1 A0

Data–Latch

Enable

OE1 OE2 OE3 Y Y Description

X
X
X

X
X
X

X
X
X

X
X
X

H
X
X

X
H
X

X
X
L

Z
Z
Z

Z
Z
Z

Outputs in High–Impedance States

L
L
L
L
H
H
H
H

L

L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

L

L L H D0

D1
D2
D3
D4
D5
D6
D7

D0
D1
D2
D3
D4
D5
D6
D7

Data–Latch is Transparent

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

H

L L H D0

n

D1

n

D2

n

D3

n

D4

n

D5

n

D6

n

D7

n

D0

n

D1

n

D2

n

D3

n

D4

n

D5

n

D6

n

D7

n

New Data is Stored in Data–Latch and is
Not Alterable

# Represents bits in Address–Latch. See Address–Latch Enable pin description.
X = Don’t Care; Z = High Impedance; D0–D7 = the data at inputs D0 through D7; D0n–D7n = the data present at inputs D0 through D7 when the

Data–Latch Enable pin was taken high.

SWITCHING WAVEFORMS

Figure 1. Figure 2.

t

r

Any Input

Y or Y

V

CC

GND

90%

10%

t

f

90%

10%

t

TLH

t

THL

D0–D7

A0–A2

Y or Y

V

CC

GND

t

PHL

t

PLH

50%

50%

VALID VALID

Figure 3.

Address–

Latch Enable

Y or Y

V

CC

GND

50%

t

PLH

t

PHL

t

w

50%

Figure 4.

OE1, OE2

Y or Y

V

CC

GND

t

PZH

50%

50%

Y or Y 50%

t

PHZ

t

PZLtPLZ

High
Impedance

V

OL

V

OH

High
Impedance

OE3

10%

90%

MC54/74HC354

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

V

CC

GND

50%

D0–D7

A0–A2

V

CC

GND

50%

t

h

t

su

Valid

Data–Latch

Enable

Figure 5.

CL*

*Includes all probe and jig capacitance

TEST

POINT

DEVICE
UNDER

TEST

OUTPUT

TEST CIRCUITS

Figure 6. Figure 7.

CL*

*Includes all probe and jig capacitance

TEST

POINT

DEVICE
UNDER

TEST

OUTPUT

1k

Ω

CONNECT TO VCC WHEN
TESTING t

PLZ

AND t

PZL

.
CONNECT TO GND WHEN
TESTING t

PHZ

and t

PZH

.

MC54/74HC354

High–Speed CMOS Logic Data
DL129 — Rev 6

7 MOTOROLA

Figure 8. Expanded Logic Diagram

LE Q

D

OE1

15

OE2

16

A0

14

Q

LE Q

D

A1

13

Q

LE Q

D

A2

12

Q

LE Q

D

D0

8

LE Q

D

D1

7

LE Q

D

D2

6

LE Q

D

D3

5

LE Q

D

D4

4

LE Q

D

D5

3

LE Q

D

D6

2

LE Q

D

D7

1

OE3

17

Address–

Latch Enable

11

Data–Latch

Enable

9

Y

19

Y

18

Output

Enables

Address

Inputs

Data

Inputs

3–State
Data
Outputs

MC54/74HC354

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

8

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

ISSUE E

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ISSUE E

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

ISSUE E

NOTES:

1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSIONS A AND B INCLUDE MENISCUS.

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 23.88 25.15 0.940 0.990
B 6.60 7.49 0.260 0.295
C 3.81 5.08 0.150 0.200
D 0.38 0.56 0.015 0.022
F 1.40 1.65 0.055 0.065
G 2.54 BSC 0.100 BSC
H 0.51 1.27 0.020 0.050
J 0.20 0.30 0.008 0.012
K 3.18 4.06 0.125 0.160
L 7.62 BSC 0.300 BSC
M 0 15 0 15
N 0.25 1.02 0.010 0.040

_ _ _ _

A

20

1 10

11

B

F

C

SEATING
PLANE

D

H

G

K

N

J

M

L

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

M

L

J

20 PL

M

B

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022

G 2.54 BSC0.100 BSC

J 0.21 0.380.008 0.015

K 2.80 3.550.110 0.140

L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040

_ __ _

E

1.27 1.770.050 0.070

1

11

10

20

–A–

SEATING
PLANE

K

N

FG

D

20 PL

–T–

M

A

M

0.25 (0.010) T

E

B

C

F

1.27 BSC0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.

–A–

–B–

20

1

11

10

S

A

M

0.010 (0.25) B

S

T

D20X

M

B

M

0.010 (0.25)

P10X

J

F

G

18X

K

C

–T–

SEATING
PLANE

M

R

X 45

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019

F 0.50 0.90 0.020 0.035

G 1.27 BSC 0.050 BSC

J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029

_ _

_ _

MC54/74HC354

High–Speed CMOS Logic Data
DL129 — Rev 6

9 MOTOROLA

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