Datasheet MC-4R512FKE6D-840 Datasheet (ELPIDA)

DATA SHEET

MOS INTEGRATED CIRCUIT

MC-4R512FKE6D-840

Direct Rambus DRAM RIMMTM Module

512M-BYTE (256M-WORD x 16-BIT)

Description

The Direct Rambus RIMM module is a general-purpose high-performance memory module subsystem suitable for

use in a broad range of applications including computer memory, personal computers, workstations, and other

applications where high bandwidth and low latency are required.

MC-4R512FKE6D modules consists of sixteen 288M Direct Rambus DRAM (Direct RDRAM) devices (

These are extremely high-speed CMOS DRAMs organized as 16M words by 18 bits. The use of Rambus Signaling

Level (RSL) technology permits 600MHz, 711MHz or 800MHz transfer rates while using conventional system and

board design technologies.

Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10 ns per sixteen bytes).

The architecture of the Direct RDRAM enables the highest sustained bandwidth for multiple, simultaneous,

randomly addressed memory transactions. The separate control and data buses with independent row and column

control yield over 95 % bus efficiency. The Direct RDRAM's 32 banks support up to four simultaneous transactions

per device.

Features

PD488588).

µ

• 184 edge connector pads with 1mm pad spacing

• 512 MB Direct RDRAM storage



• Each RDRAM

• Gold plated contacts

• RDRAMs use Chip Scale Package (CSP)

• Serial Presence Detect support

• Operates from a 2.5 V supply

• Powerdown self refresh modes

• Separate Row and Column buses for higher efficiency

• Over Drive Factor (ODF) support

Document No. E0263N10 (Vert 1.0)
Date Published April 2002 (K) Japan
URL: http://www.elpida.com

has 32 banks, for 512 banks total on module

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

Elpida Memory,Inc. 2002



Order information

MC-4R512FKE6D-840

Part number Organization I/O Freq.

MHz

MC-4R512FKE6D - 840 256M x 16 800 40 184 edge connector pads RIMM 16 pieces of

with heat spreader

Edge connector : Gold plated FBGA (µBGA) package

RAS access time

ns

Package Mounted devices

PD488588FF

µ

2

Data Sheet E0263N10 (Ver 1.0)

Module Pad Configuration

MC-4R512FKE6D-840

B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46

B1
B2
B3
B4
B5
B6
B7
B8
B9

GND
LDQA7
GND
LDQA5
GND
LDQA3
GND
LDQA1
GND
LCFM
GND
LCFMN
GND
NC
GND
LROW2
GND
LROW0
GND
LCOL3
GND
LCOL1
GND
LDQB0
GND
LDQB2
GND
LDQB4
GND
LDQB6
GND
LDQB8
GND
LCMD

CMOS

V
SIN

CMOS

V
NC
GND
NC

DD

V
V

DD

NC
NC
NC
NC

GND

LDQA8

GND

LDQA6

GND

LDQA4

GND

LDQA2

GND

LDQA0

GND

LCTMN

GND

LCTM

GND

NC

GND

LROW1

GND

LCOL4

GND

LCOL2

GND

LCOL0

GND

LDQB1

GND

LDQB3

GND

LDQB5

GND

LDQB7

GND

LSCK

V

CMOS

SOUT
V

CMOS

NC

GND

NC
V
V

NC

NC

NC

NC

DD
DD

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46

Side B Side A

B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92

NC
NC
NC
NC
V

REF

GND
SA0
V

DD

SA1
SV

DD

SA2
V

DD

RCMD
GND
RDQB8
GND
RDQB6
GND
RDQB4
GND
RDQB2
GND
RDQB0
GND
RCOL1
GND
RCOL3
GND
RROW0
GND
RROW2
GND
NC
GND
RCFMN
GND
RCFM
GND
RDQA1
GND
RDQA3
GND
RDQA5
GND
RDQA7
GND

NC

NC

NC

NC

V

REF

GND

SCL

V

SDA

SV

SWP

V

RSCK

GND

RDQB7

GND

RDQB5

GND

RDQB3

GND

RDQB1

GND

RCOL0

GND

RCOL2

GND

RCOL4

GND

RROW1

GND

NC

GND

RCTM

GND

RCTMN

GND

RDQA0

GND

RDQA2

GND

RDQA4

GND

RDQA6

GND

RDQA8

GND

A47
A48
A49
A50
A51
A52
A53

DD

DD

DD

A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92

LCFM, LCFMN,

RCFM, RCFMN : Clock from master

LCTM, LCTMN,

RCTM, RCTMN : Clock to master

LCMD, RCMD : Serial Command Pad

LROW2 - LROW0,

RROW2 - RROW0 : Row bus

LCOL4 - LCOL0,

RCOL4 - RCOL0 : Column bus

LDQA8 - LDQA0,

RDQA8 - RDQA0 : Data bus A

LDQB8 - LDQB0,

RDQB8 - RDQB0 : Data bus B

LSCK, RSCK : Clock input

SA0 - SA2 : Serial Presence Detect Address

SCL, SDA : Serial Presence Detect Clock

SIN, SOUT : Serial I/O

SVDD : SPD Voltage

SWP : Serial Presence Detect Write Protect

V

: Supply voltage for serial pads

CMOS

VDD : Supply voltage

V

: Logic threshold

REF

GND : Ground reference

NC : These pads are not connected

Data Sheet E0263N10 (Ver 1.0)

3

MC-4R512FKE6D-840

Module Pad Names

Pad Signal Name Pad Signal Name Pad Signal Name Pad Signal Name

A1 GND B1 GND A47 NC B47 NC

A2 LDQA8 B2 LDQA7 A48 NC B48 NC

A3 GND B3 GND A49 NC B49 NC

A4 LDQA6 B4 LDQA5 A50 NC B50 NC

A5 GND B5 GND A51 V

A6 LDQA4 B6 LDQA3 A52 GND B52 GND

A7 GND B7 GND A53 SCL B53 SA0

A8 LDQA2 B8 LDQA1 A54 VDD B54 VDD

A9 GND B9 GND A55 SDA B55 SA1

A10 LDQA0 B10 LCFM A56 SVDD B56 SVDD

A11 GND B11 GND A57 SWP B57 SA2

A12 LCTMN B12 LCFMN A58 VDD B58 VDD

A13 GND B13 GND A59 RSCK B59 RCMD

A14 LCTM B14 NC A60 GND B60 GND

A15 GND B15 GND A61 RDQB7 B61 RDQB8

A16 NC B16 LROW2 A62 GND B62 GND

A17 GND B17 GND A63 RDQB5 B63 RDQB6

A18 LROW1 B18 LROW 0 A64 GND B64 GND

A19 GND B19 GND A65 RDQB3 B65 RDQB4

A20 LCOL4 B20 LCOL3 A66 GND B66 GND

A21 GND B21 GND A67 RDQB1 B67 RDQB2

A22 LCOL2 B22 LCOL1 A68 GND B68 GND

A23 GND B23 GND A69 RCOL0 B69 RDQB0

A24 LCOL0 B24 LDQB0 A70 GND B70 GND

A25 GND B25 GND A71 RCOL2 B71 RCOL1

A26 LDQB1 B26 LDQB2 A72 GND B72 GND

A27 GND B27 GND A73 RCOL4 B73 RCOL3

A28 LDQB3 B28 LDQB4 A74 GND B74 GND

A29 GND B29 GND A75 RROW1 B75 RROW0

A30 LDQB5 B30 LDQB6 A76 GND B76 GND

A31 GND B31 GND A77 NC B77 RROW2

A32 LDQB7 B32 LDQB8 A78 GND B78 GND

A33 GND B33 GND A79 RCTM B79 NC

A34 LSCK B34 LCMD A80 GND B80 GND

A35 V

CMOS

B35 V

CMOS

A81 RCTMN B81 RCFMN

A36 SOUT B36 SIN A82 GND B82 GND

A37 V

CMOS

B37 V

CMOS

A83 RDQA0 B83 RCFM

A38 NC B38 NC A84 GND B84 GND

A39 GND B39 GND A85 RDQA2 B85 RDQA1

A40 NC B40 NC A86 GND B86 GND

A41 VDD B41 VDD A87 RDQA4 B87 RDQA3

A42 VDD B42 VDD A88 GND B88 GND

A43 NC B43 NC A89 RDQA6 B89 RDQA5

A44 NC B44 NC A90 GND B90 GND

A45 NC B45 NC A91 RDQA8 B91 RDQA7

A46 NC B46 NC A92 GND B92 GND

REF

B51 V

REF

4

Data Sheet E0263N10 (Ver 1.0)

MC-4R512FKE6D-840

Module Connector Pad Description

Signal I/O Type Description

GND — — Ground reference for RDRAM core and interface. 72 PCB connector pads.

LCFM I RSL Clock from master. Interface clock used for receiving RSL signals from the

Channel. Positive polarity.

LCFMN I RSL Clock from master. Interface clock used for receiving RSL signals from the

Channel. Negative polarity.

LCMD I V

LCOL4..LCOL0 I RSL Column bus. 5-bit bus containing control and address information for column

LCTM I RSL Clock to master. Interface clock used for transmitting RSL signals to the

LCTMN I RSL Clock to master. Interface clock used for transmitting RSL signals to the

LDQA8..LDQA0 I/O RSL Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel

LDQB8..LDQB0 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel

LROW2..LROW0 I RSL Row bus. 3-bit bus containing control and address information for row accesses.

LSCK I V

NC — — These pads are not connected. These 24 connector pads are reserved for future

RCFM I RSL Clock from master. Interface clock used for receiving RSL signals from the

RCFMN I RSL Clock from master. Interface clock used for receiving RSL signals from the

RCMD I V

RCOL4..RCOL0 I RSL Column bus. 5-bit bus containing control and address information for column

RCTM I RSL Clock to master. Interface clock used for transmitting RSL signals to the

RCTMN I RSL Clock to master. Interface clock used for transmitting RSL signals to the

RDQA8..RDQA0 I/O RSL Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel

RDQB8..RDQB0 I/O RSL Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel

RROW2..RROW0 I RSL Row bus. 3-bit bus containing control and address information for row accesses.

Serial Command used to read from and write to the control registers. Also used

CMOS

for power management.

accesses.

Channel. Positive polarity.

Channel. Negative polarity.

and the RDRAM. LDQA8 is non-functional on modules.

and the RDRAM. LDQB8 is non-functional on modules.

Serial clock input. Clock source used to read from and write to the RDRAM

CMOS

control registers.

use.

Channel. Positive polarity.

Channel. Negative polarity.

Serial Command Input used to read from and write to the control registers. Also

CMOS

used for power management.

accesses.

Channel. Positive polarity.

Channel. Negative polarity.

and the RDRAM. RDQA8 is non-functional on modules.

and the RDRAM. RDQB8 is non-functional on modules.

(1/2)

Data Sheet E0263N10 (Ver 1.0)

5

MC-4R512FKE6D-840

(2/2)

Signal I/O Type Description

RSCK I V

Serial clock input. Clock source used to read from and write to the RDRAM

CMOS

control registers.

SA0 I SVDD Serial Presence Detect Address 0.

SA1 I SVDD Serial Presence Detect Address 1.

SA2 I SVDD Serial Presence Detect Address 2.

SCL I SVDD Serial Presence Detect Clock.

SDA I/O SVDD Serial Presence Detect Data (Open Collector I/O).

SIN I/O V

Serial I/O for reading from and writing to the control registers. Attaches to SIO0

CMOS

of the first RDRAM on the module.

SOUT I/O V

Serial I/O for reading from and writing to the control registers. Attaches to SIO1

CMOS

of the last RDRAM on the module.

SVDD — — SPD Voltage. Used for signals SCL, SDA, SWP, SA0, SA1 and SA2.

SWP I SVDD Serial Presence Detect Write Protect (active high). When low, the SPD can be

written as well as read.

V

— — CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT.

CMOS

VDD — — Supply voltage for the RDRAM core and interface logic.

REF

V

— — Logic threshold reference voltage for RSL signals.

6

Data Sheet E0263N10 (Ver 1.0)

Block Diagram

V

REF

LCMD

LSCK

SIN

LDQB 7

LDQB 8

DQB 7

DQB 8

SIO 0
SIO 1
SCK
CMD

REF

V

DQB 7

DQB 8

SIO 0
SIO 1
SCK
CMD

REF

V

LDQB 5

LDQB 6

DQB 5

DQB 6

DQB 5

DQB 6

LDQB 3

LDQB 4

DQB 3

DQB 4

DQB 3

DQB 4

LDQB 1

LDQB 2

DQB 1

DQB 2

DQB 1

DQB 2

LDQB 0

LCOL 0

COL 0

DQB 0

COL 0

DQB 0

LCOL 2

LCOL 1

COL 2

COL 1

COL 2

COL 1

LCOL 4

LCOL 3

COL 4

COL 3

COL 4

COL 3

LROW 1

LROW 0

ROW 1

ROW 0

U1

ROW 1

ROW 0

U2

LROW 2

LCTMN

CTMN

ROW 2

CTMN

ROW 2

LCTM

CTM

CTM

LCFMN

LCFM

CFM

CFMN

CFM

CFMN

LDQA 1

LDQA 0

DQA 1

DQA 0

DQA 1

DQA 0

MC-4R512FKE6D-840

LDQA 8

LDQA 7

LDQA 6

LDQA 5

LDQA 4

LDQA 3

LDQA 2

DQA 3

DQA 2

DQA 3

DQA 2

DQA 5

DQA 4

DQA 5

DQA 4

DQA 7

DQA 6

DQA 7

DQA 6

DQA 8

DQA 8

V

CMOS

V

DD

RSCK

RCMD

SOUT

DQB 7

DQB 8

SIO 0
SIO 1
SCK
CMD

REF

V

DQB 7

DQB 8

SIO 0
SIO 1
SCK
CMD

REF

V

RDQB 7

RDQB 8

DQB 5

DQB 6

DQB 5

DQB 6

RDQB 5

RDQB 6

DQB 3

DQB 4

DQB 3

DQB 4

RDQB 3

RDQB 4

DQB 1

DQB 2

DQB 1

DQB 2

RDQB 1

RDQB 2

COL 0

DQB 0

COL 0

DQB 0

RCOL 0

RDQB 0

COL 2

COL 1

COL 2

COL 1

RCOL 2

RCOL 1

COL 4

COL 3

COL 4

COL 3

RCOL 4

RCOL 3

ROW 1

ROW 0

U3

ROW 1

ROW 0

U16

RROW 1

RROW 0

SV

DD

CTMN

ROW 2

CTMN

ROW 2

RCTMN

RROW 2

CFMN

CTM

CFMN

CTM

RCFMN

RCTM

DQA 0

CFM

DQA 0

CFM

RDQA 0

RCFM

DQA 2

DQA 1

DQA 2

DQA 1

RDQA 2

RDQA 1

DQA 4

DQA 3

DQA 4

DQA 3

RDQA 4

RDQA 3

DQA 6

DQA 5

DQA 6

DQA 5

RDQA 6

RDQA 5

DQA 8

DQA 7

DQA 8

DQA 7

RDQA 8

RDQA 7

V

SCL
SWP

47 kΩ

SCL
WP

A0

SA1 SA2

SA0

SERIAL PD

CC

SDA

U0

A1 A2

SDA

Remarks 1. Rambus Channel signals form a loop through the RIMM module, with the exception of the SIO chain.

2. See Serial Presence Detection Specification for information on the SPD device and its contents.

Data Sheet E0263N10 (Ver 1.0)

7

MC-4R512FKE6D-840

Electrical Specification

Absolute Maximum Ratings

Symbol Parameter MIN. MAX. Unit

I,ABS

V

Voltage applied to any RSL or CMOS signal pad with respect to GND −0.3 V

DD,ABS

V

Voltage on V

STORE

T

Storage temperature −50 +100 °C

with respect to GND −0.5 V

DD

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

DC Recommended Electrical Conditions

Symbol Parameter and conditions MIN. MAX. Unit

V

Supply voltage 2.50 − 0.13 2.50 + 0.13 V

DD

V

CMOS I/O power supply at pad 2.5V controllers 2.5 − 0.13 2.5 + 0.25 V

CMOS

1.8V controllers 1.8 − 0.1 1.8 + 0.2

REF

V

Reference voltage 1.4 − 0.2 1.4 + 0.2 V

IL

V

RSL input low voltage V

VIH RSL input high voltage V

IL,CMOS

V

CMOS input low voltage −0.3 0.5V

IH,CMOS

V

CMOS input high voltage 0.5V

OL,CMOS

V

CMOS output low voltage, I

OH,CMOS

V

CMOS output high voltage, I

REF

I

V

SCK,CMD

I

CMOS input leakage current, (0 ≤ V

SIN,SOUT

I

CMOS input leakage current, (0 ≤ V

REF

current, V

REF,MAX

OL,CMOS

= 1 mA

OH,CMOS

= −0.25 mA V

−160.0 +160.0
≤ VDD) −160.0 +160.0

CMOS

≤ VDD) −10.0 +10.0

CMOS

REF

− 0.5 V

REF

+ 0.2 V

+0.25 V

CMOS

—

− 0.3

CMOS

+ 0.3 V

DD

+ 1.0 V

DD

REF

− 0.2 V

REF

+ 0.5 V

− 0.25 V

CMOS

+ 0.3 V

CMOS

0.3 V

—

V

A

µ

A

µ

A

µ

8

Data Sheet E0263N10 (Ver 1.0)

MC-4R512FKE6D-840

AC Electrical Specifications

Symbol Parameter and Conditions MIN. TYP. MAX. Unit
Z Module Impedance of RSL signals 25.2 28.0 30.8 Ω
Module Impedance of SCK and CMD signals 23.8 28.0 32.2

PD

T

Average clock delay from finger to f i nger of all RSL clock nets 2.11 ns

(CTM, CTMN,CFM, and CFMN)

Note1,2

PD

∆T

PD-CMOS

∆T

PD- SCK,CMD

∆T

Vα/V

VXF/V

IN

Propagation delay variation of RSL signals with respect to TPD

Propagation delay variation of SCK signal with respect to an average clock

Note1

delay

Propagation delay variation of CMD signal with respect to SCK signal −200 +200 ps

Attenuation Limit 25.0 %

IN

Forward crosstalk coeffic i ent

(300ps input rise time 20% - 80%)

IN

VXB/V

Backward crosstalk coefficient

(300ps input rise time 20% - 80%)

RDC DC Resistance Limit 1.2 Ω

−24 +24 ps

−250 +250 ps

8.0 %

2.5 %

or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,

Notes 1. T

PD

CTMN, CFM, and CFMN).

2.

If the RIMM module meets the following specification, then it is compliant to the specification.

If the RIMM module does not meet these specifications, then the specification can be adjusted by the

“Adjusted ∆TPD

Specification” table.

PD

Adjusted ∆∆∆∆T

Specification

Symbol Parameter and conditions Adjusted MIN./MAX. Absolute Unit

MIN. MAX.

PD

Propagation delay variation of RSL signals with respect to TPD

∆T

N = Number of RDRAM devices installed on the RIMM module.

Note

MIN. Z0) / (MIN. Z0)

∆Z0 = delta Z0% = (MAX. Z0

−

+/− [24+(18*N*∆Z0)]

Note

−50 50 ps

(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers

on the module.)

Data Sheet E0263N10 (Ver 1.0)

9

MC-4R512FKE6D-840

RIMM Module Current Profile

IDD

DD1

I

DD2

I

DD3

I

DD4

I

DD5

I

DD6

I

One RDRAM in Read

One RDRAM in Read

One RDRAM in Read

One RDRAM in Write, balance in NAP mode

One RDRAM in Write, balance in Standby mode

One RDRAM in Write, balance in Active mode

RIMM module power conditions

Note2

, balance in NAP mode

Note2

, balance in Standby mode

Note2

, balance in Active mode

Notes 1. Actual power will depend on individual RDRAM component specifications, memory controller and usage

patterns. Power does not include Refresh Current.

2. I/O current is a function of the % of 1’s, to add I/O power for 50 % 1’s for a x16 need to add 257 mA for the
following : V

= 2.5 V, V

DD

= 1.8 V, V

TERM

Note1

= 1.4 V and V

REF

DIL

MAX. Unit

768 mA
2055 mA
2730 mA
828 mA
2115 mA
2790 mA

= V

− 0.5 V.

REF

10

Data Sheet E0263N10 (Ver 1.0)

Package Drawings

184 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (1/2)

EEPROM

R

P

S

A (AREA B)

288 M Direct RDRAM

MC-4R512FKE6D-840

M1 (AREA B)

ON M

K

G

L

H

B

detail of A part

W

Y

X

A

A1 (AREA A)

R1.00

Q

B

I

J

M2 (AREA A)

T

FDE

C

ITEM MILLIMETERS

133.35 TYP.

A

133.35±0.13

A1

55.175

B

1.00±0.10

B1

11.50

detail of B part

C1

B1

Z

R1.00

C
C1
D
E
F
G
H
I
J
K
L
M
M1
M2
N
O
P
Q
R
S
T
W
X
Y
Z

3.00±0.10

45.00

32.00

45.00

5.675

47.625

25.40

47.625

6.35

1.00 TYP.

34.925±0.13

15.145

19.78

29.21

17.78

4.00±0.10
R 2.00

3.00±0.10

φ

2.44

1.27±0.10

0.80±0.05

2.99

0.30

2.00±0.10

ECA-TS2-0053-02

Data Sheet E0263N10 (Ver 1.0)

11

184 EDGE CONNECTOR PADS RIMM (SOCKET TYPE) (2/2)

A

MC-4R512FKE6D-840

B

E

Pad A1 Pad A92

C C
D

ITEM

A

B

C

D

E

F

G

H

DESCRIPTION
PCB length

PCB height

Center-center pad width from pad A1 to A46,
A47 to A92, B1 to B46 or B47 to B92
Spacing from PCB left edge to connector key notch

Spacing from contact pad PCB edge
to side edge retainer notch
PCB thickness

Heat spreader thickness from PCB surface (one side) to
heat spreader top surface
RIMM thickness

MIN.

133.22

34.795

44.95

-

-

1.17

-

-

TYP.

133.35

34.925

45.00

55.175

17.78

1.27

-

-

MAX.

133.48

35.055

45.05

-

-

1.37

3.09

7.55

G
H

UNIT

mm

mm

mm

mm

mm

mm

mm

mm

F

12

Data Sheet E0263N10 (Ver 1.0)

ECA-TS2-0053-02

MC-4R512FKE6D-840

CAUTION FOR HANDLING MEMORY MODULES

When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.

When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR MOS DEVICES

Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.

MDE0202

2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES

No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to V

DD

or GND with a resistor, if it is considered to have a possibility of being an output

pin. The unused pins must be handled in accordance with the related specifications.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.

CME0107

Data Sheet E0263N10 (Ver 1.0)

13

MC-4R512FKE6D-840

Rambus, RDRAM and the Rambus logo are registered trademarks of Rambus Inc.

RIMM, SO-RIMM, RaSer and QRSL are trademarks of Rambus Inc.

µµµµ

BGA is a registered trademark of Tessera, Inc.

The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.

Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.

Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.

[Product applications]

Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.

[Product usage]

Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.

[Usage environment]

This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.

If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.

If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.

M01E0107