Datasheet MC-458CA721ESA-A10, MC-458CA721ESA-A80, MC-458CA721PSA-A10 Datasheet (NEC)

A

DATA SHEET

★

★

MOS INTEGRATED CIRCUIT

MC-458CA721ESA, 458CA721PS

8M-WORD BY 72-BIT

SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)

Description

The MC-458CA721ESA and MC-458CA721PSA are 8,388,608 words by 72 bits synchronous dynamic RAM module

µ

(Small Outline DIMM) on which 5 pieces of 128M SDRAM:
These modules provide high density and large quantities of memory in a small space without utilizing the surface­mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.

Features

• 8,388,608 words by 72 bits organization (ECC type)

• Clock frequency and access time from CLK

Part number /CAS latency Clock frequency (MAX.) Access time from CLK (MAX.)

MC-458CA721ESA-A80 CL = 3 125 MHz 6 ns

CL = 2 100 MHz 6 ns

MC-458CA721ESA-A10 CL = 3 100 MHz 6 ns

CL = 2 77 MHz 7 ns

MC-458CA721PSA-A80 CL = 3 125 MHz 6 ns

CL = 2 100 MHz 6 ns

MC-458CA721PSA-A10 CL = 3 100 MHz 6 ns

CL = 2 77 MHz 7 ns

PD45128163 are assembled.

• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge

• Pulsed interface

• Possible to assert random column address in every cycle

• Quad internal banks controlled by BA0, BA1 (Bank Select)

• Programmable burst-length (1, 2, 4, 8 and Full Page)

• Programmable wrap sequence (Sequential / Interleave)

• Programmable /CAS latency (2, 3)

• Automatic precharge and controlled precharge

• CBR (Auto) refresh and self refresh

• Single 3.3 V ± 0.3 V power supply

• LVTTL compatible

• 4,096 refresh cycles/64 ms

• Burst termination by Burst Stop command and Precharge command

• 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)

• Unbuffered type

• Serial PD

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. M14494EJ2V0DS00 (2nd edition)
Date Published February 2000 NS CP(K)
Printed in Japan

The mark

••••

shows major revised points.

©

1999

MC-458CA721ESA, 458CA721PS

A

★

Ordering Information

Part number Clock frequency

MHz (MAX.)

MC-458CA721ESA-A80 125 MHz 144-pin Small Outline DIMM 5 piece of µPD45128163G5 (Rev. E)

(Socket Type) (10.16mm (400) TSOP (II))

MC-458CA721ESA-A10 100 MHz Edge connector: Gold plated

31.75 mm height

MC-458CA721PSA-A80 125 MHz 5 piece of µPD45128163G5 (Rev. P)

★

MC-458CA721PSA-A10 100 MHz

Package Mounted devices

(10.16mm (400) TSOP (II ))

2

Data Sheet M14494EJ2V0DS00

MC-458CA721ESA, 458CA721PS

A

Pin Configuration

144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Vss
DQ 32
DQ 33
DQ 34
DQ 35
Vcc
DQ 36
DQ 37
DQ 38
DQ 39
Vss
DQMB4
DQMB5
Vcc
A3
A4
A5
Vss
DQ 40
DQ 41
DQ 42
DQ 43
Vcc
DQ 44
DQ 45
DQ 46
DQ 47
Vss
CB 4
CB 5

CKE0
Vcc
/CAS
NC
NC
NC
CLK1
Vss
CB 6
CB 7
Vcc
DQ 48
DQ 49
DQ 50
DQ 51
Vss
DQ 52
DQ 53
DQ 54
DQ 55
Vcc
A7
BA0 (A13)
Vss
BA1 (A12)
A11
Vcc
DQMB6
DQMB7
Vss
DQ 56
DQ 57
DQ 58
DQ 59
Vcc
DQ 60
DQ 61
DQ 62
DQ 63
Vss
SCL
Vcc

Vss
DQ 0
DQ 1
DQ 2
DQ 3

DQ 4
DQ 5
DQ 6
DQ 7

Vss

DQMB0
DQMB1

A0
A1
A2

Vss
DQ 8
DQ 9

DQ 10
DQ 11

DQ 12
DQ 13
DQ 14
DQ 15

Vss

CB 0
CB 1

CLK0

Vcc
/RAS

/WE

/CS0

NC
NC

Vss

CB 2
CB 3

DQ 16
DQ 17
DQ 18
DQ 19

Vss

DQ 20
DQ 21
DQ 22
DQ 23

Vcc

A6
A8

Vss

A9

A10

Vcc

DQMB2
DQMB3

Vss

DQ 24
DQ 25
DQ 26
DQ 27

DQ 28
DQ 29
DQ 30
DQ 31

Vss

SDA

1
3
5
7
9

CCV

CCV

CCV

CCV

CCV

CCV

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

/xxx indicates active low signal.

A0 - A11 : Address Inputs
[Row: A0 - A11, Column: A0 - A8]
BA0(A13), BA1(A12) : SDRAM Bank Select
DQ0 - DQ63 : Data Inputs/Outputs
CB0 - CB7 : Data Inputs/Outputs
CLK0, CLK1 : Clock Input
CKE0 : Clock Enable Input
/CS0 : Chip Select Input
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQMB0 - DQMB7 : DQ Mask Enable
SDA : Serial Data I/O for PD
SCL : Clock Input for PD

CC

V

SS

V

: Power Supply
: Ground

NC : No Connection

Data Sheet M14494EJ2V0DS00

3

A

Block Diagram

DQMB0

DQMB1

/WE

/CS0

DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7

DQ 8

DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15

LDQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
UDQM
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15

/CS

MC-458CA721ESA, 458CA721PS

/WE

D0

DQMB4

DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39

DQMB5

DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47

LDQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7

UDQM
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15

/CS

/WE

D3

DQMB2

DQMB3

CB 0
CB 1
CB 2
CB 3
CB 4
CB 5
CB 6
CB 7

DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23

DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31

LDQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7

UDQM

DQ 8

DQ 9

DQ 10

DQ 11

DQ 12

DQ 13

DQ 14

DQ 15

LDQM

DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7

UDQM

DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15

/CS /WE

D1

/CS /WE

D2

DQMB6

DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55

DQMB7

DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62

DQ 63

SERIAL PD

SCL

A0 A1 A2

A0 - A11 A0 - A11 : D0 - D4

BA0 A13 : D0 - D4

BA1 A12 : D0 - D4
/RAS /RAS : D0 - D4
/CAS /CAS : D0 - D4

CKE0 CKE : D0 - D4

SDA

LDQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7

UDQM
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15

V

CC

V

SS

CLK0

CLK1

/CS

/WE

D4

D0 - D4

C

D0 - D4

CLK : D0 - D4

10 Ω

10 pF

Remarks 1.

4

D0 – D4:

2.

The value of all resistors is 10 Ω.

µ

PD45128163 (2M words x 16 bits x 4 banks)

Data Sheet M14494EJ2V0DS00

MC-458CA721ESA, 458CA721PS

A

Electrical Specifications

•All voltages are referenced to VSS (GND).

•After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper

device operation is achieved.

Absolute Maximum Ratings

Parameter Symbol Condition Rating Unit
Voltage on power supply pin relative to GND V
Voltage on input pin relative to GND V
Short circuit output c urrent I
Power dissipation P
Operating ambient tem perature T
Storage temperature T

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

CC

T

O

D

A

stg

–0.5 to +4.6 V
–0.5 to +4.6 V

50 mA

5W

0 to 70

–55 to +125

C

°

C

°

Recommended Operating Conditions

Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage V
High level input voltage V
Low level input voltage V
Operating ambient tem perature T

Capacitance (TA = 25

Input capacitance C

Data input/output capaci t ance C

C, f = 1 MHz)

°°°°

Parameter Symbol Tes t condition MI N. TYP . MAX. Unit

CC

IH

IL

A

I1

A0 - A11, BA0(A13), BA1(A12),

3.0 3.3 3.6 V

2.0 V

CC +

0.3 V

–0.3 +0.8 V

070

C

°

17 34 pF

/RAS, /CAS, /WE

I2

C
C
C
C

CLK0 23 37

I3

CKE0 18 30

I4

/CS0 18 30

I5

DQMB0 - DQMB7 5 16.5

I/O

DQ0 - DQ63, CB0 - CB7 5 13 pF

Data Sheet M14494EJ2V0DS00

5

MC-458CA721ESA, 458CA721PS

A

★

DC Characteristics (Recommended Operating Conditions unless otherwise noted)

Parameter Symbol Test condition MIN. MAX. Unit Notes

Operating current I

Precharge standby current in I
power down mode I
Precharge standby current in

non power down mode

Active standby current i n I
power down mode I
Active standby current i n

non power down mode

Operating current I

CC1

Burst length = 1, t

CC2

P CKE ≤ V

CC2

PS CKE ≤ V

CC2

I

NCKE

Input signals are changed one time during 30

CC2

I

NS CKE ≥ V

CC3

P CKE ≤ V

CC3

PS CKE ≤ V

CC3

I

NCKE

Input signals are changed one time during 30

CC3

I

NS CKE ≥ V

CC4tCK ≥ tCK(MIN.)

IL(MAX.)

IL(MAX.)

≥ VIH(MIN.)

IH(MIN.)

IL(MAX.)

IL(MAX.)

≥ VIH(MIN.)

IH(MIN.)

(Burst mode) -A10 550

★

CBR (Auto) refresh current I

Self refresh current I
Input leakage current I
Output leakage current I
High level output voltage V
Low level output voltage V

CC5tRC ≥ tRC(MIN.)

CC6

CKE ≤ 0.2 V10mA

=

I(L)

I

V

0 to 3.6 V, All other pins not under test = 0 V – 5+5µA

O(L)DOUT

OHIO = –

OLIO = +

is disabled, VO = 0 to 3.6 V –1.5 +1.5µA

4.0 mA 2.4 V

4.0 mA 0.4 V

RC ≥ tRC(MIN.)

/CAS latency = 2 -A80 550 mA 1

-A10

/CAS latency = 3 -A80 550

-A10

CK = 15

, t
, t

, t

, t
, t
, t

, t

, t

ns 5 mA

CK =

∞

CK = 15

CK =

∞

CK = 15

CK =

CK = 15

CK =

∞

∞

≥ VIH(MIN.)

ns, /CS

,

ns.

, Input signals are st abl e. 40

ns 25 mA

≥ VIH(MIN.)

ns, /CS

,

ns.

, Input signals are st abl e. 100

, IO = 0 mA /CAS latency = 2 -A80 725 mA 2

/CAS latency = 3 -A80 875

-A10 700

/CAS latency = 2 -A80 1,150 mA 3

-A10

/CAS latency = 3 -A80 1,150

-A10

5

100 mA

20

150 mA

Notes 1.

6

CC1

I

depends on output loading and cycle rates. Specified values are obtained with the output open. In

CC1

addition to this, I

CC4

2.

I

depends on output loading and cycle rates. Specified values are obtained with the output open. In

addition to this, I

CC5

3.

I

is measured on condition that addresses are changed only one time during t

is measured on condition that addresses are changed only one time during t

CC4

is measured on condition that addresses are changed only one time during t

CK(MIN.)

.

Data Sheet M14494EJ2V0DS00

CK(MIN.)

CK(MIN.)

.

.

MC-458CA721ESA, 458CA721PS

A

★

AC Characteristics (Recommended Operating Conditions unless otherwise noted)

Test Conditions

Parameter Value Unit

AC high level input voltage / low level input vol t age 2.4 / 0.4 V
Input timing m easurement reference level 1.4 V
Transition time (Input rise and fall time) 1 ns
Output timing m easurement reference level 1.4 V

t

CK

t

CLK

Input

2.4 V

1.4 V

0.4 V

2.4 V

1.4 V

0.4 V

t

SETUPtHOLD

CH

t

AC

t

OH

t

CL

Output

Data Sheet M14494EJ2V0DS00

7

MC-458CA721ESA, 458CA721PS

A

Synchronous Characteristics

Parameter Symbol -A80 -A10 Unit Note

MIN. MAX. MIN. MAX.

Clock cycle time

Access time from CLK

/CAS latency = 3

/CAS latency = 2

/CAS latency = 3
/CAS latency = 2

CLK high level width t
CLK low level width t
Data-out hold time t
Data-out low-impedance tim e t
Data-out high-impedance time

/CAS latency = 3
/CAS latency = 2

Data-in setup time t
Data-in hold time t
Address setup time t
Address hold time t
CKE setup time t
CKE hold time t
CKE setup time (P ower down exit) t
Command (/CS0, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
Command (/CS0, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time

CK3

t

CK2

t

AC3

t

AC2

t

CH

OH

HZ3

t

HZ2

t

DS

DH

AH

CKS

CKH

CKSP

CMS

t

CMH

t

8

(125 MHz) 10 (100 MHz)

ns

10 (100 MHz) 13 (77 MHz) ns

66ns1
67ns1

33

CL

33
33

LZ

00ns

ns
ns
ns

3636ns
3637ns
22ns
11ns

AS

22ns
11ns
22ns
11ns
22ns
22ns

11ns

1

Note 1.

Remark

8

Output load

Z = 50 Ω

Output

50 pF

These specifications are applied to the monolithic device.

Data Sheet M14494EJ2V0DS00

A

Asynchronous Characteristics

Parameter Symbol -A80 -A10 Unit Note

ACT to REF/ACT comm and peri od (Operat i on) t
REF to REF/ACT command period (Refresh) t
ACT to PRE command period t

PRE to ACT command period
Delay time ACT to READ/WRITE command t
ACT(one) to ACT(another) command period t
Data-in to PRE command period t
Data-in to ACT(REF) command
period (Auto precharge)
Mode register set cycle time t
Transition time t
Refresh time (4,096 refres h cycles) t

/CAS latency = 3
/CAS latency = 2

t
t

RC

RC1

RAS

RP

t

RCD

RRD

DPL

DAL3

DAL2

RSC

REF

MC-458CA721ESA, 458CA721PS

MIN. MAX. MIN. MAX.

70 70 ns
70 70 ns
48

120,000
20 20 ns
20 20 ns
16 20 ns

810ns
1CLK+20 1CLK+20 ns
1CLK+20 1CLK+20 ns

22CLK

T

0.530130ns
64 64 ms

50 120,000 ns

Data Sheet M14494EJ2V0DS00

9

MC-458CA721ESA, 458CA721PS

A

Serial PD

Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes

0 Defines the number of bytes written into

serial PD memory

1 Total number of bytes of serial PD memory 08H 0 0 0 0 1 0 0 0 256 bytes
2 Fundamental memory type 04H 0 0 0 0 0 1 0 0 SDRAM
3 Number of rows 0CH 0 0 0 0 1 1 0 0 12 rows
4 Number of columns 09H 0 0 0 0 1 0 0 1 9 columns
5 Number of banks 01H 0 0 0 0 0 0 0 1 1 bank
6 Data width 48H 0 1 0 0 1 0 0 0 72 bits
7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0
8 Voltage interface 01H 0 0 0 0 0 0 0 1 LVTTL
9 CL = 3 Cycle time -A80 80H 1 0 0 0 0 0 0 0 8 ns

-A10 A0H 1 0 1 0 0 0 0 0 10 ns

10 CL = 3 Access time -A80 60H 0 1 1 0 0 0 0 0 6 ns

-A10 60H 0 1 1 0 0 0 0 0 6 ns
11 DIMM configuration type 02H 0 0 0 0 0 0 1 0 ECC
12 Refresh rate/type 80H 1 0 0 0 0 0 0 0 Normal
13SDRAM width 10H00010000×16
14 Error checking SDRAM width 10H 0 0 0 1 0 0 0 0×16
15 Minimum clock delay 01H 0 0 0 0 0 0 0 1 1 clock
16 Burst length supported 8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F
17 Number of banks on each SDRAM 04H 0 0 0 0 0 1 0 0 4 banks
18 /CAS latency supported 06H 0 0 0 0 0 1 1 0 2, 3
19 /CS latency supported 01H 0 0 0 0 0 0 0 1 0
20 /WE latency s upported 01H 0 0 0 0 0 0 0 1 0
21 SDRAM module attributes 00H 0 0 0 0 0 0 0 0
22 SDRAM device attributes : General 0EH 0 0 0 0 1 1 1 0
23 CL = 2 Cycle time -A80 A0H 1 0 1 0 0 0 0 0 10 ns

-A10 D0H 1 1 0 1 0 0 0 0 13 ns
24 CL = 2 Access time -A80 60H 0 1 1 0 0 0 0 0 6 ns

-A10 70H 0 1 1 1 0 0 0 0 7 ns

25-26 00H 0 0 0 0 0 0 0 0

RP(MIN.)

27 t

RRD(MIN.)

28 t

RCD(MIN.)

29 t

RAS(MIN.)

30 t

31 Module bank density 10H 0 0 0 1 0 0 0 0 64M bytes

-A80 14H 0 0 0 1 0 1 0 0 20 ns

-A10 14H 0 0 0 1 0 1 0 0 20 ns

-A80 10H 0 0 0 1 0 0 0 0 16 ns

-A10 14H 0 0 0 1 0 1 0 0 20 ns

-A80 14H 0 0 0 1 0 1 0 0 20 ns

-A10 14H 0 0 0 1 0 1 0 0 20 ns

-A80 30H 0 0 1 1 0 0 0 0 48 ns

-A10 32H 0 0 1 1 0 0 1 0 50 ns

80H 1 0 0 0 0 0 0 0 128 bytes

(1/2)

10

Data Sheet M14494EJ2V0DS00

MC-458CA721ESA, 458CA721PS

A

(2/2)

Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes

32 Command and address -A80 20H 0 0 1 0 0 0 0 0 2 ns

signal setup time -A10 20H 0 0 1 0 0 0 0 0 2 ns

33 Command and address -A80 10H 0 0 0 1 0 0 0 0 1 ns

signal hold time -A10 10H 0 0 0 1 0 0 0 0 1 ns

34 Data signal input setup time -A80 20H 0 0 1 0 0 0 0 0 2 ns

-A10 20H 0 0 1 0 0 0 0 0 2 ns
35 Data signal input hold time -A80 10H 0 0 0 1 0 0 0 0 1 ns

-A10 10H 0 0 0 1 0 0 0 0 1 ns

36-61 00H 0 0 0 0 0 0 0 0

62 SPD revision -A80 12H 0 0 0 1 0 0 1 0 1.2 A

-A10 12H 0 0 0 1 0 0 1 0 1.2 A
63 Checksum -A80 01H 0 0 0 0 0 0 0 1

for bytes 0 - 62 -A10 67H 0 1 1 0 0 1 1 1

64-71 Manufacture’s JEDE C ID code

72 Manufacturing location

73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number

99-125 Mfg specific

126 Intel specification frequency -A80 64H 0 1 1 0 0 1 0 0 100 MHz

-A10 64H 0 1 1 0 0 1 0 0 100 MHz

127 Intel specification /CAS -A80 87H 1 0 0 0 0 1 1 1

latency support -A10 85H 1 0 0 0 0 1 0 1

Timing Chart

Refer to the

SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E)

Data Sheet M14494EJ2V0DS00

.

11

MC-458CA721ESA, 458CA721PS

A

★

Package Drawing

144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)

A (AREA B)

Y

M1 (AREA B)

R

Z

N

Q

M

L

M2 (AREA A)

A

H

(OPTIONAL HOLES)

C

I E

B

D

A1 (AREA A)

F

detail of A part

W

D1

D2

X

V

S

U1

U2

T

ITEM MILLIMETERS

A

67.6

A1

67.6±0.15

B

23.2
C 29.0
D

4.6
D1

1.5±0.10
D2

4.0
E

32.8
F

3.7
H

0.8 (T.P.)

I 3.3

20.0

L

M

31.75±0.15

M1

9.75

22.0

M2

N

3.8 MAX.

R2.0

Q
R

4.00±0.10

φ

S
T
U1
U2
V 0.25 MAX.

W

X
Y
Z

1.8

1.0±0.1

3.2 MIN.

4.0 MIN.

0.6±0.05

2.55 MIN.

2.0 MIN.

2.0 MIN.

M144S-80A13

12

Data Sheet M14494EJ2V0DS00

A

[MEMO]

MC-458CA721ESA, 458CA721PS

Data Sheet M14494EJ2V0DS00

13

A

[MEMO]

MC-458CA721ESA, 458CA721PS

14

Data Sheet M14494EJ2V0DS00

MC-458CA721ESA, 458CA721PS

A

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

DD

pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.

or GND with a resistor, if it is considered to have a possibility of

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

Data Sheet M14494EJ2V0DS00

15

MC-458CA721ESA, 458CA721PS

A

CAUTION FOR HANDLING MEMORY MODULES

When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.

When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.

• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.

M7 98. 8