Page 1
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4532DA727XFA
32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Description
The MC-4532DA727XFA a 33,554,432 words by 72 bits synchronous dynamic RAM module on which 18 pieces of
128M SDRAM:
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 33,554,432 words by 72 bits organization (ECC type)
• Clock frequency and access time from CLK.
PD45128441 are assembled.
µ
Part number /CAS latency Clock frequency Access time from CLK
(MAX.) (MAX.)
MC-4532DA727XFA-A75 CL = 3 133 MHz 5.4 ns
CL = 2 100 MHz 6.0 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
Interleave)
• Programmable wrap sequence (Sequential
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
% of series resistor
• All DQs have 10
• Single 3.3
• LVTTL compatible
• 4,096 refresh cycles/64
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27
• Registered type
• Serial PD
Ω ±10
V ±0.3
V power supply
ms
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
/
mm)
Document No. E0279N10 (Ver 1.0)
Date Published May 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Page 2
A
Ordering Information
MC-4532DA727XF
Part number Clock frequency
MHz (MAX.)
MC-4532DA727XFA-A75 133 MHz 168-pin Dual In-line Memory Module
(Socket Type)
Edge connector: Gold plated
30.48 mm height
Package Mounted devices
18 pieces of µPD45128441G5 (Rev. X)
(10.16mm (400) TSOP (II))
2
Data Sheet E0279N10 (Ver. 1.0)
Page 3
MC-4532DA727XF
A
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
SS
V
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
SS
V
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
CB4
CB5
SS
V
NC
NC
Vcc
/CAS
DQMB4
DQMB5
NC
/RAS
SS
V
A1
A3
A5
A7
A9
BA0
(A13)
A11
Vcc
CLK1
NC
SS
V
CKE0
NC
DQMB6
DQMB7
NC
Vcc
NC
NC
CB6
CB7
SS
V
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
REGE
SS
V
DQ53
DQ54
DQ55
SS
V
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
SS
V
CLK3
NC
SA0
SA1
SA2
Vcc
V
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
V
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
CB0
CB1
V
NC
NC
Vcc
/WE
DQMB0
DQMB1
/CS0
NC
V
A10
BA1(A12)
Vcc
Vcc
CLK0
V
NC
/CS2
DQMB2
DQMB3
NC
Vcc
NC
NC
CB2
CB3
V
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
V
DQ21
DQ22
DQ23
V
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
V
CLK2
NC
NC
SDA
SCL
Vcc
SS
SS
SS
SS
A0
A2
A4
A6
A8
SS
SS
SS
SS
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
/xxx indicates active low signal.
A0 - A11 : Address Inputs
[Row: A0 - A11, Column: A0 - A9, A11]
(A13), BA1 (A12) : SDRAM Bank Select
BA0
- DQ63, CB0 - CB7 : Data Inputs/Outputs
DQ0
CLK0 - CLK3 : Clock Input
CKE0 : Clock Enable Input
WP : Write Protect
/CS0, /CS2 : Chip Select Input
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : W rite Enable
DQMB0 - DQMB7 : DQ Mask Enable
SA0 - SA2 : Address Input for EEPROM
SDA : Serial Data I/O for PD
SCL : Clock Input for PD
CC
V
VSS
: Power Supply
: Ground
REGE : Register / Buffer Enable
NC : No Connection
Data Sheet E0279N10 (Ver. 1.0)
3
Page 4
A
Block Diagram
/RCS0
RDQMB0
DQ 3
DQ 2
DQ 1
DQ 0
DQ 7
DQ 6
DQ 5
DQ 4
RDQMB1
DQ 11
DQ 10
DQ 9
DQ 8
DQ 15
DQ 14
DQ 12
DQ 13
CB 2
CB 3
CB 0
CB 1
/RCS2
RDQMB2
DQ 18
DQ 19
DQ 17
DQ 16
DQ 23
DQ 22
DQ 21
DQ 20
RDQMB3
DQ 27
DQ 26
DQ 25
DQ 24
DQ 31
DQ 30
DQ 29
DQ 28
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQM
/CS
D0
DQM
/CS
D1
DQM
/CS
D
2
DQM
/CS
D3
DQM
/CS
D
4
DQM /CS
D5
DQM
/CS
D6
DQM
/CS
D7
DQM
/CS
D8
RDQMB4
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
RDQMB5
DQ 40
DQ 41
DQ 42
DQ 43
DQ 45
DQ 44
DQ 46
DQ 47
CB 5
CB 4
CB 7
CB 6
RDQMB6
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
RDQMB7
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQ 0
DQ 1
DQ 2
DQ 3
DQM
DQM
DQM
DQM
DQM
DQM
DQM
DQM
DQM
D
D11
D12
D
D14
D15
D16
D17
MC-4532DA727XF
/CS
D9
/CS
10
D1 - D17
V
CC
/CS
/CS
/CS
13
/CS
/CS
/CS
/CS
CLK0
V
SS
SCL
CLK1 - CLK3
10 Ω
SA0
PLL
Register1, Register2, Register3,
PLL
C
D1 - D17
Register1, Register2, Register3,
PLL
SERIAL PD
A1 A2
A0
SA1 SA2
MC-4532DA727XFA
have no this circuit.
10 Ω
12 pF
CLK : D0, D1, D9
CLK : D2, D10, D11
CLK : D3, D4, D12
CLK : D5, D13, D14
CLK : D6, D7, D15
CLK : D8, D16, D17
CLK : Register1, Register2,Register3
SDA
WP
47 kΩ
A0 - A3, A10
BA0, BA1
A4 - A9, A11
REGE
10 kΩ
/RAS
/CAS
CKE0
V
CC
Register1
/LE
Remarks 1.
The value of all resistors of DQs is 10 Ω.
2. D0 - D17:
3. REGE ≤ V
REGE ≥ V
4
RA0A - RA3A, RA10A
RBA0A, RBA1A
RA4A - RA9A, RA11A
/RRASA
/RCASA
RCKE0A
RCKE0B
PD45128441 (8M words × 4 bits × 4 banks)
µ
: Buffer mode
IL
: Register mode
IH
A0 - A3, A10 : D0 - D3, D9 - D13
BA0, BA1
A4 - A9, A11 : D4 - D8, D14 - D17
/RAS : D0 - D3, D9 - D13
/CAS : D0 - D3, D9 - D13
CKE : D0 - D4, D9 - D12
CKE : D5 - D8, D13 - D17
Data Sheet E0279N10 (Ver. 1.0)
A0 - A3,A10
BA0, BA1
A4 - A9, A11
/RAS
/CAS
DQMB0 - DQMB7
/CS0, /CS2
/WE
Register2
/LE
Register3
/LE
RA0B - RA3B, RA10B
RBA0B, RBA1B
RA4B - RA9B, RA11B
/RRASB
/RCASB
RDQMB0 - RDQMB7
/RCS0, /RCS2
/RWEA
/RWEB
/RAS : D4 - D8, D14 - D17
/CAS : D4 - D8, D14 - D17
/WE : D0 - D3, D9 - D13
CKE : D4 - D8, D14 - D17
A0 - A3, A10 : D4 - D8, D14 - D17
BA0, BA1
A4 - A9, A11 : D0 - D3, D9 - D13
Page 5
A
Electrical Specifications
MC-4532DA727XF
• All voltages are referenced to VSS
(GND).
• After power up, wait more than 1 ms and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Voltage on power supply pin relative to GND VCC –0.5 to +4.6 V
Voltage on input pin relative to GND VT –0.5 to +4.6 V
Short circuit output current IO 50 mA
Power dissipation PD 22 W
Operating ambient temperature T
Storage temperature T
A
0 to 70 °C
stg
–55 to +125 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage VCC 3.0 3.3 3.6 V
High level input voltage VIH 2.0 V
Low level input voltage VIL –0.3 + 0.8 V
Operating ambient temperature T
A
0 70 °C
CC +
0.3 V
°°°°C, f = 1 MHz)
Capacitance (TA = 25
Input capacitance CI1 A0 - A11, BA0 (A13), BA1 (A12),
C
C
C
C
Data input/output capacitance C
Parameter Symbol Test condition MIN. TYP. MAX. Unit
7 20 pF
/RAS, /CAS, /WE
I2
CLK0 15 25
I3
CKE0 7 20
I4
/CS0, /CS2 4 10
I5
DQMB0 - DQMB7 3 12
I/O
DQ0 - DQ63, CB0 - CB7 5 13 pF
Data Sheet E0279N10 (Ver. 1.0)
5
Page 6
MC-4532DA727XF
A
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test condition Grade MIN. MAX. Unit Notes
Operating current I
t
Precharge standby current in I
power down mode I
Precharge standby current in I
CC1
Burst length = 1 /CAS latency = 2 -A75 2,200 mA 1
CC2
P CKE ≤ V
CC2
PS CKE ≤ V
CC2
N CKE ≥
RC ≥ tRC (MIN.)
, IO = 0 mA /CAS latency = 3 -A75 2,290
IL (MAX.)
, tCK = 15 ns 268 mA
IL (MAX.)
CK
, t
= ∞ 98
VIH (MIN.)
, tCK = 15 ns, /CS
≥ VIH (MIN.)
, 610 mA
non power down mode Input signals are changed one time during 30 ns.
I
Active standby current in I
power down mode I
Active standby current in I
CC2
NS CKE ≥
CC3
P CKE ≤ V
CC3
PS CKE ≤ V
CC3
N CKE ≥
VIH (MIN.)
VIH (MIN.)
CK
, t
= ∞, Input signals are stable. 224
IL (MAX.)
, tCK = 15 ns 340 mA
IL (MAX.)
CK
, t
= ∞ 152
, tCK = 15
ns, /CS ≥
VIH (MIN.)
, 790 mA
non power down mode Input signals are changed one time during 30 ns.
I
Operating current I
CC3
NS CKE ≥
CC4
t
VIH (MIN.)
CK ≥ tCK (MIN.)
CK
, t
= ∞, Input signals are stable. 440
, IO = 0 mA /CAS latency = 2 -A75 2,290 mA 2
(Burst mode) /CAS latency = 3 -A75 2,920
CC5
CBR (Auto) Refresh current I
RC ≥ tRC (MIN.)
t
/CAS latency = 2 -A75 4,540 mA 3
/CAS latency = 3 -A75 4,720
Self refresh current I
Input leakage current I
Output leakage current I
CC6
CKE ≤ 0.2
I (L)
VI = 0 to 3.6 V, All other pins not under test = 0 V –20 +20 µA
O (L)
OUT
D
V 286 mA
is disabled, VO = 0 to 3.6 V –1.5 +1.5 µA
High level output voltage VOH IO = –4.0 mA 2.4 V
Low level output voltage VOL IO = +4.0 mA 0.4 V
Notes 1.
2. I
3. I
I
depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
addition to this, ICC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC4
addition to this, ICC4
is measured on condition that addresses are changed only one time during t
CC5
is measured on condition that addresses are changed only one time during t
is measured on condition that addresses are changed only one time during t
.
CK (MIN.)
CK (MIN.)
CK (MIN.)
.
.
6
Data Sheet E0279N10 (Ver. 1.0)
Page 7
MC-4532DA727XF
A
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Test Conditions
Parameter Value Unit
AC high level input voltage / low level input voltage 2.4 / 0.4 V
Input timing measurement reference level 1.4 V
Transition time (Input rise and fall time) 1 ns
Output timing measurement reference level 1.4 V
t
CK
t
CLK
Input
2.4 V
1.4 V
0.4 V
2.4 V
1.4 V
0.4 V
t
SETUPtHOLD
CH
t
AC
t
OH
t
CL
Output
Data Sheet E0279N10 (Ver. 1.0)
7
Page 8
A
Synchronous Characteristics
Parameter Symbol -A75 Unit Note
MIN. MAX.
MC-4532DA727XF
Clock cycle time /CAS latency = 3 t
/CAS latency = 2 t
Access time from CLK /CAS latency = 3 t
/CAS latency = 2 t
CK3
7.5 (133 MHz) ns
CK2
10 (100 MHz) ns
AC3
5.4 ns 1
AC2
6.0 ns 1
Input clock frequency 50 133 MHz
Input CLK duty cycle 45 55 %
Data-out hold time tOH 2.7 ns 1
Data-out low-impedance time tLZ 0 ns
Data-out high-impedance time /CAS latency = 3 t
/CAS latency = 2 t
HZ3
3.0 5.4 ns
HZ2
3.0 6.0 ns
Data-in setup time tDS 1.5 ns
Data-in hold time tDH 0.8 ns
Address setup time tAS 1.5 ns
Address hold time tAH 0.8 ns
CKE setup time t
CKE hold time t
CKE setup time (Power down exit) t
Command (/CS0, /CS2, /RAS, /CAS, /WE, t
CKS
1.5 ns
CKH
0.8 ns
CKSP
1.5 ns
CMS
1.5 ns
DQMB0 - DQMB7) setup time
Command (/CS0, /CS2, /RAS, /CAS, /WE, t
CMH
0.8 ns
DQMB0 - DQMB7) hold time
Note 1.
Output load
Z = 50 Ω
Output
Remark These specifications are applied to the monolithic device.
50 pF
8
Data Sheet E0279N10 (Ver. 1.0)
Page 9
MC-4532DA727XF
A
Asynchronous Characteristics
Parameter Symbol -A 75 Unit Note
MIN. MAX.
ACT to REF/ACT command period (operation) tRC 67.5 ns
REF to REF/ACT command period (refresh) t
ACT to PRE command period t
PRE to ACT command period tRP 20 ns
Delay time ACT to READ/WRITE command t
ACT(one) to ACT(another) command period t
Data-in to PRE command period t
Data-in to ACT(REF) command /CAS latency = 3 t
period (Auto precharge) /CAS latency = 2 t
Mode register set cycle time t
Transition time tT 0.5 30 ns
Refresh time (4,096 refresh cycles) t
RC1
67.5 ns
RAS
45 120,000 ns
RCD
20 ns
RRD
15 ns
DPL
8 ns
DAL3
1CLK+22.5 ns 1
DAL2
1CLK+20 ns
RSC
2 CLK
REF
64 ms
Note 1. This device can satisfy the t
spec of 1CLK+20 ns for up to and including 125 MHz operation.
DAL3
Data Sheet E0279N10 (Ver. 1.0)
9
Page 10
MC-4532DA727XF
A
Serial PD (1/2)
Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
0 Defines the number of bytes written into
serial PD memory
1 Total number of bytes of serial PD memory 08H 0 0 0 0 1 0 0 0 256 bytes
2 Fundamental memory type 04H 0 0 0 0 0 1 0 0 SDRAM
3 Number of rows 0CH 0 0 0 0 1 1 0 0 12 rows
4 Number of columns 0BH 0 0 0 0 1 0 1 1 11 columns
5 Number of banks 01H 0 0 0 0 0 0 0 1 1 bank
6 Data width 48H 0 1 0 0 1 0 0 0 72 bits
7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0
8 Voltage interface 01H 0 0 0 0 0 0 0 1 LVTTL
9 CL = 3 Cycle time -A75 75H 0 1 1 1 0 1 0 1 7.5 ns
10 CL = 3 Access time -A75 54H 0 1 0 1 0 1 0 0 5.4 ns
11 DIMM configuration type 02H 0 0 0 0 0 0 1 0 ECC
12 Refresh rate/type 80H 1 0 0 0 0 0 0 0 Normal
13 SDRAM width 04H 0 0 0 0 0 1 0 0 ×4
14 Error checking SDRAM width 04H 0 0 0 0 0 1 0 0 ×4
15 Minimum clock delay 01H 0 0 0 0 0 0 0 1 1 clock
16 Burst length supported 8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F
17 Number of banks on each SDRAM 04H 0 0 0 0 0 1 0 0 4 banks
18 /CAS latency supported 06H 0 0 0 0 0 1 1 0 2, 3
19 /CS latency supported 01H 0 0 0 0 0 0 0 1 0
20 /WE latency supported 01H 0 0 0 0 0 0 0 1 0
21 SDRAM module attributes 1FH 0 0 0 1 1 1 1 1 Registered
22 SDRAM device attributes : General 0EH 0 0 0 0 1 1 1 0
23 CL = 2 Cycle time -A75 A0H 1 0 1 0 0 0 0 0 10 ns
24 CL = 2 Access time -A75 60H 0 1 1 0 0 0 0 0 6 ns
25-26 00H 0 0 0 0 0 0 0 0
RP(MIN.)
27 t
28 t
29 t
30 t
31 Module bank density 40H 0 1 0 0 0 0 0 0 256M bytes
-A75 14H 0 0 0 1 0 1 0 0 20 ns
RRD(MIN.)
-A75 0FH 0 0 0 0 1 1 1 1 15 ns
RCD(MIN.)
-A75 14H 0 0 0 1 0 1 0 0 20 ns
RAS(MIN.)
-A75 2DH 0 0 1 0 1 1 0 1 45 ns
80H 1 0 0 0 0 0 0 0 128 bytes
10
Data Sheet E0279N10 (Ver. 1.0)
Page 11
MC-4532DA727XF
A
Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
32 Command and address signal input
setup time
33 Command and address signal input hold
time
34 Data signal input setup time 15H 0 0 0 1 0 1 0 1 1.5 ns
35 Data signal input hold time 08H 0 0 0 0 1 0 0 0 0.8 ns
36-61 00H 0 0 0 0 0 0 0 0
62 SPD revision 02H 0 0 0 0 0 0 1 0 JEDEC 2
63 Checksum for bytes 0 - 62 -A75 E9H 1 1 1 0 1 0 0 1
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91 Revision Code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126 Intel specification frequency 64H 0 1 1 0 0 1 0 0 100 MHz
127 Intel specification /CAS -A75 85H 1 0 0 0 0 1 0 1
latency support
15H 0 0 0 1 0 1 0 1 1.5 ns
08H 0 0 0 0 1 0 0 0 0.8 ns
(2/2)
Timing Chart
Refer to the µµµµPD45128441, 45128841, 45128163 Data sheet (E0031N).
Data Sheet E0279N10 (Ver. 1.0)
11
Page 12
A
Package Drawing
MC-4532DA727XFA
Front side
3.00
3.00
1 84
11.43
133.35
(DATUM -A-)
(63.67)
Component area
(Front)
C
36.83 54.61
MC-4532DA727XF
4.00 max
4.00 min
AB
1.27
Unit: mm
Back side
2 – φ 3.00
85
4.00
Detail A
1.27
2.50 ± 0.20
1.00 ± 0.05
Note: Tolerance on all dimensions ± 0.15 unless otherwise specified.
127.35
Component area
(Back)
(DATUM -A-)
Detail B Detail C
R FULL
0.20 ± 0.15
3.125 ± 0.125
(DATUM -A-)
6.35 6.35
2.00 ± 0.10 4.175
168
1.00
3.125 ± 0.125
17.80
30.48
R FULL
2.00 ± 0.10
ECA-TS2-0027-01
12
Data Sheet E0279N10 (Ver. 1.0)
Page 13
MC-4532DA727XF
A
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to V
DD
or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
MDE0202
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
Data Sheet E0279N10 (Ver. 1.0)
CME0107
13
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MC-4532DA727XF
A
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[Usage environment]
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M01E0107
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