Datasheet MC-4516CD64PS-A10B Datasheet (NEC)

DATA SHEET

★

MOS INTEGRATED CIRCUIT

MC-4516CD64ES, 4516CD64PS

16 M-WORD BY 64-BIT

SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)

Description

The MC-4516CD64ES and MC-4516CD64PS are 16,777,216 words by 64 bits synchronous dynamic RAM module
(Small Outline DIMM) on which 8 pieces of 128 M SDRAM: µPD45128163 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface­mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.

Features

• 16,777,216 words by 64 bits organization

• Clock frequency and access time from CLK

Part number /CAS latency Clock frequency (MAX.) Access time from CLK (MAX.)

MC-4516CD64ES-A10B CL = 3 100 MHz 7 ns

CL = 2 67 MHz 8 ns

MC-4516CD64PS-A10B CL = 3 100 MHz 7 ns

CL = 2 67 MHz 8 ns

• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge

• Pulsed interface

• Possible to assert random column address in every cycle

• Quad internal banks controlled by BA0, BA1 (Bank Select)

• Programmable burst-length (1, 2, 4, 8 and Full Page)

• Programmable wrap sequence (Sequential / Interleave)

• Programmable /CAS latency (2, 3)

• Automatic precharge and controlled precharge

• CBR (Auto) refresh and self refresh

• Single 3.3 V ± 0.3 V power supply

• LVTTL compatible

• 4,096 refresh cycles/64 ms

• Burst termination by Burst Stop command and Precharge command

• 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)

• Unbuffered type

• Serial PD

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. M13612EJ5V0DS00 (5th edition)
Date Published February 2000 NS CP(K)
Printed in Japan

The mark

••••

shows major revised points.

©

1998

Ordering Information

★

MC-4516CD64ES, 4516CD64PS

Part number Clock frequency

MHz (MAX.)

MC-4516CD64ES-A10B 100 MHz 144-pin Small Outline DIMM 8 pieces of µPD45128163G5 (Rev. E)

(Socket Type) (10.16mm (400) TSOP (II))

MC-4516CD64PS-A10B Edge connector: Gold plated 8 pieces of µPD45128163G5 (Rev. P)

26.67 mm height (10.16mm (400) TSOP (II))

Package Mounted devices

2

Data Sheet M13612EJ5V0DS00

MC-4516CD64ES, 4516CD64PS

Pin Configuration

144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

Vss
DQ 32
DQ 33
DQ 34
DQ 35
Vcc
DQ 36
DQ 37
DQ 38
DQ 39
Vss
DQMB4
DQMB5
Vcc
A3
A4
A5
Vss
DQ 40
DQ 41
DQ 42
DQ 43
Vcc
DQ 44
DQ 45
DQ 46
DQ 47
Vss
NC
NC

CKE0
Vcc
/CAS
CKE1
NC
NC
CLK1
Vss
NC
NC
Vcc
DQ 48
DQ 49
DQ 50
DQ 51
Vss
DQ 52
DQ 53
DQ 54
DQ 55
Vcc
A7
BA0 (A13)
Vss
BA1 (A12)
A11
Vcc
DQMB6
DQMB7
Vss
DQ 56
DQ 57
DQ 58
DQ 59
Vcc
DQ 60
DQ 61
DQ 62
DQ 63
Vss
SCL
Vcc

Vss
DQ 0
DQ 1
DQ 2
DQ 3

V
DQ 4
DQ 5
DQ 6
DQ 7

Vss
DQMB0
DQMB1

V

A0
A1
A2

Vss

DQ 8

DQ 9
DQ 10
DQ 11

V
DQ 12
DQ 13
DQ 14
DQ 15

Vss

NC
NC

CLK0

Vcc

/RAS

/WE
/CS0
/CS1

NC

Vss

NC
NC

V
DQ 16
DQ 17
DQ 18
DQ 19

Vss
DQ 20
DQ 21
DQ 22
DQ 23

Vcc

A6
A8

Vss

A9

A10

Vcc

DQMB2
DQMB3

Vss
DQ 24
DQ 25
DQ 26
DQ 27

V
DQ 28
DQ 29
DQ 30
DQ 31

Vss

SDA

V

CC

CC

CC

CC

CC

CC

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143

/xxx indicates active low signal.

A0 - A11 : Address Inputs
[Row: A0 - A11, Column: A0 - A8]

(A13), BA1 (A12) : SDRAM Ba nk Select

BA0
DQ0 - DQ63 : Data Inputs/Outputs
CLK0, CLK1 : Clock Input
CKE0, CKE1 : Clock Enable Input
/CS0, /CS1 : Chip Select Input
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQMB0 - DQMB7 : DQ Mask Enable
SDA : Serial Data I/O for PD
SCL : Clock Input for PD

CC

V

SS

V

: Power Supply
: Ground

NC : No Connection

Data Sheet M13612EJ5V0DS00

3

Block Diagram

CKE1
CKE0

/CS1
/CS0

MC-4516CD64ES, 4516CD64PS

DQMB0

DQMB1

DQMB2

DQMB3

DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7

DQ 8

DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15

DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23

DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31

UDQM
DQ 15
DQ 14
DQ 13
DQ 12
DQ 11
DQ 10
DQ 9
DQ 8
LDQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7

UDQM
DQ 15
DQ 14
DQ 13
DQ 12
DQ 11
DQ 10
DQ 9
DQ 8
LDQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7

/CS

CKE

D0

/CS CKE

D1

LDQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7

UDQM
DQ 15
DQ 14
DQ 13
DQ 12
DQ 11
DQ 10
DQ 9
DQ 8

LDQM

DQ 0

DQ 1

DQ 2

DQ 3

DQ 4

DQ 5

DQ 6

DQ 7

UDQM

DQ 15

DQ 14

DQ 13

DQ 12

DQ 11

DQ 10

DQ 9

DQ 8

/CS

CKE

D4

/CS CKE

D5

DQMB4

DQMB5

DQMB6

DQMB7

DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39

DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47

DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55

DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62

DQ 63

UDQM
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
LDQM

DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0

UDQM
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
LDQM
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0

/CS

/CS

D2

D3

CKE

CKE

LDQM
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
UDQM
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15

LDQM
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0

UDQM
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15

/CS

/CS

CKE

D6

CKE

D7

SERIAL PD

SCL

A0 - A11 A0 - A11 : D0 - D7

BA0 A13 : D0 - D7
BA1 A12 : D0 - D7

Remark

D0 - D7:

A0 A1 A2

µ

PD45128163 (2M words x 16 bits x 4 banks)

4

SDA

CLK0

Data Sheet M13612EJ5V0DS00

V

CC

V

SS

CLK : D0, D2
CLK : D1, D3

10 Ω

/RAS /RAS : D0 - D7
/CAS /CAS : D0 - D7

/WE /WE : D0 - D7

C

CLK1

D0 - D7
D0 - D7

CLK : D4, D6
CLK : D5, D7

10 Ω

MC-4516CD64ES, 4516CD64PS

Electrical Specifications

• All voltages are referenced to VSS (GND).

• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper

device operation is achieved.

Absolute Maximum Ratings

Parameter Symbol Condition Rating Unit
Voltage on power supply pin relative to GND V
Voltage on input pin relative to GND V
Short circuit output c urrent I
Power dissipation P
Operating ambient tem perature T
Storage temperature T

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

CC

T

O

D

A

stg

–0.5 to +4.6 V
–0.5 to +4.6 V

50 mA

8W

0 to +70

–55 to +125

C

°

C

°

Recommended Operating Conditions

Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage V
High level input voltage V
Low level input voltage V
Operating ambient tem perature T

Capacitance (TA = 25

Input capacitance C

Data input/output capaci t ance C

C, f = 1 MHz)

°°°°

Parameter Symbol Test condition MIN. TYP. MAX. Unit

CC

IH

IL

A

I1

A0 - A11, BA0(A13), BA1(A12),

3.0 3.3 3.6 V

2.0 V

–0.3 + 0.8 V

070

/RAS, /CAS, /WE

I2

C

CLK0, CLK1 30

I3

C

CKE0, CKE1 30

I4

C

/CS0, /CS1 30

I5

C

DQMB0 – DQMB7 20

I/O

DQ0 - DQ63 20 pF

CC +

0.3 V

60 pF

C

°

Data Sheet M13612EJ5V0DS00

5

MC-4516CD64ES, 4516CD64PS

★

DC Characteristics (Recommended Operating Conditions unless otherwise noted)

Parameter Symbol Test condition MIN. MAX. Unit Notes

Operating current I

Precharge standby current in I
power down mode I
Precharge standby current in
non power down mode

Active standby current i n I
power down mode I
Active standby current i n
non power down mode

Operating current I

CC1

Burst length = 1, t

CC2

P CKE ≤ V

CC2

PS CKE ≤ V

CC2

I

NCKE

Input signals are changed one time during 30

CC2

I

NS CKE ≥ V

CC3

P CKE ≤ V

CC3

PS CKE ≤ V

CC3

I

NCKE

Input signals are changed one time during 30

CC3

I

NS CKE ≥ V

CC4tCK ≥ tCK(MIN.)

IL(MAX.)

IL(MAX.)

≥ VIH(MIN.)

IH(MIN.)

IL(MAX.)

IL(MAX.)

≥ VIH(MIN.)

IH(MIN.)

(Burst mode) /CAS latency = 3 680
CBR (Auto) refresh current I

Self refresh current I
Input leakage current I
Output leakage current I
High level output voltage V
Low level output voltage V

Notes 1.

CC1

depends on output loading and cycle rates. Specified values are obtained with the output open. In

I
addition to this, I

CC4

2

.I

depends on output loading and cycle rates. Specified values are obtained with the output open. In

addition to this, I

CC5

3.

I

is measured on condition that addresses are changed only one time during t

CC5tRC ≥ tRC(MIN.)

CC6

CKE ≤ 0.2 V16mA

=

I(L)

I

V

0 to 3.6 V, All other pins not under test = 0 V – 8+8µA

O(L)DOUT

OHIO = –

OLIO = +

CC1

is measured on condition that addresses are changed only one time during t

CC4

is measured on condition that addresses are changed only one time during t

is disabled, VO = 0 to 3.6 V–3+3

4.0 mA 2.4 V

4.0 mA 0.4 V

RC ≥ tRC(MIN.)

/CAS latency = 2 560 mA 1
/CAS latency = 3 560

CK = 15

, t
, t

, t

, t
, t
, t

, t

, t

ns 8 mA

∞

CK =

CK = 15

∞

CK =

CK = 15

CK =

CK = 15

∞

CK =

∞

≥ VIH(MIN.)

ns, /CS

,

ns.

, Input signals are st abl e. 64

ns 40 mA

≥ VIH(MIN.)

ns, /CS

,

ns.

, Input signals are st abl e. 160

, IO = 0 mA /CAS latency = 2 520 mA 2

/CAS latency = 2 1,000 mA 3
/CAS latency = 3 1,000

CK(MIN.)

8

160 mA

32

240 mA

µ

.

A

CK(MIN.)

CK(MIN.)

.

.

6

Data Sheet M13612EJ5V0DS00

MC-4516CD64ES, 4516CD64PS

★

AC Characteristics (Recommended Operating Conditions unless otherwise noted)

Test Conditions

Parameter Value Unit

AC high level input voltage / low level input vol t age 2.4 / 0.4 V
Input timing m easurement reference level 1.4 V
Transition time (Input rise and fall time) 1 ns
Output timing m easurement reference level 1.4 V

t

CK

t

CLK

Input

2.4 V

1.4 V

0.4 V

2.4 V

1.4 V

0.4 V

t

SETUPtHOLD

t

CH

t

AC

OH

t

CL

Output

Data Sheet M13612EJ5V0DS00

7

Synchronous Characteristics

★

Parameter Symbol -A10B Unit Note

Clock cycle time /CAS latency = 3 t

/CAS latency = 2 t

Access time from CLK /CAS latency = 3 t

/CAS latency = 2 t
CLK high level width t
CLK low level width t
Data-out hold time t
Data-out low-impedance tim e t
Data-out high-impedance time /CAS latency = 3 t

/CAS latency = 2 t
Data-in setup time t
Data-in hold time t
Address setup time t
Address hold time t
CKE setup time t
CKE hold time t
CKE setup time (P ower down exit) t
Command (/CS0, /CS1, /RAS, /CAS, /WE,

DQMB0 - DQMB7) setup time
Command (/CS0, /CS1, /RAS, /CAS, /WE,

DQMB0 - DQMB7) hold time

CK3

CK2

AC3

AC2

HZ3

HZ2

CKS

CKH

CKSP

CMS

t

CMH

t

MC-4516CD64ES, 4516CD64PS

MIN. MAX.

10
15

(100 MHz)

(67 MHz)

7ns1
8ns1

CH

CL

OH

LZ

3.5 ns

3.5 ns
3ns1
0ns
37ns
38ns

DS

DH

AS

AH

2.5 ns
1ns

2.5 ns
1ns

2.5 ns
1ns

2.5 ns

2.5 ns

1ns

ns
ns

Note 1.

Remark

Output load

Z = 50 Ω

Output

50 pF

These specifications are applied to the monolithic device.

8

Data Sheet M13612EJ5V0DS00

Asynchronous Characteristics

Parameter Symbol

MC-4516CD64ES, 4516CD64PS

-A10B

MIN. MAX.

Unit Note

ACT to REF/ACT comm and peri od (Operation) t
REF to REF/ACT command period (Refresh) t
ACT to PRE command period t
PRE to ACT command period t
Delay time ACT to READ/WRITE command t
ACT(one) to ACT(another) command period t
Data-in to PRE command period t
Data-in to ACT(REF) command /CAS latency = 3 t
period (Auto precharge)

/CAS latency = 2 t
Mode register set cycle time t
Transition time t
Refresh time (4,096 refres h cycles) t

RC

RC1

RAS

RP

RCD

RRD

DPL

DAL3

DAL2

RSC

REF

90 ns
90 ns
60 120,000 ns
30 ns
30 ns
20 ns

10 ns
1CLK+30 ns
1CLK+30 ns

2CLK

T

130ns

64 ms

Data Sheet M13612EJ5V0DS00

9

MC-4516CD64ES, 4516CD64PS

Serial PD

Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes

0 Defines the number of byt es written

into serial PD memory

1 Total number of bytes of serial PD

memory
2 Fundamental me mory type 04H 0 0 0 0 0 1 0 0 SDRAM
3 Number of rows 0CH 0 0 0 0 1 1 0 0 12 rows
4 Number of columns 09H 0 0 0 0 1 0 0 1 9 columns
5 Number of banks 02H 0 0 0 0 0 0 1 0 2 bank s
6 Data width 40H 0 1 0 0 0 0 0 0 64 bits
7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0
8 Voltage interface 01H 0 0 0 0 0 0 0 1 LVTTL
9 CL = 3 Cycle time A0H 1 0 1 0 0 0 0 0 10 ns

10 CL =3 Access time 70H 0 1 1 1 0 0 0 0 7 ns
11 DIMM configuration type 00H 0 0 0 0 0 0 0 0 None
12 Refresh rate/type 80H 1 0 0 0 0 0 0 0 Normal
13SDRAM width 10H00010000×16
14 Error checking SDRAM width 00H 0 0 0 0 0 0 0 0 None
15 Mini mum clock delay 01H 0 0 0 0 0 0 0 1 1 clock
16 Burst length supported 8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F
17 Number of banks on each SDRAM 04H 0 0 0 0 0 1 0 0 4 banks
18 /CAS latency supported 06H 0 0 0 0 0 1 1 0 2, 3
19 /CS latency supported 01H 0 0 0 0 0 0 0 1 0
20 /WE latency supported 01H 0 0 0 0 0 0 0 1 0
21 SDRAM module attributes 00H 0 0 0 0 0 0 0 0
22 SDRAM device attributes : General 0EH 0 0 0 0 1 1 1 0
23 CL = 2 Cycle time F0H 1 1 1 1 0 0 0 0 15 ns
24 CL = 2 Access time 80H 1 0 0 0 0 0 0 0 8 ns

25-26 00H 0 0 0 0 0 0 0 0

RP(MIN.)

27 t

RRD(MIN.)

28 t

RCD(MIN.)

29 t

RAS(MIN.)

30 t
31 Module bank density 10H 0 0 0 1 0 0 0 0 64 M bytes

80H 1 0 0 0 0 0 0 0 128 bytes

08H 0 0 0 0 1 0 0 0 256 bytes

1EH 0 0 0 1 1 1 1 0 30 ns

14H0001010020 ns
1EH 0 0 0 1 1 1 1 0 30 ns
3CH 0 0 1 1 1 1 0 0 60 ns

(1/2)

10

Data Sheet M13612EJ5V0DS00

MC-4516CD64ES, 4516CD64PS

Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes

32 Command and add setup tim e
33 Command and add hold time 10H 0 0 0 1 0 0 0 0 1 ns

34 Data signal input setup tim e 25H 0 0 1 0 0 1 0 1 2.5 ns
35 Data signal input hold time 10H 0 0 0 1 0 0 0 0 1 ns

36-61 00H 0 0 0 0 0 0 0 0

62 SPD revision 12H 0 0 0 1 0 0 1 0 1.2 A
63 Checksum for bytes 0 - 62 B6H 1 0 1 1 0 1 1 0

64-71 Manufacture’s JEDEC ID code

72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly s eri al number

99-125 Mfg spec i fic

126 Intel specificati on f requency 66H 0 1 1 0 0 1 1 0 66 MHz
127 Intel specificati on / CA S latency

support

25H 0 0 1 0 0 1 0 1 2.5 ns

C7H11000111

(2/2)

Timing Chart

Refer to the

SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E)

.

Data Sheet M13612EJ5V0DS00

11

Package Drawing

144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)

MC-4516CD64ES, 4516CD64PS

M1 (AREA B)

R

M2 (AREA A)

Y

A (AREA B)

N

Q

M

L

A

H

S

(OPTIONAL HOLES)

U1

U2

C

I

B E

T

D

A1 (AREA A)

F

ITEM

MILLIMETERS

A

67.6
A1 67.6±0.15
B

23.2
C

29.0

4.6

D
D1 1.5±0.10

detail of A part

W

D1

V

D2

X

D2 4.0

32.8

E
F

3.7
H

0.8(T.P)

3.3

I
L 20.0
M

26.67±0.15
M1 4.67
M2 22.0

3.8 MAX.

N
Q R2.0
R 4.0±0.10

φ

S 1.8
T 1.0±0.1
U1 3.2 MIN.
U2 4.0 MIN.
V 0.25 MAX.
W 0.6±0.05
X 2.55 MIN.
Y 2.0 MIN.

M144S-80A11-1

12

Data Sheet M13612EJ5V0DS00

[MEMO]

MC-4516CD64ES, 4516CD64PS

Data Sheet M13612EJ5V0DS00

13

[MEMO]

MC-4516CD64ES, 4516CD64PS

14

Data Sheet M13612EJ5V0DS00

MC-4516CD64ES, 4516CD64PS

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

DD

pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.

or GND with a resistor, if it is considered to have a possibility of

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

Data Sheet M13612EJ5V0DS00

15

MC-4516CD64ES, 4516CD64PS

CAUTION FOR HANDLING MEMORY MODULES

When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.

When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.

• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.

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