Page 1
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4516CB647XFA
16M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-4516CB647XFA is 16,777,216 words by 64 bits synchronous dynamic RAM module on which 8 pieces of
128M SDRAM:
This module provides high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 16,777,216 words by 64 bits organization
• Clock frequency and access time from CLK
Part number /CAS latency Clock frequency Access time from CLK
MC-4516CB647XFA-A75 CL = 3 133 MHz 5.4 ns
CL = 2 100 MHz 6.0 ns
µ
PD45128841 are assembled.
(MAX.) (MAX.)
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and full page)
• Programmable wrap sequence (sequential
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10
• Single 3.3
• LVTTL compatible
• 4,096 refresh cycles/64
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27
• Unbuffered type
• Serial PD
Ω ±10 % of series resistor
V ± 0.3 V power supply
ms
/
interleave)
mm)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0232N20 (Ver 2.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
Elpida Memory, Inc. i s a joint venture DRAM company of NEC Corporation and Hi tachi, Ltd.
Page 2
Ordering Information
MC-4516CB647XFA
Part number Clock frequency
(MAX.)
MC-4516CB647XFA-A75 133 MHz 168-pin Dual In-line Memory Module 8 pieces of µPD45128841G5 (Rev. X)
(Socket Type) (10.16 mm (400) TSOP (II ))
Edge connector : Gold plated
34.93 mm height
Package Mounted devices
2
Data Sheet E0232N20 (Ver. 2.0)
Page 3
Pin Configuration
168-pin Dual In-line Memory
Module Socket Type (Edge connector: Gold plated)
MC-4516CB647XFA
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
SS
V
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
NC
NC
SS
V
NC
NC
Vcc
/CAS
DQMB4
DQMB5
NC
/RAS
SS
V
A1
A3
A5
A7
A9
(A13)
BA0
A11
Vcc
CLK1
NC
SS
V
CKE0
NC
DQMB6
DQMB7
NC
Vcc
NC
NC
NC
NC
SS
V
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
NC
SS
V
DQ53
DQ54
DQ55
SS
V
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
SS
V
CLK3
NC
SA0
SA1
SA2
Vcc
DQMB0
DQMB1
BA1
DQMB2
DQMB3
V
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
V
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
NC
NC
V
NC
NC
Vcc
/WE
/CS0
NC
V
A10
(A12)
Vcc
Vcc
CLK0
V
NC
/CS2
NC
Vcc
NC
NC
NC
NC
V
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
V
DQ21
DQ22
DQ23
V
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
V
CLK2
NC
NC
SDA
SCL
Vcc
SS
SS
SS
SS
A0
A2
A4
A6
A8
SS
SS
SS
SS
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
/xxx indicates active low signal.
A0 - A11 : Address Inputs
[Row: A0 - A11, Column: A0 - A9]
(A13), BA1 (A12) : SDRAM Bank Select
BA0
DQ0 - DQ63 : Data Inputs/Outputs
CLK0 - CLK3 : Clock Input
CKE0 : Clock Enable Input
/CS0, /CS2 : Chip Select Input
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQMB0
-
DQMB7 : DQ Mask Enable
SA0 - SA2 : Address Input for EEPROM
SDA : Serial Data I/O for PD
SCL : Clock Input for PD
V
CC
V
SS
: Power Supply
: Ground
NC : No Connection
Data Sheet E0232N20 (Ver. 2.0)
3
Page 4
Block Diagram
/WE
/CS0
DQMB0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQM
MC-4516CB647XFA
/CS2
DQMB2
/WE
/CS
D0
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQMD2/CS /WE
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQMB1
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQMB4
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQMB5
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 4
DQ 7
DQ 6
DQ 5
DQ 3
DQ 2
DQ 1
DQ 0
DQ 5
DQ 7
DQ 6
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQM
/CS
D1
DQM /CS
D4
DQM
/CS
D5
/WE
/WE
/WE
DQMB3
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQMB6
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
DQMB7
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQ 4
DQ 7
DQ 6
DQ 5
DQ 3
DQ 2
DQ 1
DQ 0
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQM
DQM
DQM
/WE
/CS
D3
/WE
/CS
D6
/CS
/WE
D7
CLK0
CLK2
CLK1, CLK3
V
V
CC
SS
CLK : D0, D1, D4, D5
3.3 pF
CLK : D2, D3, D6, D7
3.3 pF
10 pF
D0 - D7
C
D0 - D7
Remarks 1. The value of all resistors is 10 Ω.
2. D0 - D7:
µ
PD45128841 (4M words × 8 bits × 4 banks)
4
A0 - A11
SCL
Data Sheet E0232N20 (Ver. 2.0)
BA0
BA1
/RAS
/CAS
CKE0
SERIAL PD
A0
SA1 SA2
SA0
A0 - A11 : D0 - D7
A13 : D0 - D7
A12 : D0 - D7
/RAS : D0 - D7
/CAS : D0 - D7
CKE : D0 - D7
SDA
A1 A2
Page 5
Electrical Specifications
y
–
• All voltages are referenced to VSS (GND).
µ
• After power up, wait more than 100
device operation is achieved.
Absolute Maximum Ratings
s and then, execute power on sequence and CBR (Auto) refresh before proper
MC-4516CB647XFA
Parameter S
Voltage on power supply pin relative to GND VCC
Voltage on input pin relative to GND V
Short circuit output current IO 50 mA
Power dissipation PD 8 W
Operating ambient temperature TA 0 to 70 °C
Storage temperature T
mbol Condition Rating Unit
0.5 to +4.6 V
T
stg
–55 t o +125 °C
–0.5 to +4.6 V
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage VCC 3.0 3.3 3.6 V
High level input voltage VIH 2.0 VCC + 0.3 V
Low level input voltage VIL −0.3 +0.8 V
Operating ambient temperature TA 0 70 °C
A
Capacitance (T
= 25 °°°°C, f = 1 MHz)
Parameter Symbol Test condition MIN. TYP. MAX. Unit
Input capacitance CI1 A0 - A11, BA0 (A1 3), BA1 (A1 2), /RAS,
/CAS, /WE
C
C
C
C
Data input/output capacitance C
I2
CLK0, CLK2 20 40
I3
CKE0 28 52
I4
/CS0, /CS2 15 29
I5
DQMB0 - DQMB7 3 13
I/O
DQ0 - DQ63 4 13 pF
Data Sheet E0232N20 (Ver. 2.0)
24 62 pF
5
Page 6
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
-A75
Parameter Symbol Test condition MIN. MAX. Unit Notes
Operating current I
t
Precharge standby current in I
power down mode I
Precharge standby current i n
non power down mode
I
Active standby current i n I
power down mode I
Active standby current i n non
power down mode
I
Operating current I
(Burst mode) IO = 0 mA
CBR (Auto) refresh current I
Self refresh current I
Input leakage current I
Output leakage current I
High level output voltage VOH IO = – 4.0 mA
Low level output voltage VOL IO = + 4.0 mA
CC1
Burst length
RC ≥ tRC(MIN.)
CC2
P CKE ≤ V
CC2
PS CKE ≤ V
I
CC2
N CKE ≥ V
=
, IO = 0 mA
IL(MAX.)
IL(MAX.)
IH(MIN.)
, t
1
, t
CK = 15
, t
CK =
CK = 15
ns
∞
ns, /CS ≥ V
Input signals are changed one time during
30
ns.
CC2
NS CKE ≥ V
IH(MIN.)
, t
CK =
∞ Input
signals are stable.
CC3
P CKE ≤ V
CC3
PS CKE ≤ V
I
CC3
N CKE ≥ V
IL(MAX.)
IL(MAX.)
IH(MIN.)
, t
CK = 15
, t
CK =
, t
CK = 15
ns
∞
ns, /CS ≥ V
Input signals are changed one time during
30
ns.
CC3
NS CKE ≥ V
CC4
t
CK ≥ tCK(MIN.)
CC5
t
RC ≥ tRC(MIN.)
CC6
CKE ≤ 0.2 V
I(L)
V
test =
O(L)
D
IH(MIN.)
, t
CK =
∞, Input signals are st abl e. 160 mA
I
=
0 to 3.6 V, All other pins not under
0 V
OUT
is disabled, VO = 0 to 3.6 V
/CAS latency = 2
/CAS latency = 3
IH(MIN.)
,
IH(MIN.)
,
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
/CAS latency = 3
– 1.5 + 1.5
160 mA
240 mA
8 + 8
–
2.4 V
0.4 V
MC-4516CB647XFA
800 mA 1
840
8 mA
8
64
40 mA
32
960 mA 2
1,240
1,840 mA 3
1,920
16 mA
µ
A
µ
A
Notes 1. I
2. I
3. I
6
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
addition to this, I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC5
is measured on condition that addresses are changed only one time during t
is measured on condition that addresses are changed only one time during t
CC4
is measured on condition that addresses are changed only one time during t
CK (MIN.)
.
Data Sheet E0232N20 (Ver. 2.0)
CK (MIN.)
CK (MIN.)
.
.
Page 7
MC-4516CB647XFA
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Test Conditions
Parameter Value Unit
AC high level input voltage / low level input vol tage 2.4 / 0.4 V
Input timing m easurement reference level 1.4 V
Transition time (Input ri se and fall time) 1 ns
Output timing measurement reference level 1.4 V
tCK
tCH tCL
2.4 V
CLK
Input
1.4 V
0.4 V
tSETUP tHOLD
2.4 V
1.4 V
0.4 V
tAC
tOH
Output
Data Sheet E0232N20 (Ver. 2.0)
7
Page 8
Synchronous Characteristics
MC-4516CB647XFA
Parameter Symbol -A75
MIN. MAX.
Clock cycle time /CAS latency = 3 t
/CAS latency = 2 t
Access time from CLK /CAS latency = 3 t
/CAS latency = 2 t
CK3
7.5 (133 MHz) ns
CK2
10 (100 MHz) ns
AC3
5.4 ns 1
AC2
6.0 ns 1
Unit
Note
CLK high level width tCH 2.5 ns
CLK low level width tCL 2.5 ns
Data-out hold time tOH 3.0 ns 1
Data-out low-impedance tim e tLZ 0 ns
Data-out high-impedance time /CAS latency = 3 t
/CAS latency = 2 t
HZ3
3.0 5.4 ns
HZ2
3.0 6.0 ns
Data-in setup time tDS 1.5 ns
Data-in hold time tDH 0.8 ns
Address setup time tAS 1.5 ns
Address hold time tAH 0.8 ns
CKE setup time t
CKE hold time t
CKE setup time (P ower down exit) t
Command (/CS0, / CS 2, /RAS, /CAS, /WE, t
DQMB0 - DQMB7) setup time
Command (/CS0, / CS 2, /RAS, /CAS, /WE, t
DQMB0 - DQMB7) hold time
CKS
1.5 ns
CKH
0.8 ns
CKSP
1.5 ns
CMS
1.5 ns
CMH
0.8
ns
Note 1. Output load
Z = 50 Ω
Output
Remark These specifications are applied to the monolithic device.
50 pF
8
Data Sheet E0232N20 (Ver. 2.0)
Page 9
MC-4516CB647XFA
Asynchronous Characteristics
Parameter Symbol -A75 Unit Note
MIN. MAX.
ACT to REF/ACT comm and peri od (operat i on) tRC 67.5 ns
REF to REF/ACT command period (refresh) t
ACT to PRE command period t
PRE to ACT command period tRP 20 ns
Delay time ACT to READ/WRITE command t
ACT(one) to ACT(another) comm and peri od t
Data-in to PRE command period t
Data-in to ACT(REF) command /CAS latency = 3
period (Auto precharge) /CAS latency = 2
Mode register set cycle time t
Transition time tT 0.5 30 ns
Refresh time (4,096 refres h cycles) t
RC1
67.5 ns
RAS
45 120,000 ns
RCD
20 ns
RRD
15 ns
DPL
8 ns
t
DAL3
1CLK+22.5 ns 1
t
DAL2
1CLK+20 ns 1
RSC
2 CLK
REF
64 ms
Note This device can satisfy the t
DAL3
spec of 1CLK+20 ns for up to and including 125 MHz operation.
Data Sheet E0232N20 (Ver. 2.0)
9
Page 10
MC-4516CB647XFA
Serial PD (1/2)
Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
0 Defines the number of bytes written into
serial PD memory
1 Total number of bytes of serial PD memory
2 Fundamental memory type
3 Number of rows
4 Number of columns
5 Number of banks
6 Data width
7 Data width (continued)
8 Voltage interface
9 CL = 3 Cycle time 75H 0 1 1 1 0 1 0 1 7.5 ns
10 CL = 3 Access time 54H 0 1 0 1 0 1 0 0 5.4 ns
11 DIMM configuration type
12 Refresh rate/type
13 SDRAM width
14 Error checking SDRAM width
15 Minimum clock delay
16 Burst length supported
17 Number of banks on each SDRAM
18 /CAS latency supported
19 /CS latency supported
20 /WE latency supported
21 SDRAM module attributes
22 SDRAM device attributes : General
23 CL = 2 Cycle time A0H 1 0 1 0 0 0 0 0 10 ns
24 CL = 2 Access time 60H 0 1 1 0 0 0 0 0 6 ns
25-26 00H 0 0 0 0 0 0 0 0
27 t
RP(MIN.)
14H 0 0 0 1 0 1 0 0 20 ns
28 t
RRD(MIN.)
0FH 0 0 0 0 1 1 1 1 15 ns
29 t
RCD(MIN.)
14H 0 0 0 1 0 1 0 0 20 ns
30 t
RAS(MIN.)
2DH 0 0 1 0 1 1 0 1 45 ns
31 Module bank density 20H 0 0 1 0 0 0 0 0 128M bytes
32 Command and address signal input setup
time
33 Command and address signal input
hold time
34 Data signal input setup time 15H 0 0 0 1 0 1 0 1 1.5 ns
35 Data signal input hold time 08H 0 0 0 0 1 0 0 0 0.8 ns
36-61 00H 0 0 0 0 0 0 0 0
62 SPD revision 12H 0 0 0 1 0 0 1 0 1.2
63 Checksum for bytes 0 - 62 AFH 1 0 1 0 1 1 1 1
64 Manufacture’s JEDEC ID code 10H 0 0 0 1 0 0 0 0 NEC
80H 1 0 0 0 0 0 0 0 128 bytes
08H 0 0 0 0 1 0 0 0 256 bytes
04H 0 0 0 0 0 1 0 0 SDRAM
0CH 0 0 0 0 1 1 0 0 12 rows
0AH 0 0 0 0 1 0 1 0 10 columns
01H 0 0 0 0 0 0 0 1 1 bank
40H 0 1 0 0 0 0 0 0 64 bits
00H 0 0 0 0 0 0 0 0 0
01H 0 0 0 0 0 0 0 1 LVTTL
00H 0 0 0 0 0 0 0 0 None
80H 1 0 0 0 0 0 0 0 Normal
08H 0 0 0 0 1 0 0 0 ×8
00H 0 0 0 0 0 0 0 0 None
01H 0 0 0 0 0 0 0 1 1 clock
8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F
04H 0 0 0 0 0 1 0 0 4 banks
06H 0 0 0 0 0 1 1 0 2, 3
01H 0 0 0 0 0 0 0 1 0
01H 0 0 0 0 0 0 0 1 0
00H 0 0 0 0 0 0 0 0
0EH 0 0 0 0 1 1 1 0
15H 0 0 0 1 0 1 0 1 1.5 ns
08H 0 0 0 0 1 0 0 0 0.8 ns
10
Data Sheet E0232N20 (Ver. 2.0)
Page 11
MC-4516CB647XFA
(2/2)
Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
65-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126 Intel specification frequency 64H 0 1 1 0 0 1 0 0
127 Intel s pecification /CAS latency s upport FFH 1 1 1 1 1 1 1 1
Timing Chart
Refer to the µµµµPD45128441, 45128841, 45128163 Data sheet (E0031N).
Data Sheet E0232N20 (Ver. 2.0)
11
Page 12
Package Drawing
MC-4516CB647XFA
Front side
3.00
3.00
Back side
4.00
(DATUM -A-)
(63.67)
Component area
(Front)
1 84
AB
2 – φ 3.00
85
11.43
C
36.83 54.61
133.35
127.35
Component area
(Back)
168
4.80 Max
17.80
4.00 Min
1.27
34.93
Unit: mm
(DATUM -A-)
Detail A
1.27
0.050
2.50 ± 0.20
1.00 ± 0.05
Note: Tolerance on all dimensions ± 0.15 unless otherwise specified.
Detail B Detail C
R FULL
0.20 ± 0.15
3.125 ± 0.125
(DATUM -A-)
6.35 6.35
2.00 ± 0.10 4.175
1.00
3.125 ± 0.125
R FULL
2.00 ± 0.10
ECA-TS2-0049-01
12
Data Sheet E0232N20 (Ver. 2.0)
Page 13
MC-4516CB647XFA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
DD or GND with a resistor, if it is considered to have a possibility of being an output
to V
pin. The unused pins must be handled in accordance with the related specifications.
MDE0202
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
Data Sheet E0232N20 (Ver. 2.0)
CME0107
13
Page 14
MC-4516CB647XFA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
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