Datasheet MC44826D Datasheet (Motorola)



SEMICONDUCTOR

TECHNICAL DATA

TV AND VCR

I2C PLL TUNING CIRCUIT

WITH 1.3 GHz PRESCALER

AND MIX/OSC DECODER

PIN CONNECTIONS

Order this document by MC44826/D

14

13

12

11

10

9

8

1

2

3

4

5

6

7

V

TUN

Gnd

V

CC1

B

1

B

3

B

5

D SUFFIX

PLASTIC PACKAGE

CASE 751A

(SO–14)

14

1

HF

1

HF

2

PHO

Xtal

DEC

SDA

SCL

CA

(Top View)

1

MOTOROLA ANALOG IC DEVICE DATA

  
  

The MC44826 is a tuning circuit for TV and VCR tuner applications. It
contains, on one chip, all the functions required for PLL control of a VCO. This
integrated circuit also contains a high frequency prescaler and thus can
handle frequencies up to 1.3 GHz. The circuit has a band decoder that
provides the band switching signal for the mixer/oscillator circuit. The decoder
is controlled by the buffer bits or independently by extra bits T6 and T7.

The MC44826 has a programmable 512/1024 reference divider and is
manufactured on a single silicon chip using Motorola’s high density bipolar
process, MOSAIC (Motorola Oxide Self Aligned Implanted Circuits).

• Complete Single Chip System for MPU Control (I

2

C Bus)

• Divide–by–8 Prescaler Accepts Frequencies up to 1.3 GHz

• 15 Bit Programmable Divider

• Reference Divider: Programmable for Division Ratios 512 and 1024

• 3–State Phase/Frequency Comparator

• Operational Amplifier for Direct Tuning Voltage Output (30 V)

• Four Programmable Chip Addresses

• Integrated Band Decoder for the Mixer/Oscillator Circuit

• Band Buffers with Low “On” Voltage (0.4 V Maximum at 15 mA)

• Fully ESD Protected to MIL–STD–883C, Method 3015.7

(2000 V, 1.5 kΩ, 150 pF)

MOSAIC is a trademark of Motorola, Inc.

ORDERING INFORMATION

Device

Operating

Temperature Range

Package

MC44826D TA = –20° to +80°C SO–14

 Motorola, Inc. 1996 Rev 1

MC44826

2

MOTOROLA ANALOG IC DEVICE DATA

Representative Block Diagram

This device contains 3,204 active transistors.

Gnd

Test

Logic

Buffers

Latches

P–On
Reset

I2C Bus

Receiver

Latches

Phase

Comp

Ref

Divider

Osc

Latch Control

Program Divider

15 Bit

Latches B

Latches A

÷

8

Prescaler

Preamp

DTB2

POR

Operational

Amplifier

2.7 V

CL

DTB1

CL

Data

RL

DTF

F

out

TDI

F

out

F

ref

T10, T

11

T9, T12, T

14

T

13

37

67812

RL

55.0 V

F

out

F

ref

2

9
11
10

4

CA

SDA

SCL

HF

1

V

CC1

V

TUNVCC2

Bands Out

PHO

Xtal

B5B3B

1

DTS, EN

512/1024

14

13

Shift Register

15 Bit

DEC

Mixer/Oscillator

Band Decoder

T

7

T

6

T

8

1

3

HF

2

12 pF

3.2/4.0
MHz

MAXIMUM RATINGS (T

A

= 25°C, unless otherwise noted.)

Rating Pin Value Unit

Power Supply Voltage (V

CC1

) 5 6.0 V
Band Buffer “Off” Voltage 6, 7, 8 15 V
Band Buffer “On” Current 6, 7, 8 20 mA
Operational Amplifier Power Supply (V

CC2

) 1 40 V
RF Input Level 10 MHz to 1.3 GHz 3, 4 1.5 Vrms
Storage Temperature – –65 to +150 °C
Operating Temperature Range – –20 to +80 °C
Bus Input Voltage (Positive) 10, 11 7 V
Bus Input Voltage (Negative) 10, 11 –0.5 V

MC44826

3

MOTOROLA ANALOG IC DEVICE DATA

ELECTRICAL CHARACTERISTICS (V

CC1

= 5.0 V , V

CC2

= 33 V, TA = 25°C, unless otherwise noted.)

Characteristic

Pin Min Typ Max Unit

V

CC1

Supply Voltage Range 5 4.5 5.0 5.5 V

V

CC1

Supply Current (V

CC1

= 5.0 V) 5 25 35 50 mA
Band Buffer Leakage Current when “Off” at 12 V 6, 7, 8 – 0.01 1.0 µA
Band Buffer Saturation Voltage when “On” at 15 mA 6, 7, 8 – 0.2 0.4 V
Data/Clock Current at 0 V (Acknowledge “Off”) 10, 11 –10 – 0 µA
Data/Clock Current at 5.0 V (Acknowledge “Off”) 10, 11 0 – 1.0 µA
Data/Clock Input Voltage Low 10, 11 – – 1.5 V
Data/Clock Input Voltage High 10, 11 3.0 – – V
Data Saturation Voltage at 3.0 mA (Acknowledge “On”) 11 – 0.25 0.4 V
Decoder “High” Level Sourcing 100 µA 12 3.4 – V

CC1

V
Decoder “Medium” Level Sourcing 15 µA 12 1.7 – 2.3 V
Decoder “Low” Level Sinking 20 µA 12 0 – 0.8 V
Clock Frequency Range 10 – – 100 kHz
Oscillator Frequency Range 13 3.15 3.2 4.05 MHz

Operational Amplifier Internal Reference Voltage – 2.0 2.75 3.2 V
Operational Amplifier Input Current 14 –15 0 15 nA
DC Open Loop Gain (RL = 22 kΩ) 14, 1 100 250 1000 V/V
Gain Bandwidth Product (CL = 0.5 nF) 14, 1 0.3 – – MHz
V

out

Low (RL = 22 kΩ) 1 – 0.25 0.4 V
Phase Detector Current in High Impedance State 14 –15 0 15 nA
Charge Pump Current of Phase Comparator (T14 = 0) 14 30 40 50 µA
Charge Pump Current of Phase Comparator (T14 = 1) 14 90 125 150 µA
V

CC2

Supply Voltage Range 1 25 33 36 V

PIN FUNCTION DESCRIPTION

Pin Function Description

1 V

TUN/VCC2

Output of the tuning voltage amplifier. Needs an external pull–up resistor to drive the varicaps

2 Gnd Ground

3, 4 HF1/ HF

2

Symmetric HF inputs from local oscillator

5 V

CC1

Supply voltage. Typical 5.0 V

6, 7, 8 B1, B3, B

5

Band buffer outputs

9 CA Chip address selection pin
10 SCL Clock input of the I2C bus
11 SDA Data input
12 DEC Band decoder output for the mixer/oscillator circuit
13 Xtal Crystal input
14 PHO Input of tuning voltage amplifier

MC44826

4

MOTOROLA ANALOG IC DEVICE DATA

Figure 1. Typical Prescaler Input Sensitivity

Guaranteed Operating Area

0

5.0

RF Level (dBm)

RF In (MHz)

200 400

600

800 1000 1200 1400

–5.0

–15

–25

–35

–45

NOTE: VCC = 4.5 to 5.5 V, TA = – 20° to +80°C

HF CHARACTERISTICS (See Figure 1)

Characteristic

Pin Min Typ Max Unit

DC Bias 3, 4 – 1.6 – V
Input Voltage Range mVrms

50–950 MHz 3, 4 10 – 315
950–1300 MHz 3, 4 50 – 315

Figure 2. RF Sensitivity Test Circuit

10, 11 2

34 8

I

2

C Bus Controller

RF Generator

(50

Ω

)

5

+5.0 V

Frequency Counter

4.0 k

Ω

MC44826

50

Ω

1.0 nF1.0 nF

HF In

V

CC1

B

5

+12 V

Device is in test mode, B5 and B3 are “On”, B1 is “Off”.
Sensitivity is the level of the HF generator on 50 Ω load.

7

B

3

4.0 k

MC44826

5

MOTOROLA ANALOG IC DEVICE DATA

500 MHz

1.3 GHz

–j +j

2

0.5

1

0.5

1

2

0.5

1

2

ZO = 50

Ω

1.0 GHz

50 MHz

0

Figure 3. Typical HF Input Impedance

Figure 4. Complete Data Transfer Process

SDA

SCL

S P

1–7 8 9 1–7 8 9 1–7 8 9

STA ADDRESSCAR/W ACK DATA ACK DAT A ACK STO

Data Format and Bus Receiver

The circuit receives the information for tuning and control
via the I2C bus. The incoming information, consisting of a
chip address byte followed by two or four data bytes, is
treated in the I2C bus receiver. The definition of the
permissible bus protocol is shown below:

1_ST A CA CO BA STO
2_ST A CA FM FL STO
3_ST A CA CO BA FM FL STO
4_ST A CA FM FL CO BA STO

STA = Start Condition
STO = Stop Condition
CA = Chip Address Byte
CO = Data Byte for Control Information
BA = Band Information
FM = Data Byte for Frequency Information (MSB’s)
FL = Data Byte for Frequency Information (LSB’s)

Figure 5 shows the five bytes of information that are
needed for circuit operation: there is the chip address, two

bytes of control and band information and two bytes of
frequency information.

After the chip address, two or four data bytes may be
received: if three data bytes are received the third data byte
is ignored.

If five or more data bytes are received the fifth and
following data bytes are ignored and the last acknowledge
pulse is sent at the end of the fourth data byte.

The first and the third data bytes contain a function bit
which allows the IC to distinguish between frequency
information and control plus band information.

Frequency information is preceded by a Logic “0”. If the
function bit is Logic “1” the two following bytes contain control
and band information. The first data byte, shifted after the
chip address, may be byte CO or byte FM.

The two permissible bus protocols with five bytes are
shown in Figure 5.

The Data and Clock inputs (Pins 10 and 11) are high
impedance when the supply voltage V

CC1

is between 0 and

5.5 V.

MC44826

6

MOTOROLA ANALOG IC DEVICE DATA

Chip Address

The chip address is programmable by Pin 9 (CA – Address

Select).

CA – Pin 9 Address (HEX.)

–0.04 V

CC1

to 0.1 V

CC1

C6

Open or 0.2 V

CC1

to 0.3 V

CC1

C4

0.42 V

CC1

to 0.75 V

CC1

C2

0.9 V

CC1

to 1.2 V

CC1

C0

Figure 5. Definition of Bytes

CA_Chip Address 1 1 0 0 0 0/1 0/1 0 ACK

CO_Information

1

T

14

T

13

T

12

T

11

T

10

T

9

T

8

ACK

BA_Band Information T

7

T

6

B

5

X B

3

X B

1

X ACK

FM_Frequency Information

0

N

14

N

13

N

12

N

11

N

10

N

9

N

8

ACK

FL_Frequency Information N

7

N

6

N

5

N

4

N

3

N

2

N

1

N

0

ACK

CA_Chip Address 1 1 0 0 0 0/1 0/1 0 ACK

FM_Frequency Information

0

N

14

N

13

N

12

N

11

N

10

N

9

N

8

ACK

FL_Frequency Information N

7

N

6

N

5

N

4

N

3

N

2

N

1

N

0

ACK

ЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙЙ

CO_Information

1

T

14

T

13

T

12

T

11

T

10

T

9

T

8

ACK

BA_Band Information T

7

T

6

B

5

X B

3

X B

1

X ACK

1.0 nF

÷

8

Pres

Figure 6. Typical Tuner Application

678

B5B3B

1

12 pF

3.2/4.0 MHz

Gnd
2

114

B III

VHF

UHF

AGC

V

TUN

Phase

Comp

2.7 V

Mixer

B. P. Filter

Antenna

Filter

Oscillator

IF

5

5.0 V
11

10

9

13

Osc &

Ref Div

3

F

osc

SDA
SCL
CA

Bus
Rec

22 nF

47 k

(Note 1)

(Note 2)

330 p

47 nF

NOTES: 1. On some layouts the 100 Ω resistor will not be required.

2.C2 = 330 pF minimum is required for stability.

MC44826

Band Decoder

4

R

L

1.0 nF

33 V

Program

Divider

12

M/O

MC44826

7

MOTOROLA ANALOG IC DEVICE DATA

Bits B1, B3, B5: Control the Band Buffers

B1, B3, B5 = 0

B0, B1, B3 = 1

Buffer “Off”
Buffer “On”

Bit T8: Controls the Output of the Operational Amplifier

T8 = 0

T8 = 1

Normal Operation
Operational Amplifier Active

Output State of Operational Amplifier Switched “Off”,
Output Pulls High Through the External Pull–Up
Resistor R

L

Bits T9, T12: Control the Phase Comparator

T

9

T

12

Function

1
1
0
0

0
1
0
1

Normal Operation
High Impedance
Upper Source “On” Only
Lower Source “On” Only

Bits T10, T11: Control the Reference Divider

T

10

T

11

Division Ratio

0
0
1
1

0
1
0
1

512
1024
1024
512

Bit T13: Switches the Internal Signals F

ref

and F

BY2

to

Bit T13: the Band Buffer Outputs (Test)

T13 = 0

T13 = 1

Normal Operation
Test Mode
F

ref

Output at B3 (Pin 7)

F

BY2

Output at B5 (Pin 8)

Bits B3 and B5 have to be “On”, B3 = B5 = 1 in the test mode.
F

ref

is the reference frequency.

F

BY2

is the output frequency of the programmable divider, divided by two.

Bit T14: Controls the Charge Pump Current of the

Bit T14: Phase Comparator

T14 = 0

T13 = 1

Pump Current 40 µA Typical
Normal Operation. Pump Current 125 µA Typical

Bits T6, T7: Mixer/Oscillator Band Decoder

The band decoder provides the band switching signal for
the mixer/oscillator circuit. The buffer bits control the decoder
output. The decoder can be controlled by the buffer bits or
independently by the control bits T6 and T7 as per the tables
below.

T

7

T

6

Decoder Output DEC

0

0
1
1

0

1
0
1

Decoder Output Controlled by Buffer Bits
B1, B3, B

5

0 to 0.8 V

1.8 to 2.1 V

3.4 V to V

CC1

(V

CC1

= 4.5 to 5.5 V)

B

5

B

3

B

1

Decoder Output DEC

0
0
1

1

X
X
X

X

0
1
0

1

1.8 to 2.1 V
0 to 0.8 V

3.4 V to V

CC1

(V

CC1

= 4.5 to 5.5 V)

Undefined

BA_Band Information

T7T6B5XB

3

XB

1

X ACK

The band buffers are open collector buffers and are active
“low” at Bn = 1. They are designed for 15 mA with a typical
“On” voltage of 200 mV. These buffers are designed to
withstand relative high output voltage in the “Off” state.

B3 and B5 buffers may also be used to output internal IC
signals (reference frequency and programmable divider
output frequency divided by 2) for test purposes.

The bit B3 and/or B5 have to be one if the buffers are used
for these additional functions.

The Programmable Divider

The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.

Since latches A receive the data asynchronously with the
programmable divider, this double latch scheme is needed to
assure correct data transfer to the counter.

The division ratio definition is given by:

N = 16384 x N14 + 8192 x N13 + … + 4 x N2 + 2 x N1 + N

0

Maximum Ratio 32767

Minimum Ratio 256

Where N0 … N14 are the different bits for frequency
information.

The counter may be used for any ratio between 256 and
32767, and reloads correctly as long as its output frequency
does not exceed 1.0 MHz.

The data transfer between latches A and B (signal TDI) is
also initiated by any start condition on the I2C bus.

At power–on the whole bus receiver is reset and the bit N

8

of the programmable divider is set to N8 = 1. Thus the
programmable divider starts with a division ratio of 256 or
higher.

The first I2C message must be sent only when the
POWER ON RESET is completed. Division ratios of N < 256
are not allowed.

The Prescaler

The prescaler has a preamplifier which guarantees high
input sensitivity.

The Phase Comparator

The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.

The Tuning Voltage Amplifier

The amplifier is designed for very low noise, low input bias
current and high power supply rejection. The positive input is
biased internally. The tuning voltage amplifier needs an
external pull–up resistor to generate the tuning voltage.

The amplifier can be switched “Off” through bit T8. When
bit T8 is “One”, the amplifier is “Off”. The tuning voltage is
then pulled high by the external pull–up resistor.

Figure 6 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).

The Oscillator

The oscillator uses a 3.2 or 4.0 MHz crystal tied to ground in
series with a capacitor. The crystal operates in its series
resonance mode.

The voltage at Pin 13, has low amplitude and low
harmonic distortion.

The negative impedance of the crystal input (Pin 13) is
about 3.0 kΩ.

MC44826

8

MOTOROLA ANALOG IC DEVICE DATA

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC PACKAGE

CASE 751A–03

(SO–14)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

G

P

7 PL

14 8

71

M

0.25 (0.010) B

M

S

B

M

0.25 (0.010) A

S

T

–T–

F

R X 45

SEATING
PLANE

D 14 PL

K

C

J

M

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

P 5.80 6.20 0.228 0.244

R 0.25 0.50 0.010 0.019

____

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

How to reach us:
USA/EUROPE / Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,

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MC44826/D

*MC44826/D*

◊