Datasheet MC44817D, MC44817BD Datasheet (Motorola)

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T

20° t

80°C

SO–16

Order this document by MC44817/D

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The MC44817/17B are tuning circuits for TV and VCR tuner applications.
They contain on one chip all the functions required for PLL control of a VCO.
The integrated circuits also contain a high frequency prescaler and thus can
handle frequencies up to 1.3 GHz.

The MC44817 has programmable 512/1024 reference divider while the
MC44817B has a fixed reference divider of 1024.

The MC44817/17B are manufactured on a single silicon chip using
Motorola’s high density bipolar process, MOSAIC (Motorola Oxide Self
Aligned Implanted Circuits).

• Complete Single Chip System for MPU Control (3–Wire Bus). Data and

Clock Inputs are IIC Bus Compatible

• Divide–by–8 Prescaler Accepts Frequencies up to 1.3 GHz

• 15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz

• Reference Divider: Programmable for Division Ratios 512 and 1024.

The MC44817B has a Fixed 1024 Reference Divider

• Tri–State Phase/Frequency Comparator

• Operational Amplifier for Direct Tuning Voltage Output (30 V)

• Four Integrated PNP Band Buffers for 40 mA (V

• Output Options for the Reference Frequency and the

Programmable Divider

• Bus Protocol for 18 or 19 Bit Transmission

• Extra Protocol for 34 Bit for Test and Further Features

• High Sensitivity Preamplifier

• Circuit to Detect Phase Lock

• Fully ESD Protected

CC1

to 14.4 V)

TV AND VCR

PLL TUNING CIRCUITS

WITH 1.3 GHz PRESCALER

AND 3–WIRE BUS

SEMICONDUCTOR

TECHNICAL DATA

16

1

D SUFFIX

PLASTIC PACKAGE

CASE 751B

(SO–16)

PIN CONNECTIONS

MOSAIC is a trademark of Motorola, Inc.

ORDERING INFORMATION

Device

MC44817D
MC44817BD

MOTOROLA ANALOG IC DEVICE DATA

Operating

Temperature Range

= –

A

116

DA

CL

2

XTAL

3

Amp In

V

Package

°

°

o +

V

33 V

CC2

V

5.0 V

CC1

 Motorola, Inc. 1996 Rev 1

TUN

HF In

4

5

6

7

8

(Top View)

15

14

13

12

11

10

EN

Lock

V

12 V

CC3

B

3

B

2

B

1

B

0

Gnd

9

1

Gnd

EN

Data

Clock

F

9

16
1

2

F

out

ref

V

CC1

Logic

Test

P–On

Reset

3–Wire Bus

Receiver

MC44817/17B

Representative Block Diagram

Bands Out 30 mA

°

(40 mA at 0

DTB1

DTB2

POR

CL

Data

RL

to 80°C)

B3B2B1B

Buffers

Latches

T

6

4

Shift Register

15 Bit

15

10111213 14 5 675.0 V

0

T

4

Latches

V

T0

6

CC3

…

12 V

T

V

TUN

V

CC2

20 k

4

Amp In

2.7 V

Operational

Amplifier

3

T

5

Phase

Comp

F

out

15

Lock

F

ref

512/1024

B = 1024 Only

Ref

Divider

DTF

Latches A

Latches B

TDI

Osc

3

XTAL

Preamp 1

÷

HF Input

8

Preamp 2

8

Prescaler

Program Divider

15 Bit

F

Latch Control

out

DTS, EN

This device contains 3,204 active transistors.

MAXIMUM RATINGS (T

= 25°C, unless otherwise noted.)

A

Rating Pin Value Unit

Power Supply Voltage (V

) 7 6.0 V

CC1

Band Buffer “Off” Voltage 10–13 14.4 V
Band Buffer “On” Current 10–13 50 mA
Band Buffer – Short Circuit Duration (0 to V
Operational Amplifier Power Supply Voltage (V
Operational Amplifier Short Circuit Duration (0 to V
Power Supply Voltage (V

) 14 14.4 V

CC3

) (Note 2) 10–13 Continuous –

CC3

) 6 40 V

CC2

) 5 Continuous –

CC2

Storage Temperature – –65 to +150 °C
Operating Temperature Range – –20 to +80 °C
Band Buffer Operation (Note 1) at 50 mA each Buffer

10–13 10 sec

All Buffers “On” Simultaneously

Operational Amplifier Output Voltage 5 V

CC2

RF Input Level (10 MHz to 1.3 GHz) – 1.5 Vrms

NOTES: 1. At V

2.At V

CC3
CC3

= V

to 14.4 V and TA = –20° to +80°C.

CC1

= V

to 14.4 V and TA = –20° to +80°C one buffer “On” only.

CC1

V

2

MOTOROLA ANALOG IC DEVICE DATA

MC44817/17B

ELECTRICAL CHARACTERISTICS (V

Characteristic

V

Supply Voltage Range 7 4.5 5.0 5.5 V

CC1

V

Supply Current (V

CC1

V

Supply Voltage Range 6 25 – 37 V

CC2

V

Supply Current (Output Open) 6 – 1.5 3.5 mA

CC2

Band Buffer Leakage Current when “Off” at 12 V 10–13 – 0.01 1.0 µA
Band Buffer Saturation Voltage when “On” at 30 mA 10–13 – 0.15 0.3 V
Band Buffer Saturation Voltage when “On” at 40 mA

only for 0° to 80°C
Data/Clock/Enable Current at 0 V 1, 2, 16 –10 – 0 µA
Data/Clock/Enable Current at 5.0 V 1, 2, 16 0 – 1.0 µA
Data/Clock/Enable Input Voltage Low 1, 2, 16 – – 1.5 V
Data/Clock/Enable Input Voltage High 1, 2, 16 3.0 – – V
Clock Frequency Range 2 – – 100 kHz
Oscillator Frequency Range 3 3.15 3.2 4.05 MHz
Operational Amplifier Internal Reference Voltage – 2.0 2.75 3.2 V
Operational Amplifier Input Current 4 –15 0 15 nA
DC Open Loop Voltage Gain – 100 250 – V/V
Gain Bandwidth Product (CL = 1.0 nF) – 0.3 – – MHz
V

Low, Sinking 50 µA 5 – 0.2 0.4 V

out

V

High, Sourcing 10 µA, V

out

Phase Comparator Tri–State Current 4 –15 0 15 nA
Charge Pump High Current of Phase Comparator 4 30 50 85 µA
Charge Pump Low Current of Phase Comparator 4 10 15 30 µA
V

Supply Voltage Range 14 V

CC3

V

Supply Current 14 mA

CC3

All Buffers “Off” – 0.2 0.5

One Buffer “On” when Open – 8.0 13

One Buffer “On” at 40 mA – 48 53

= 5.0 V) 7 – 37 50 mA

CC1

– V

CC2

out

CC1

= 5.0 V, V

CC2

= 33 V, V

= 12 V, TA = 25°C, unless otherwise noted.)

CC3

Pin Min Typ Max Unit

10–13 – 0.2 0.5 V

5 – 0.2 0.5 V

CC1

– 14.4 V

Data Format and Bus Receiver

The circuit is controlled by a 3–wire bus via Data (DA),
Clock (CL), and Enable (EN) inputs. The Data and Clock
inputs may be shared with other inputs on the IIC–Bus while
the Enable is a separate signal. The circuit is compatible with
18 and 19 bit data transmission and also has a mode for
34 bit transmission for test and additional features.

The 3–wire bus receiver receives data for the internal shift
register after the positive going edge of the EN–signal. The
data is transmitted to the band buffers on the negative going
edge of the clock pulse 4 (signal DTB1).

18 and 19 Bit Data Transmission

The programmable divider may receive 14 bit (18 bit
transmission) or 15 bit (19 bit transmission). The data is
transmitted to the programmable divider (latches A) on the
negative going edge of clock pulse 19 or on the negative
edge of the EN–signal if EN goes down after the 18th clock
pulse (signal DTF). If the programmable divider receives
14 bit, its MSB (bit N14) is internally reset. The reset pulse is
generated only if EN goes negative after the 18th clock pulse
(signal RL).

MOTOROLA ANALOG IC DEVICE DATA

34 Bit Data Transmission
(For Test and Additional Features)

In the test mode, the programmable divider receives 15 bit
and the data is transferred to latches A on the negative edge
of clock pulse 19 (signal DTF). The information for test is
received on clock pulses 20 to 26 and transmitted to the
latches on the negative edge of pulse 34 (signal DTB2).
These latches have a power–on reset. The power–on reset
sets the programmable divider to a counting ratio of 256 or
higher and resets the corresponding latches to the test bits
T0 to T6 (signal POR). The bus receiver is not disturbed if the
data format is wrong. Useless bits are ignored. If for example
the Enable signal goes low after the clock pulse 9, bits one to
four are accepted as valid buffer information and the other
bits are ignored. If more than 34 bits are received, bit 35 and
the following are ignored.

Lock Detector

The lock–detector output is low in lock. The output goes
immediately high when an unlock condition is detected. The
output goes low again when the loop is in lock during a
complete period of the reference frequency.

3

MC44817/17B

Figure 1. HF Sensitivity T est Circuit

Bus

Bus Controller

16 1 2 14

Ω

MC44817/17B

0

10

Pin Min Typ Max Unit

CC1

HF Generator

HF Out Gnd

50 Ω Cable

Device is in test mode. B2, B3 are “On” and B0, B1 are “Off”.
Sensitivity is level of HF generator on 50 Ω load (without Pin 8 loading).

HF CHARACTERISTICS (See Figure 1)

Characteristic

DC Bias 8 – 1.6 – V
Input Voltage Range mVrms

10–80 MHz, Prescaler “Off”, T6 = 1.0 8 20 – 315
80–150 MHz 8 10 – 315
150–600 MHz 8 5.0 – 315
600–950 MHz 8 10 – 315
950–1300 MHz 8 50 – 315

7V

HF8Gnd9B

1.0 nF

50

V

CC3

B

1

11

4.7 k 4.7 k

B

12

2

390

40 mA

B

3

13

Ω

Ω

390

Counter

In

Figure 2. T ypical HF Input Impedance

–j +j

0

0.5

0.5

ZO = 50

1.3 GHz

1

1.0 GHz

2

500 MHz

1

2

50 MHz

Ω

0.5

1

2

4

MOTOROLA ANALOG IC DEVICE DATA

MC44817/17B

Figure 3. Pin Circuit Schematic

DA 1

Data input

(3–wire bus)

CL 2

Clock input (supplied

by a microprocessor

via 3–wire bus)

XTAL 3

Crystal oscillator

(3.2 MHz or 4.0 MHz)

500

20 V

500

20 V

100

5.0 V

132 k

132 k

V

96 k

1/2 V

96 k

V

96 k

1/2 V

96 k

CC1

CC1

CC1

CC1

V

CC1

1/2 V

96 k

CC1

96 k

“On”/“Off”

132 k

100 k

20 V

500

20 V

V

CC1

2.0 k

20 V

20 V

16 EN
Enable input
(3–wire bus)

15 Lock
Lock detector output

14 V

CC3

Positive supply for integrated
band buffers (12 V)

13 B

3

Amp In 4

Negative input of

operation amplifier and

charge pump output

V

5

Operational amplifier

output which provides

the tuning voltage

Operational amplifier

positive supply (33 V)

Positive supply of

the circuit (5.0 V)

TUN

V

6

CC2

V

7

CC1

HF In 8

HF input from

local oscillator

2.0 k 10 k

20 V

100

20 V
20 V

20 V
20 V

5.0 V

5.0 V

20 k

2.0 k

2.0 k

18 k

1.2

“On”/“Off”

“On”/“Off”

“On”/“Off”

…

1.8 V

20 V

20 V

20 V

12 B

2

Band buffer outputs
can drive up to 30 mA
(40 mA at 05 to 805C

11 B

1

10 B

0

9 Gnd
Circuit Ground

)

MOTOROLA ANALOG IC DEVICE DATA

5

MC44817/17B

Bus Timing Diagram

Standard Bus Protocol 18 or 19 Bit

Data

26 344201

19

27 33195

51814

Clock

Buffers Frequency

Enable

Bus Protocol for Test and Features

B

B

B

B

3

Buffers Frequency Test & Features Random

N

2

1

0

14N13N12N11N10N9N8N7N6N5N4N3N2N1N0T6T5T4T3T2T1T0X7X6X5X4X3X2X1X0

Definition of Permissible Bus Protocols

1. Bus Protocol for 18 Bit
B3 B2 B1 B0 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N
N2 N1 N

0

Max Counting Ratio 16363
N14 is Reset Internally

2. Bus Protocol for 19 Bit
B3 B2 B1 B0 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N
N3 N2 N1 N

0

Max Counting Ratio 32767
–B0 to B3: Control of Band Buffers

–N0 to N14: Control of Programmable Dividers
N14 = MSB; N0 = LSB

Minimum Counting Ratio Always 17
B3 = First Shifted Bit
N0 = Last Shifted Bit

3. Bus Protocol for Test and Further Features (34 Bit)
B3 B2 B1 B0 N14…N0 T6 T5 T4 T3 T2 T1 T0 X7
X6…X1 X

0
–T0 to T3: Control the Phase Comparator
–T4: Switches Test Signals to the Buffer Outputs
–T5: Division Ratio of the Reference Divider

B Version T5 = “X”
–T6: Bypasses the Prescaler (Note 1)
–X0 to X7: Are Random

B3 = First Shifted Bit
X0 = Last Shifted Bit

Definition of the Bits for Test and Features
Bit T0: Defines the Charge Pump Current of the

Bit T0: Phase Comparator

T0 = 0

T0 = 1

Pump Current 50 µA Typical
Pump Current 15 µA Typical

Bits T1 and T2: Define the Digital Function of the Phase

Bits T1 and T2: Comparator

3

4

T2T1State Output Function of Phase Comparator

0 0 1 Normal Operation
0 1 2 High Impedance (Tri–State)
1 0 3 Upper Source “On”, Lower Source “Off”
1 1 4 Lower Source “On”, Upper Source “Off”

NOTE: 1. The phase comparator pulls high if the input frequency is too

high and it pulls low when the input frequency is too low.
(Inversion by Operational Amplifier) The phase comparator
generates a fixed duration offset pulse for each comparison
pulse (similar to the MC44802A). This guarantees operation in
the linear region. The offset pulse is a positive current pulse
(upper source).

Bit T3: Defines the Offset Pulse of the Phase

Bit T3: Comparator

T3 = 0

T3 = 1

Bit T4: Switches the Internal Frequencies F

Offset Pulse Short (200 ns)
Normal Mode
Offset Pulse Long (350 ns)

ref

and

Bit T4: FBY2 to the Buffer Outputs (B2, B3)

T4 = 0

T4 = 1

NOTE: Bits B2 and B3 have to be one in this case.

Normal Operation
F

Switched to Buffer Output B

ref

FBY2 Switched to Buffer Output B

F

is the reference frequency.

ref

FBY2 is the output frequency of the programmable divider,
divided by two.

2

3

Bit T5: Defines the Division Ratio of the Reference

Bit T5: Divider

T5 = 0

T5 = 1

NOTE: The division ratio of the reference divider can only be

Division Ratio 512
Division Ratio 1024

programmed in the 34 bit bus protocol.
In the standard bus protocol the division ratio is 512.
(The power–up reset POR sets the division ratio to 512).
On “B–version”, T5 = “X”. Division ratio 1024 fixed.

6

MOTOROLA ANALOG IC DEVICE DATA

MC44817/17B

Bit T6: Switches the Prescaler

T6 = 0

T6 = 1

Normal Operation, 1.3 GHz
Low Frequency Operation

Preamp. 2 Switched Off, 165 MHz maximum
The prescaler is bypassed and the power supply of
the prescaler is switched off. Input: 10 MHz
minimum, 20 mVrms minimum

Figure 4. Equivalent Circuit of the Integrated

Band Buffers

V

12 V

CC3

25 V

Protection

NOTE:

IB + I
IB = Base Current
I

SUB

I

B

Gnd

“On”/“Off”

= 8.0 mA Typical, 13 mA Max

SUB
= Substrate Current of PNP

(1)

I

SUB

(Min V

0.15 V Typical

0.3 V Max

Out

…

B

B

0

, Max 14.4 V)

CC1

30 mA (40 mA
at 0 to 80

3

°

C)

The Programmable Divider

The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.

Since latches A receive the data asynchronously with the
programmable divider; this double latch scheme is needed to
assure correct data transfer to the counter.

The division ratio definition is given by:
N = 16384 x N14 + 8132 x N13 + … + 4 x N2 + 2 x N1 + N

Maximum Ratio 32767

(16363 in case of 18 bit bus protocol)

Minimum Ratio 17

N0 … N14 are the different bits for frequency information.

At power–on the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256 or
higher.

The Prescaler

The prescaler has a preamplifier which guarantees high
input sensitivity.

The Phase Comparator

The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.

The Operational Amplifier

The operational amplifier is designed for very low noise,
low input bias current and high power supply rejection. The
positive input is biased internally. The operational amplifier
needs 28.5 V supply (V

as minimum voltage for a

CC2)

guaranteed maximum tuning voltage of 28 V.

Figure 6 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).

The Oscillator

The oscillator uses a 3.2 to 4.0 MHz crystal tied to ground in
series with a capacitor. The crystal operates in the series
resonance mode.

The voltage at Pin 3 has low amplitude and low harmonic
distortion.

Figure 5. Equivalent Circuit of the Lock Output

V

CC1

200

µ

A Typical

0

2.0 k

100 k

Lock

25 V Protection

5.0 V

Figure 6. T ypical Tuner Application

UHF

VHF

B III

Antenna

Filter

AGC

NOTES: 1. On some layouts the 100 Ω resistor will not be required.

2.C2 = 330 pF minimum is required for stability.

B. P. Filter

V

TUN

Mixer

Oscillator

MOTOROLA ANALOG IC DEVICE DATA

F

IF

1.0 nF

osc

5.0 V

7

MC44817/17B

8

Gnd
9

330 p

(Note 2)

External Switching

111213 10

B3B2B1B

T

6

÷

8

Pres

65 4 15

(Note 1)

47 nF

33 V

0

Bus
Rec

Program

Divider

2.7 V

47 k

22 nF

14 12 V

V

Osc &

Ref Div

Phase
Comp

CC3

2
1

16

3

Lock

CL
DA
EN

12 pF

3.2/4.0 MHz

7

–T–

SEATING

PLANE

MC44817/17B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC PACKAGE

CASE 751B–05

M

(SO–16)

M M

R X 45°

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES

MIN MINMAX MAX

DIM

A

F

J

9.80

B

3.80

C

1.35

D

0.35

F

0.40

1.27 BSC 0.050 BSC

G
J

0.19

K

0.10

M

0

°

P

5.80

R

0.25

10.00

4.00

1.75

0.49

1.25

0.25

0.25
7

6.20

0.50

0.386

0.393

0.150

0.157

0.054

0.068

0.014

0.019

0.016

0.049

0.008

0.009

0.004

0.009

0

7

°

°

°

0.229

0.010

0.244

0.019

–A–

916

–B–

P 8 PL

1

8

0.25 (0.010) B

G

K

C

D

16 PL

0.25 (0.010) T B A

M

S S

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,

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INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

8

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MOTOROLA ANALOG IC DEVICE DATA

MC44817/D

*MC44817/D*