Datasheet MC44608P Specification

MC44608

Few External Components
Reliable and Flexible
SMPS Controller

The MC44608 is a high performance voltage mode controller
designed for off−line converters. This high voltage circuit that
integrates the start−up current source and the oscillator capacitor,
requires few external components while offering a high flexibility and
reliability.

The device also features a very high efficiency stand−by
management consisting of an effective Pulsed Mode operation. This
technique enables the reduction of the stand−by power consumption to
approximately 1.0 W while delivering 300 mW in a 150 W SMPS.

• Integrated Start−Up Current Source

• Lossless Off−Line Start−Up

• Direct Off−Line Operation

• Fast Start−Up

General Features

• Flexibility

• Duty Cycle Control

• Undervoltage Lockout with Hysteresis

• On Chip Oscillator Switching Frequency 40, 75, or 100 kHz

• Secondary Control with Few External Components

Protections

• Maximum Duty Cycle Limitation

• Cycle by Cycle Current Limitation

• Demagnetization (Zero Current Detection) Protection

• “Over V

• Programmable Low Inertia Over Voltage Protection

Against Open Loop

• Internal Thermal Protection

SMPS Controller

• Pulsed Mode Techniques for a Very High Efficiency

Low Power Mode

• Lossless Startup

• Low dV/dT for Low EMI Radiations

Protection” Against Open Loop

CC

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8

PDIP−8

P SUFFIX

CASE 626

PIN CONNECTIONS AND

MARKING DIAGRAM

Demag

Control Input

Device

MC44608P40 40 kHz

MC44608P75 75 kHz

1 8

2

I

sense

3

(Top View)

44608Pxxx

4

GND

(Top View)

AWL = Manufacturing Code
YYWW = Date Code

ORDERING INFORMATION

Switching

Frequency Shipping

1

AWL

YYWW

Package

7

6
5

Plastic
DIP−8

Plastic
DIP−8

V

i

V

CC

Driver

50/Rail

50/Rail

 Semiconductor Components Industries, LLC, 2003

December, 2003 − Rev. 6

MC44608P100 100 kHz

1 Publication Order Number:

Plastic
DIP−8

50/Rail

MC44608/D

Isense

10

S1

2

DMG

200 A

Demag

Logic

Output

Start−up

Phase

Stand−by

+

−

50 mV
/20 mV

Switching

Phase

&

Management

Leading Edge

Blanking

Latched off

Phase

Start−up

Phase

Stand−by

Output

MC44608

Demag Vi

18

1 V

>24 A

Enable

NOCOC

+

CS

−

OSC

>120 A

OSC

&

2 S

Clock

+

PWM

−

VPWM

4 kHz Filter

&

&

&

Latched off Phase

Start−up Phase

Switching Phase

S

R

Latched off Phase

Regulation

Block

UVLO2

OVP
UVLO1
UVLO2

OUT Disable

DMG

Thermal

Shutdown

PWM
Latch

Q

Stand−by

9 mA

Switching Phase

Start−up

Source

V

CC

Management

&

S2 S3

Buffer

6

V

CC

5

Driver

4

GND

3

Control
Input

Figure 1. Representative Block Diagram

MAXIMUM RATINGS

Rating Symbol Value Unit

Total Power Supply Current I
Output Supply Voltage with Respect to Ground V
All Inputs except Vi V
Line Voltage Absolute Rating V
Recommended Line Voltage Operating Condition V
Power Dissipation and Thermal Characteristics

Maximum Power Dissipation at TA = 85°C P
Thermal Resistance, Junction−to−Air R

Operating Junction Temperature T
Operating Ambient Temperature T

CC

CC

inputs

i
i

D



JA
J

A

30 mA
16 V

−1.0 to +16 V
500 V
400 V

600 mW
100 °C/W

150 °C

−25 to +85 °C

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2

MC44608

ELECTRICAL CHARACTERISTICS

Characteristic Symbol Min Typ Max Unit

OUTPUT SECTION

Output Resistor

Sink Resistance R

Source Resistance R
Output Voltage Rise Time (from 3.0 V up to 9.0 V) (Note 1) t
Output Voltage Falling Edge Slew−Rate (from 9.0 V down to 3.0 V) (Note 1) t

CONTROL INPUT SECTION

Duty Cycle @ I
Duty Cycle @ I
Control Input Clamp Voltage (Switching Phase) @ I
Latched Phase Control Input Voltage (Stand−by) @ I
Latched Phase Control Input Voltage (Stand−by) @ I

= 2.5 mA d

pin3

= 1.0 mA d

pin3

= −1.0 mA 4.75 5.0 5.25 V

pin3

= +500 A V

pin3

= +1.0 mA V

pin3

CURRENT SENSE SECTION

Maximum Current Sense Input Threshold
Input Bias Current I
Stand−By Current Sense Input Current I
Start−up Phase Current Sense Input Current I
Propagation Delay (Current Sense Input to Output @ VTH T MOS = 3.0 V) T
Leading Edge Blanking Duration MC44608P40 T
Leading Edge Blanking Duration MC44608P75 T
Leading Edge Blanking Duration MC44608P100 T
Leading Edge Blanking + Propagation Delay MC44608P40 T
Leading Edge Blanking + Propagation Delay MC44608P75 T
Leading Edge Blanking + Propagation Delay MC44608P100 T

OSCILLATOR SECTION

Normal Operation Frequency MC44608P40
Normal Operation Frequency MC44608P75 f
Normal Operation Frequency MC44608P100 f
Maximum Duty Cycle @ f = f

osc

OVERVOLTAGE SECTION

Quick OVP Input Filtering (R
Propagation Delay (I

demag

= 100 k) T

demag

> I

to output low) T

ovp

Quick OVP Current Threshold I
Protection Threshold Level on V
Minimum Gap Between V

CC−OVP

CC

and V

stup−th

1. This parameter is measured using 1.0 nF connected between the output and the ground.

OL

OH

r
f

2mA
1mA

LP−stby
LP−stby

V

CS−th

B−cs
CS−stby
CS−stup

PLH(In/Out)

LEB
LEB
LEB
DLY
DLY
DLY

f

osc
osc
osc

d

max

filt

PHL(In/Out)

OVP

V

CC−OVP

V

CC−OVP

V

stup

5.0 8.5 15

− 15 −

− 50 − ns

− 50 − ns

− − 2.0 %

36 43 48 %

3.4 3.9 4.3 V

2.4 3.0 3.7 V

0.95 1.0 1.05 V

−1.8 − 1.8 A
180 200 220 A
180 200 220 A

− 220 − ns

− 480 − ns

− 250 − ns

− 200 − ns
500 680 900 ns
370 470 570 ns
300 420 500 ns

36 40 44 kHz
68 75 82 kHz
90 100 110 kHz
78 82 86 %

− 250 − ns

− 2.0 − s
105 120 140 A

14.8 15.3 15.8 V

−

1.0 − − V



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3

MC44608

ELECTRICAL CHARACTERISTICS (V

= 12 V, for typical values TA = 25°C, for min/max values TA = −25°C to +85°C unless otherwise

CC

noted) (Note 2)

Characteristic

Symbol Min Typ Max Unit

DEMAGNETIZATION DETECTION SECTION (Note 3)

Demag Comparator Threshold (V

increasing) V

pin1

Demag Comparator Hysteresis (Note 4) H
Propagation Delay (Input to Output, Low to High) t
Input Bias Current (V
Negative Clamp Level (I
Positive Clamp Level @ I

Positive Clamp Level @ I

= 50 mV) I

demag

= −1.0 mA) V

demag

= 125 A V

demag

= 25 A V

demag

PHL(In/Out)

cl−neg−dem

dmg−th

dmg

dem−lb

cl−pos−

dem−H

cl−pos−

dem−L

30 50 69 mV

− 30 − mV

− 300 − ns

−0.6 − − A

−0.9 −0.7 −0.4 V

2.05 2.3 2.8 V

1.4 1.7 1.9 V

OVERTEMPERATURE SECTION

Trip Level Over Temperature
Hysteresis T

T

high
hyst

− 160 − °C

− 30 − °C

STAND−BY MAXIMUM CURRENT REDUCTION SECTION

Normal Mode Recovery Demag Pin Current Threshold

I

dem−NM

20 25 30 A

K FACTORS SECTION FOR PULSED MODE OPERATION

/ I

I

CCS

stup

I

/ I

CCS

stup

I

/ I

CCS

stup

I

/ I

CCL

stup

(V

− UVLO2) / (V

stup

(UVLO1 − UVLO2) / (V
ICS / V

csth

Demag ratio I
(V3

1.0 mA

V

control

ovp

− V3

Latch−off V3 − 4.8 − V

− UVLO1) 102 x K

stup

− UVLO1) 102 x K

stup

/ I

NM Dmgr 3.0 4.7 5.5 −

dem

) / (1.0 mA − 0.5 mA) R3 − 1800 − 

0.5 mA

MC44608P40 10 x K1 2.4 2.9 3.8 −
MC44608P75 10 x K1 2.8 3.3 4.2 −
MC44608P100 10 x K1 3.1 7.0 4.5 −

103 x K2 46 52 63 −

1.8 2.2 2.6 −

90 120 150 −

175 198 225 −

106 x Y

sstup

sl

cstby

SUPPLY SECTION

Minimum Start−up Voltage
VCC Start−up Voltage V
Output Disabling VCC Voltage After Turn On V
Hysteresis (V

stup−th

− V

) H

uvlo1

VCC Undervoltage Lockout Voltage V
Hysteresis (V

uvlo1

− V

) H

uvlo2

uvlo1−uvlo2

Absolute Normal Condition VCC Start Current @ (Vi = 100 V) and

(V

= 9.0 V)

CC

Switching Phase Supply Current (no load) MC44608P40

MC44608P75

MC44608P100
Latched Off Phase Supply Current I
Hiccup Mode Duty Cycle (no load) 

V

ilow

stup−th

uvlo1

stup−uvlo1

uvlo2

−(ICC) 7.0 9.5 12.8 mA

I

CCS

CC−latch

Hiccup

− − 50 V

12.5 13.1 13.8 V

9.5 10 10.5 V

− 3.1 − V

6.2 6.6 7.0 V

− 3.4 − V

2.0

2.4

2.6

2.6

3.2

3.4

3.6

4.0

4.5

mA

0.3 0.5 0.68 mA

− 10 − %

2. Adjust VCC above the start−up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction
temperature as close to ambient as possible.

3. This function can be inhibited by connecting pin 1 to GND.

4. Guaranteed by design (non tested).

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4

MC44608

PIN FUNCTION DESCRIPTION

Pin Name Description

1 Demag The Demag pin offers 3 different functions: Zero voltage crossing detection (50 mV), 24 A current detection

2 I

3 Control Input A feedback current from the secondary side of the SMPS via the Opto−coupler is injected into this pin. A

4 Ground This pin is the ground of the primary side of the SMPS.
5 Driver The current and slew rate capability of this pin are suited to drive Power MOSFETs.
6 V

7 This pin is to provide isolation between the Vi pin 8 and the VCC pin 6.
8 V

sense

CC

i

and 120 A current detection. The 24 A level is used to detect the secondary reconfiguration status and the
120 A level to detect an Over Voltage status called Quick OVP.

The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the
power MOSFET. When I
Current Protection function. A 200 A current source is flowing out of the pin 3 during the start−up phase and
during the switching phase in case of the Pulsed Mode of operation. A resistor can be inserted between the
sense resistor and the pin 2, thus a programmable peak current detection can be performed during the SMPS
stand−by mode.

resistor can be connected between this pin and GND to allow the programming of the Burst duty cycle during
the Stand−by mode.

This pin is the positive supply of the IC. The driver output gets disabled when the voltage becomes higher
than 15 V and the operating range is between 6.6 V and 13 V. An intermediate voltage level of 10 V creates a
disabling condition called Latched Off phase.

This pin can be directly connected to a 500 V voltage source for start−up function of the IC. During the
Start−up phase a 9.0 mA current source is internally delivered to the V

capacitor. As soon as the IC starts−up, this current source is disabled.

V

CC

reaches 1.0 V, the Driver output (pin 5) is disabled. This is known as the Over

sense

pin 6 allowing a rapid charge of the

CC

OPERATING DESCRIPTION

Regulation

V

V

CC

Control

Input

LP−stby

10

S3

Stand−by

&

Latched off Phase

3

5 V

10

S2

20 

V

dd

4 kHz

Filter

Regulation

Switching Phase

Output

Comparator

PWM

1.6 V

Figure 2. Regulator

The pin 3 senses the feedback current provided by the
Opto coupler. During the switching phase the switch S2 is
closed and the shunt regulator is accessible by the pin 3. The
shunt regulator voltage is typically 5.0 V. The dynamic
resistance of the shunt regulator represented by the zener
diode is 20 . The gain of the Control input is given on
Figure 11 which shows the duty cycle as a function of the
current injected into the pin 3.

A 4.0 kHz filter network is inserted between the shunt
regulator and the PWM comparator to cancel the high
frequency residual noise.

The switch S3 is closed in Stand−by mode during the
Latched Off Phase while the switch S2 remains open. (See
section PULSED MODE DUTY CYCLE CONTROL).

The resistor Rdpulsed (Rduty cycle burst) has no effect on
the regulation process. This resistor is used to determine the
burst duty cycle described in the chapter “Pulsed Duty Cycle
Control” on page 8.

PWM Latch

The MC44608 works in voltage mode. The on−time is
controlled by the PWM comparator that compares the
oscillator sawtooth with the regulation block output (refer to
the block diagram on page 2).

The PWM latch is initialized by the oscillator and is reset
by the PWM comparator or by the current sense comparator
in case of an over current. This configuration ensures that
only a single pulse appears at the circuit output during an
oscillator cycle.

Current Sense

The inductor current is converted to a positive voltage by
inserting a ground reference sense resistor R

Sense

in series

with the power switch.

The maximum current sense threshold is fixed at 1.0 V.
The peak current is given by the following equation:

Ipk

max



R

sense

1

(A)

()

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5

MC44608

In stand−by mode, this current can be lowered as due to the

activation of a 200 A current source:

1  (Rcs(k)  0,2)



10

200 A

R

sense

Switching Phase

&

L.E.B.

()

(A)

STAND−BY

START−UP

Overcurrent
Comparator

+

−

1 V

OC

Rsense

Ipk

maxstby

Isense

Rcs

2

Figure 3. Current Sense

The current sense input consists of a filter (6.0 k, 4.0 pF)
and of a leading edge blanking. Thanks to that, this pin is not
sensitive to the power switch turn on noise and spikes and
practically in most applications, no filtering network is
required to sense the current.

Finally, this pin is used:

− as a protection against over currents (Isense > I)

− as a reduction of the peak current during a Pulsed Mode

switching phase.

The overcurrent propagation delay is reduced by
producing a sharp output turn off (high slew rate). This
results in an abrupt output turn off in the event of an over
current and in the majority of the pulsed mode switching
sequence.

Demagnetization Section

The MC44608 demagnetization detection consists of a
comparator designed to compare the VCC winding voltage
to a reference that is typically equal to 50 mV.

This reference is chosen low to increase effectiveness of
the demagnetization detection even during start−up.

A latch is incorporated to turn the demagnetization block
output into a low level as soon as a voltage less than 50 mV
is detected, and to keep it in this state until a new pulse is
generated on the output. This avoids any ringing on the input
signal which may alter the demagnetization detection.

For a higher safety, the demagnetization block output is
also directly connected to the output, which is disabled
during the demagnetization phase.

The demagnetization pin is also used for the quick,
programmable OVP. In fact, the demagnetization input
current is sensed so that the circuit output is latched off when
this current is detected as higher than 120 A.

Oscillator Buffer

DMG

Output

RQ
DMG

S

+

−

&

> 24 A

>120 A

Figure 4. Demagnetization Block

50/20 mV

Idemag

Current Mirror

Demag

1

Idemag

This function can be inhibited by grounding it but in this

case, the quick and programmable OVP is also disabled.

Oscillator

The MC44608 contains a fixed frequency oscillator. It is
built around a fixed value capacitor CT successively
charged and discharged by two distinct current sources ICH
and IDCH. The window comparator senses the CT voltage
value and activates the sources when the voltage is reaching
the 2.4 V/4.0 V levels.

ICH

DMG

from Demag

logic block

SDCH

SCH

CT

4 V

2.4 V

+

−

&

IDCH

Figure 5. Oscillator Block

Window

comp

OSC

Clock

The complete demagnetization status DMG is used to
inhibit the recharge of the CT capacitor. Thus in case of
incomplete transformer demagnetization the next switching
cycle is postpone until the DMG signal appears. The
oscillator remains at 2.4 V corresponding to the sawtooth
valley voltage. In this way the SMPS is working in the so
called SOPS mode (Self Oscillating Power Supply). In that
case the effective switching frequency is variable and no
longer depends on the oscillator timing but on the external
working conditions (Refer to DMG signal in the Figure 6).

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6

MC44608

OSC

4 V

Vcont

2.4 V

Clock

DMG

Iprim

Figure 6.

The OSC and Clock signals are provided according to the
Figure 6. The Clock signals correspond to the CT capacitor
discharge. The bottom curve represents the current flowing
in the sense resistor Rcs. It starts from zero and stops when
the sawtooth value is equal to the control voltage Vcont. In
this way the SMPS is regulated with a voltage mode control.

Overvoltage Protection

The MC44608 offers two OVP functions:

− a fixed function that detects when VCC is higher than

15.4 V

− a programmable function that uses the demag pin. The
current flowing into the demag pin is mirrored and
compared to the reference current Iovp (120 A). Thus this
OVP is quicker as it is not impacted by the V

inertia and

CC

is called QOVP.

In both cases, once an OVP condition is detected, the

output is latched off until a new circuit START−UP.

Start−up Management

The Vi pin 8 is directly connected to the HV DC rail Vin.
This high voltage current source is internally connected to
the V

pin and thus is used to charge the VCC capacitor. T h e

CC

VCC capacitor charge period corresponds to the Start−up
phase. When the VCC voltage reaches 13 V, the high voltage

9.0 mA current source is disabled and the device starts
working. The device enters into the switching phase.

It is to be noticed that the maximum rating of the V

pin 8

i

is 500 V. ESD protection circuitry is not currently added to
this pin due to size limitations and technology constraints.
Protection is limited by the drain−substrate junction in
avalanche breakdown. To help increase the application
safety against high voltage spike on that pin it is possible to
insert a small wattage 1.0 k series resistor between the V
rail and pin 8.

The Figure 7 shows the VCC voltage evolution in case of
no external current source providing current into the V

CC

pin during the switching phase. This case can be
encountered in SMPS when the self supply through an
auxiliary winding is not present (strong overload on the
SMPS output for example). The Figure 17 also depicts this
working configuration.

V

CC

Start−up Latched off

Phase

Figure 7. Hiccup Mode

Phase

13 V

10 V

6.5 V

Switching

Phase

In case of the hiccup mode, the duty cycle of the switching

phase is in the range of 10%.

Mode Transition

The L W latch Figure 8 is the memory of the working status

at the end of every switching sequence.

Two different cases must be considered for the logic at the

termination of the SWITCHING PHASE:

1. No Over Current was observed

2. An Over Current was observed

These 2 cases are corresponding to the signal labelled
NOC in case of “No Over Current” and “OC” in case of Over
Current. So the ef fective working status at the end of the O N
time memorized in LW corresponds to Q=1 for no over
current and Q=0 for over current.

This sequence is repeated during the Switching phase.

Several events can occur:

1. SMPS switch OFF

2. SMPS output overload

3. Transition from Normal to Pulsed Mode

4. Transition from Pulsed Mode to Normal Mode

Latched Off

Phase

VPWM

OUT

LEB out

1 V

in

• 1. SMPS SWITCH OFF

NOC

&

+

CS

−

SQ

LW

OC

R

Figure 8. Transition Logic

Q

Start−up

Phase

&

&

I

demag

> 24 A

S
Mode
R1

R2

Switching

Q

Phase

Stand−by

&

S1

Switch

Start−up

Phase

When the mains is switched OFF, so long as the bulk
electrolithic bulk capacitor provides energy to the SMPS,
the controller remains in the switching phase. Then the peak
current reaches its maximum peak value, the switching
frequency decreases and all the secondary voltages are
reduced. The V

voltage is also reduced. When VCC is

CC

equal to 10 V, the SMPS stops working.

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7

MC44608

• 2. Overload

In the hiccup mode the 3 distinct phases are described as

follows (refer to Figure 7):

The SWITCHING PHASE: The SMPS output is low and
the regulation block reacts by increasing the ON time (dmax
= 80%). The OC is reached at the end of every switching
cycle. The LW latch (Figure 8) is reset before the VPWM
signal appears. The SMPS output voltage is low. The V

CC

voltage cannot be maintained at a normal level as the
auxiliary winding provides a voltage which is also reduced
in a ratio similar to the one on the output (i.e. Vout nominal
/ Vout short−circuit). Consequently the V
reduced at an operating rate given by the combination V

voltage is

CC

CC

capacitor value together with the ICC working consumption
(3.2 mA) according to the equation 2. When VCC crosses
10V the WORKING PHASE gets terminated. The LW latch
remains in the reset status.

The LATCHED−OFF PHASE: The V

capacitor

CC

voltage continues to drop. When it reaches 6.5 V this phase
is terminated. Its duration is governed by equation 3.

The START−UP PHASE is reinitiated. The high voltage
start−up current source (−I

= 9.0 mA) is activated and the

CC1

MODE latch is reset. The VCC voltage ramps up according
to the equation 1. When it reaches 13 V, the IC enters into the
SWITCHING PHASE.

The NEXT SWITCHING PHASE: The high voltage
current source is inhibited, the MODE latch (Q=0) activates
the NORMAL mode of operation. Figure 3 shows that no
current is injected out pin 2. The over current sense level
corresponds to 1.0 V.

As long as the overload is present, this sequence repeats.
The SWITCHING PHASE duty cycle is in the range of 10%.

• 3. Transition from Normal to Pulsed Mode

In this sequence the secondary side is reconfigured (refer
to the typical application schematic on page 13). The high
voltage output value becomes lower than the NORMAL
mode regulated value. The TL431 shunt regulator is fully
OFF. In the SMPS stand−by mode all the SMPS outputs are
lowered except for the low voltage output that supply the
wake−up circuit located at the isolated side of the power
supply . In that mode the secondary regulation is performed
by the zener diode connected in parallel to the TL431.

The secondary reconfiguration status can be detected on
the SMPS primary side by measuring the voltage level
present on the auxiliary winding Laux. (Refer to the
Demagnetization Section). In the reconfigured status, the
Laux voltage is also reduced. The V

self−powering is no

CC

longer possible thus the SMPS enters in a hiccup mode
similar to the one described under the Overload condition.

In the SMPS stand−by mode the 3 distinct phases are:

The SWITCHING PHASE: Similar to the Overload
mode. The current sense clamping level is reduced

according to the equation of the current sense section,
page 5. The C.S. clamping level depends on the power to be
delivered to the load during the SMPS stand−by mode.
Every switching sequence ON/OFF is terminated by an OC
as long as the secondary Zener diode voltage has not been
reached. When the Zener voltage is reached the ON cycle is
terminated by a true PWM action. The proper SWITCHING
PHASE termination must correspond to a NOC condition.
The LW latch stores this NOC status.

The LATCHED OFF PHASE: The MODE latch is set.
The ST ART−UP PHASE is similar to the Overload Mode.

The MODE latch remains in its set status (Q=1).

The SWITCHING PHASE: The Stand−by signal is
validated and the 200 A is sourced out of the Current Sense
pin 2.

• 4. Transition from Stand−by to Normal

The secondary reconfiguration is removed. The
regulation on the low voltage secondary rail can no longer
be achieved, thus at the end of the SWITCHING PHASE, no
PWM condition can be encountered. The LW latch is reset.

At the next WORKING PHASE a NORMAL mode status
takes place.

In order to become independent of the recovery time
constant on the secondary side of the SMPS an additional
reset input R2 is provided on the MODE latch. The condition
Idemag<24 A corresponds to the activation of the
secondary reconfiguration status. The R2 reset insures a
direct return into the Normal Mode.

Pulsed Mode Duty Cycle Control

During the sleep mode of the SMPS the switch S3 is
closed and the control input pin 3 is connected to a 4.6 V
voltage source thru a 500  resistor. The discharge rate of
the V

capacitor is given by I

CC

CC−latch

(device consumption
during the LATCHED OFF phase) in addition to the current
drawn out of the pin 3. Connecting a resistor between the
Pin 3 and GND (R

DPULSED

) a programmable current is
drawn from the VCC through pin 3. The duration of the
LATCHED OFF phase is impacted by the presence of the
resistor R

DPULSED

. The equation 3 shows the relation to the

pin 3 current.

Pulsed Mode Phases

Equations 1 through 8 define and predict the effective
behavior during the PULSED MODE operation. The
equations 6, 7, and 8 contain K, Y, and D factors. These
factors are combinations of measured parameters. They
appear in the parameter section “Kfactors for pulsed mode
operation” page 4. In equations 3 through 8 the pin 3 current
is the current defined in the above section “Pulsed Mode
Duty Cycle Control”.

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8

EQUATION 1

Start−up Phase Duration:

C

t

start–up



Vcc

 (V

stup

I

stup

MC44608

 UVLO2)

where: I
C

Vcc

EQUATION 2

Switching Phase Duration:

where: I

is the current consumed by the Power Switch

I

G

EQUATION 3

Latched−off Phase Duration:

where: I
I

pin3

EQUATION 4

Burst Mode Duty Cycle:

EQUATION 5

is the start−up current flowing through VCC pin

stup

is the VCC capacitor value

C

 (V

t

switch

ccS

t

latchedoff

ccL

is the current drawn from pin3 adding a resistor

d

BM

d

BM

Vcc



is the no load circuit consumption in switching phase

is the latched off phase consumption



t

startup



C

Vcc



(V

C

I

Vcc

 t

stup

I

 UVLO1)

stup

 I

ccS

stup

G

 (UVLO1  UVLO2)

I

 I

ccL

t

switch

switch

 UVLO2)

pin3

 t

latchedoff



C

 (V

Vcc

C

 (V

Vcc

I

I

ccS

stup

ccS

stup

 I

UVLO1)

 I

UVLO1)

G

G



C

 (UVLO1UVLO2)

Vcc

I

 I

ccL

pin3

EQUATION 6

d



BM

1 

where: k

= (UVLO1 − UVLO2)/(V

k

S/L

S/Stup

= (V

k



SStup

− UVLO2)/(V

stup

I



− UVLO1)

stup

ccS

I

stup

stup

1

 I

G



− UVLO1)

I

 I



I

ccL

ccS

 I

9

k

SL

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G

pin3



EQUATION 7

d



BM

EQUATION 8

d



BM

1 

1 











I

ccS



 I

I

stup

k1 

G

I



I

G

stup





k

SStup













1



k

SStup

MC44608

I



I

ccL



stup
 I

k2

pin3



k



SL

1

 (k

SL

1

I
I



pin3
stup

















)














where: k1 = I
k2 = I
k

S/Stup

k

= (UVLO1−UVLO2)/(V

S/L

Equations 9, 10, 11 and 12 allow the calculation of the Rcs value for the desired maximum current peak value during the

SMPS stand−by mode.

EQUATION 9

where: V
Ics is the CS internal current source
R

is the sensing resistor

S

R

is the resistor connected between pin 2 and R

cs

EQUATION 10

EQUATION 11

where: Y
Taking into account the circuit propagation delay (tcs) and the Power Switch reaction time (tps):

EQUATION 12

ccL/Istup

= (V

Ipk

stby

cs−th

Ipk

stby

Ipk

stby

cs−stby

Ipk

stby

ccs/Istup

−UVLO2)/(V

stup

V

cs–th



is the CS comparator threshold

 V

cs–th

 V

cs–th

= Ics/V

cs−th



V



cs–th

−UVLO1)

stup

−UVLO1)

stup

PULSED MODE CURRENT SENSE CLAMPING LEVEL

 (Rcs Ics)

R

S

R

1 



1  (Rcs Y



1  (Rcs Y







cs

R

S

R

S

R

I

cs

V

cs–th

cs–stby

cs–stby

S

S



)

)

Vin (tcs tps)





L

p

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10

60

50

40

30

Time (nS)

20

t_fall

t_rise

MC44608

79.0

77.0

75.0

73.0

71.0

Frequency

69.0

67.0

85° C

−25° C
25° C

10

10 11 12 13 14 15

Pin6 VCC Voltage (V)

Figure 9. Output Switching Speed

90

80

70

60

50

85° C

40

30

Switching Duty Cycle (%)

20

10

0

0.0 0.5 1.0 1.5 2.0 2.5

25° C

Current Injected in Pin3 (mA)

−25° C

Figure 11. Duty Cycle Control

65.0
10 11 12 13 14 15

VCC Voltage (V)

Figure 10. Frequency Stability

5.08

5.07

5.06

5.05

5.04

5.03

5.02

Vpin3 (V)

5.01

5.00

4.99

4.98

−25° C

0.5 1.5 2 2.5

85° C

25° C

1

Current Injected in Pin 3 (mA)

Figure 12. Vpin3 During the Working Period

5.0

4.5

4.0

3.5

3.0

Vpin3 Voltage (V)

2.5

2.0

1.5

−1.6

25° C

−1.4 −1.2 −1.0 −.08 −.06 −.04 −.02 0.0

−25° C

85° C

Current Injected in Pin 3 (mA)

Figure 13. Vpin3 During the Latched Off Period

4.80

4.60

4.40

4.20

4.00

3.80

3.60

Pin6 Current (mA)

3.40

3.20

3.00
10 11 12 13 14 15

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11

−25° C

25° C

85° C

Voltage (V)

Pin6 V

CC

Figure 14. Device Consumption when Switching

MC44608

11.00

−25° C

10.00

9.00

8.00

−Icc (mA)

7.00

6.00

5.00
0 100 200 300 400 500

25° C

85° C

Vi Pin8 Voltage (Vi)

Figure 15. High Voltage Current Source

12.00

11.00

10.00

9.00

8.00

85° C

7.00

Switching Duty Cycle (%)

6.00

5.00
0 100 200 300 400 500

−25° C

25° C

Vi Pin Voltage (V)

Figure 16. Overload Burst Mode

Figure 17. Hiccup Mode Waveforms

The data in Figure 16 corresponds to the waveform in
Figure 17. The Figure 17 shows VCC, ICC, I
V

(pin 5). V

out

(pin 5) in fact shows the envelope of the

out

(pin 2) and

sense

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output switching pulses. This mode corresponds to an
overload condition.

12

MC44608

The Figure 19 represents a complete power supply using the secondary reconfiguration.
The specification is as follows: Input source: 85 Vac to 265 Vac

3 Outputs 112 V/0.45 A

16 V/1.5 A

8.0 V/1.0 A
Output power 80 W
Stand−by mode @ Pout = 300 mW, 1.3 W

R F6

WIDE

MAINS

1N4007

FI

100 nF

D5

C1

I

sense

47288900

RFI

FILTER

C3

1 nF

C4

1 nF

1

2

3

4

3.9 k 

D1, D2, D3, D4

R5

100 k

8

7

6

MC44608P75

5

C8

100 nF

R4

V

CC

R2

1N5404

10

+

D7

1N4148

+

MTP6N60E

C5
220 F
400 V

MR856

C7
22 F
16 V

C20

2N2FY

R16

4.7 k 
4 kV

D6

5 W

C6
47 nF
630 V

R3

0.27 

R1

22 k

6

7

C9

470 pF

630 V

D14
MR856

R17

5 W

C11

220 pF

500 V

D18

MR856

14

C12

F47 

250 V

12

1

11

10

2

8

2.2 k

9

D9

MR852

C16
120 pF

D10

MR852

C15

16 V

R7

47 k

1N4934

+

+

F1000 



D12

C14
1000  F
35 V

R19

18 k

+

C17

120 pF

MCR22−6

DZ1

C13
100 nF

D13

1N4148

Post
Reg.

112 V/0.45 A

1

2

3

16 V/1.5 A

1

2

3

8 V/1 A



P

J3

J4

R11

4.7 k

OPT1

47 

DZ3
10 V

DZ2
TL431CLP

Figure 18. T ypical Application

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13

R21

C19
33 nF

R10

R9

R8

100 k

R12

1 k

10 k

2.4 k

C18
100 nF

OFFON

ON = Normal Mode
OFF = Pulsed Mode

MC44608

The secondary reconfiguration is activated by the P
through the switch. The dV/dt appearing on the high voltage
winding (pins 14 of the transformer) at every TMOS switch
off, produces a current spike through the series RC network
R7, C17. According to the switch position this spike is either
absorbed by the ground (switch closed) or flows into the
thyristor gate (switch open) thus firing the MCR22−6. The
closed position of the switch corresponds to the Pulsed
Mode activation. In this secondary side SMPS status the
high voltage winding (12−14) is connected through D12 and
DZ1 to the 8.0 V low voltage secondary rail. The voltages

applied to the secondary windings 12−14, 10−11 and 6−7
(Vaux) are thus divided by ratio N12−14 / N9−8 (number of
turns of the winding 12−14 over number of turns of the
winding 9−8). In this reconfigured status all the secondary
voltages are lowered except the 8.0 V one. The regulation
during every pulsed or burst is performed by the zener diode
DZ3 which value has to be chosen higher than the normal
mode regulation level. This working mode creates a voltage
ripple on the 8.0 V rail which generally must be post
regulated for the microProcessor supply.

Figure 19. SMPS Pulsed Mode

The Figure 19 shows the SMPS behavior while working
in the reconfigured mode. The top curve represents the V

CC

voltage (pin 6 of the MC44608). The middle curve
represents the 8.0 V rail. The regulation is taking place at

11.68 V. On the bottom curve the pin 2 voltage is shown.
This voltage represents the current sense signal. The pin 2

voltage is the result of the 200 A current source activated
during the start−up phase and also during the working phase
which flows through the R4 resistor. The used high
resolution mode of the oscilloscope does not allow to show
the effective ton current flowing in the sensing resistor R11.

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14

NOTE 2

−T−

SEATING
PLANE

H

58

−B−

14

F

−A−

C

N

D

G

0.13 (0.005) B

MC44608

PACKAGE DIMENSIONS

PDIP−8

P SUFFIX

PLASTIC PACKAGE

CASE 626−05

ISSUE L

NOTES:

1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).

3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

DIM MIN MAX MIN MAX

A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020

L

J

K

M

M

A

T

M

M

F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M −−− 10 −−− 10
N 0.76 1.01 0.030 0.040

INCHESMILLIMETERS



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15

MC44608

The product described herein (MC44608), may be covered by one or more of the following U.S. patents: 6,208,538 B1; 6,392,906 B2. There may be other
patents pending.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MC44608D

16