MC44603
17
MOTOROLA ANALOG IC DEVICE DATA
Maximum Duty Cycle and Soft–Start Control
Maximum duty cycle can be limited to values less than
80% by utilizing the D
max
and soft–start control. As depicted
in Figure 42, the Pin 11 voltage is compared to the oscillator
sawtooth.
Figure 42. D
max
and Soft–Start
C
Dmax
11
Soft–Start
Capacitor
V
OSC
Oscillator
D
max
Output
Drive
Output
Control
0.4 I
ref
V
ref
2.4 VD
Z
Figure 43. Maximum Duty Cycle Control
Voltage
D
max
Pin 11
V
CT
(Pin 10)
Using the internal current source (0.4 I
ref
), the Pin 11
voltage can easily be set by connecting a resistor to this pin.
If a capacitor is connected to Pin 11, the voltage increases
from 0 to its maximum value progressively (refer to Figure
44), thereby, implementing a soft–start. The soft–start
capacitor is discharged internally when the VCC (Pin 1)
voltage drops below 9.0 V.
Figure 44. Different Possible Uses of Pin 11
Pin 11
RI
RI
R Connected to Pin 11
I = 0.4 I
ref
V
Z
V
Z
C C // R
τ
= RC
If no external component is connected to Pin 11, an
internal zener diode clamps the Pin 11 voltage to a value V
Z
that is higher than the oscillator peak value, disabling
soft–start and maximum duty cycle limitation.
Foldback
As depicted in Fgure 32, the foldback input (Pin 5) can be
used to reduce the maximum VCS value, providing foldback
protection. The foldback arrangement is a programmable
peak current limitation.
If the output load is increased, the required converter peak
current becomes higher and VCS increases until it reaches its
maximum value (normally, VCS
max
= 1.0 V).
Then, if the output load keeps on increasing, the system is
unable to supply enough energy to maintain the output
voltages in regulation. Consequently, the decreasing output
can be applied to Pin 5, in order to limit the maximum peak
current. In this way, the well known foldback characteristic
can be obtained (refer to Figure 45).
Figure 45. Foldback Characteristic
V
out
V
O
Nominal
V
CC
V
disable2
Ipk
max
New Startup
Sequence Initiated
I
out
Overload
NOTE: Foldback is disabled by connecting Pin 5 to VCC.
Overvoltage Protection
The overvoltage arrangement consists of a comparator
that compares the Pin 6 voltage to V
ref
(2.5 V) (refer to
Figure 46).
If no external component is connected to Pin 6, the
comparator noninverting input voltage is nearly equal to:
ǒ
2.0 k
W
11.6 kW)
2.0 k
W
Ǔ
xV
CC
ǒ
2.0 k
W
11.6 kW)
2.0 k
W
Ǔ
xVCCw
2.5 V
The comparator output is high when:
à
VCCw
17 V
A delay latch (2.0 µs) is incorporated in order to sense
overvoltages that last at least 2.0 µs.
If this condition is achieved, V
OVP out
, the delay latch
output, becomes high. As this level is brought back to the
input through an OR gate, V
OVP out
remains high (disabling
the IC output) until V
ref
is disabled.
Consequently, when an overvoltage longer than 2.0 µs is
detected, the output is disabled until VCC is removed and
then re–applied.
The VCC is connected after V
ref
has reached steady state
in order to limit the circuit startup consumption.
The overvoltage section is enabled 5.0 µs after the
regulator has started to allow the reference V
ref
to stabilize.
By connecting an external resistor to Pin 6, the threshold
VCC level can be changed.
Figure 46. Overvoltage Protection
V
CC
V
ref
0
T
V
OVP
External
Resistor
2.5 V
(V
ref
)
2.0 k
11.6 k
2.5 V
5.0
µ
s
V
OVP out
2.0
µ
s
(If V
OVP out
= 1.0,
the Output is Disabled)
In Out
Delay
τ
Enable
C
OVLO
6
Delay
In
Out
τ