Datasheet MC34271 Datasheet (ON Semiconductor)

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MC34271

Liquid Crystal Display and
Backlight Integrated
Controller

The MC34271 is a low power dual switching voltage regulator,
specifically designed for handheld and laptop applications, to provide
several regulated output voltages using a minimum of external parts.
Two uncommitted switching regulators feature a very low standby
bias current of 5.0 µA, and an operating current of 7.0 mA capable of
supplying output currents in excess of 200 mA.

Both devices have three additional features. The first is an ELD
Output that can be used to drive a backlight or a liquid crystal display .
The ELD output frequency is the clock divided by 256. The second
feature allows four additional output bias voltages, in specific
proportions to VB, one of the switching regulated output voltages. It
allows use of mixed logic circuitry and provides a voltage bias for
N–Channel load control MOSFETst. The third feature is an Enable
input that allows a logic level signal to turn–“off” or turn–“on” both
switching regulators.

Due to the low bias current specifications, this device is ideally
suited for battery powered computer, consumer, and industrial
equipment where an extension of useful battery life is desirable.

MC34271 Features:

• Low Standby Bias Current of 5.0 µA

• Uncommitted Switching Regulators Allow Both Positive and

Negative Supply Voltages

• Logic Enable Allows Microprocessor Control of All Outputs

• Synchronizable to External Clock

• Mode Commandable for ELD and LCD Interface

• Frequency Synchronizable

• Auxiliary Output Bias Voltages Enable Load Control via N–Channel

FETs

MAXIMUM RATINGS (T

Rating

Input Voltage
Power Dissipation and

Thermal Characteristics

Maximum Power Dissipation – Case 873 P
Thermal Resistance, Junction–to–Ambient R

Thermal Resistance, Junction–to–Case R
Output #1 and #2 Switch Current
Output #1 and #2 “Off”–State V oltage
Feedback Enable MOSFETs

“Off”–State Voltage
Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature Range

= 25°C, unless otherwise noted.)

A

Symbol Value Unit

V

DD

D

θJA
θJC

ISL & I

SB

V

SL

V

LF

T

J

T

A

T

stg

16

1.43 W
100 °C/W

60 °C/W

500

60
20

125

0 to +70

–55 to +150

Vdc

mA
Vdc
Vdc

°C
°C
°C

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32

1

QFP–32

FB SUFFIX

CASE 873

PIN CONNECTIONS AND

MARKING DIAGRAM

32

31 30 29 2728 26 25

1

T

SW

124

DS

1

2

Ref

1

3

FB

1

4

Comp

1

5

SS

1

6

S

1

7

D

1

8

Drv

1

ELD

9101112 1413 15 16

R

Sync

Mode

V

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

Gnd

AWLYYWW

DD

4

V

(Top View)

A

V

MC34271

3

V

1

ref

V

EN

DS

Ref

Comp

SS

V2V1V

FB

V

EN

S
D

0

2

2

23

2

22

2

21

2

20

2

19

2

18

2

17

B

ORDERING INFORMATION

Device Package Shipping

MC34271FB QFP–32 250 Units / Tray

 Semiconductor Components Industries, LLC, 2000

April, 2000 – Rev. 0

1 Publication Order Number:

MC34271/D

EL

Panel

From DAC

EL

Control

µP Control

V

B

V

in

On/Off

Comp

Comp

VA = 5.0 V

MC34271

Representative Block Diagram

SW

EN

Drv

Sync

R

V

Ref

Ref

FB

EN

Ref

FB

1

32

1

26

1

8

31

30

T

V

27

1.25 V

1

2

1

3

1

4

2

25

2

23

2

22

2

21

28

÷ 2

ref

V

DD

BIAS

OSC

Circuit #1

PWM

Circuit #2

ELD

EN

PWM

BIAS Output

Buffers

D

1

7

S

1

6

ELD

9

V

V

DD

DD

11

Mode

10

D

2

18

S

2

19

V

B

17

V

0

16

V

1

15

V

2

14

V

3

13

V

in

V

B

V

0

V

1

V

2

V

3

Gnd

29

This device contains 350 active transistors.

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2

V

4

12

V

4

MC34271

ELECTRICAL CHARACTERISTICS (V

the operating ambient temperature range that applies, unless otherwise noted.)

Characteristic

REFERENCE SECTION

Reference Voltage (TJ = 25°C) V
Line Regulation (VDD = 5.0 V to 12.5 V) Reg
Load Regulation (IO = 0 to 120 µA) Reg
Total Variation (Line, Load and Temperature) V

ERROR AMPLIFIERS

Input Offset Voltage (VCM = 1.25 V) V
Input Bias Current (VCM = 1.25 V) I
Open Loop Voltage Gain (VCM = 1.25 V, V
Output Voltage Swing V

High State (IOH = –100 µA) Ve
Low State (IOL = 100 µA) Ve

BIAS VOLTAGE

Voltage (VDD = 5.0 V to 12.5 V, IO = 0) V

OSCILLATOR AND PWM SECTIONS

Total Frequency Variation Over Line and Temperature f

VDD = 5.0 V to 10 V, TA = 0° to 70°C, RT = 169 k 90 115 140

Duty Cycle at Each Output %

Maximum DC
Minimum DC

Sync Input

Input Resistance (V
Minimum Sync Pulse Width T

OUTPUT MOSFETs

Output Voltage – “On”–State (I
Output Current – “Off”–State (VOH = 40 V) I
Rise and Fall Times tr, t

EL DISCHARGE OUTPUT (ELD) AND DRV

Output Voltage – “On”–State (I
Output Voltage – “On”–State (I
Output Voltage – “Off”–State (I
Output Voltage – “Off”–State (I

FEEDBACK ENABLE SWITCHES (DS1, DS2)

Output Voltage – “Low”–State (I
Output Current – “Off”–State (VOH = 12.5 V) Ife

SWITCHED VDD OUTPUT (SW1)

Output Voltage V

Switch “On” (EN1 = 1, I
Switch “Off” (EN1 = 0, I

AUXILIARY VOLTAGE OUTPUTS

V0 Enable Switch

“On”–Resistance: VB to V
“Off”–State Leakage Current (VB = 10 V) I
V0 Voltage (VB = 30 V, I
V0 Resistance (I

NOTE: 1. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

= 3.5 V) R

sync

= 200 mA) V

sink

= 100 µA) V

sink

= 50 mA) V

sink

= –100 µA) V

source

= –50 mA) V

source

= 1.0 mA) Vfe

sink

= 100 µA) Vsw

source

= 100 µA) Vsw

sink

0

= 0 mA) V

source

= 4.0 mA) R

source

= 6.0 V, for typical values TA = Low to High [Note 1], for min/max values TA is

DD

Symbol Min Typ Max Unit

1.225 1.250 1.275 V
– 2.0 10 mV
– 2.0 10 mV

1.215 – 1.285 V

– 1.0 10 mV
– 120 600 nA

80 100 – dB

VA–1.5 4.0 5.5

0 – 1.0

4.6 5.0 5.4 V

92 95 –

– – 0

25 50 100 kΩ

– 1.0 – µs

– 150 250 mV
– 0.1 1.0 µA
– 50 – ns

– 30 100 mV
– 2.0 2.5 V

VDD–0.5 5.9 – V
VDD–3.5 3.3 – V

– 10 100 mV
– 0.6 1.0 µA

5.5 5.9 6.0
0 0.1 0.2

0 0.1 2.0 µA

29.5 29.9 30 V
20 40 60 Ω

= 2.0 V) A

COMP

1

ref

line

load

ref

IO
IB

VOL

OH

OL

A

OSC

max

min

sync

p

OL

OH

f

OL

OL
OH
OH

OL

OH

OH

OL

Rds 0 2.0 10 Ω

lkg

0

0

kHz

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3

MC34271

100

1.0

DC

SWITC

O

T

T

D

T

C

CLE

0

ELECTRICAL CHARACTERISTICS (continued) (V

the operating ambient temperature range that applies, unless otherwise noted.)

Characteristic UnitMaxTypMinSymbol

AUXILIARY VOLTAGE OUTPUTS

V1, V2, V3, V4 Outputs

1–V1/V0 Ratio 0.0500 0.0520 0.0535
1–V2/V0 Ratio 0.1010 0.1035 0.1065

V3/V0 Ratio 0.1010 0.1035 0.1065

V4/V0 Ratio 0.0500 0.0520 0.0535
Output Resistance (I
Output Short Circuit Current I

LOGIC INPUTS (EN1, EN2, MODE)

Input Low State V
Input High State V
Input Impedance R

SOFT START CONTROL (SS1,SS2)

Charge Current (Capacitor Voltage = 1.0 V to 4.0 V)

Discharge Current (Capacitor Voltage = 1.0 V) I

TOTAL SUPPLY CURRENT

VDD Current VDD = 6.0 V I

Standby Mode (EN1 = EN2 = 0) VDD = 16 V – 3.0 15

VDD Current I

Backlight “On” (EN1 = 1; EN2 = 0)

VDD Current I

LCD “On” (No Inductor) (EN1 = 0; EN2 = 1)

VB Current (V0 = 35 V) I

NOTE: 1. Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

= 4.0 mA) R

source

= 6.0 V , for typical values TA = Low to High [Note 1], for min/max values TA is

DD

o

ss

IL

IH

in

I

chg

dschg

CC

CC

CC

O

20 40 60 Ω

5.0 10 20 mA

0 – 0.8 V

2.0 – 6.0 V
25 50 100 kΩ

0.5 1.0 2.5 µA

250 650 – µA

– 2.0 5.0 µA

– 0.7 3.0 mA

– 0.9 2.0 mA

– 1.2 3.0 mA

Y
Y

U
PU

U
H

,

0.8

0.6

0.4

0.2

0

1.5

2.0 2.5 3.0 3.5 4.0 4.5 100 1.0 k 10 k 100 k 1000 k
V

, COMPENSATION VOLTAGE (V)

Comp

Figure 1. Switch Output Duty Cycle versus

Compensation V oltage

VDD = 6.0 V
TA = 25°C

80

60

40

20

, OPEN LOOP VOLTAGE GAIN (dB)

0

VOL

A

–20

10

Figure 2. Error Amp Open Loop Gain and

Gain

Phase

f, FREQUENCY (Hz)

Phase versus Frequency

VDD = 6.0 V
V

Comp

RL = Open
TA = 25°C

= 2.5 V

30

60

90

120

150

180

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4

MC34271

FET

DRAIN

OLTAGE

(

)

O

T

T

OLTAGE

DRO

(m

)

SWITC O T T SIN SAT RATION( )

8.0

OLTAGE

ARIATION

(

)

V
P

V
PU

U

– 5.0

–10

–15

–20

–25
–30

0

VDD = 6.0 V
TA = 25°C

0

1.0 2.0 3.0 4.0 5.0 4.0 6.0 8.0 10 12 16 18

V

ref

I, CURRENT DRAW (mA)

Figure 3. Reference V oltage Change versus

Reference Current

0.16

V

0.12

0.08

V

2.5

2.0

V

A

1.5

1.0

0.5

QUIESCENT CURRENT (mA)

0

2.0

EN1 = 1 and EN2 = 0

Standby Current
EN1 and EN2 = 0

VDD, SUPPLY VOLTAGE (V)

EN1 and EN2 = 1

RT = 169 k
No Loading
TA = 25°C

14

2.2

1.8

1.4

1.0

0.6

0.2

Figure 4. Quiescent Current versus Supply V oltage

–1.0

– 2.0

0

V

DD

Sink Saturation

VDD = 6.0 V
TA = 25°C

2.0

1.5

1.0

0.04
VDD = 6.0 V

TA = 25°C

0 – 4.0 0

0

ID, DRAIN CURRENT (mA)

– 3.0

, SWITCH OUTPUT SOURCE SATURATION (V)

sat

V

0

Source Saturation

30 6015 4550 150100 200

I

, SWITCH OUTPUT CURRENT (mA)

Source

Figure 5. FET Drain Voltage versus Sink Current Figure 6. ELD and DRV1 Switch Output Source

and Sink Saturation versus Current

0.30

0.25

V

0.20

0.15

0.10

V

0.05

V

– 0.05
– 0.10

VDD = 6.0 V

V

A

V

ref

0

10 20 30 40 50 60 70 10 20 30 40 50 60 70

0

TA, AMBIENT TEMPERATURE (°C)

Figure 7. V

and VA Variation

ref

versus T emperature

6.0

4.0

2.0
0

– 2.0
– 4.0

– 6.0

OSCILLATOR FREQUENCY CHANGE (kHz)

– 8.0

0

Figure 8. Oscillator Frequency Variation

TA, AMBIENT TEMPERATURE (°C)

versus T emperature

VDD = 6.0 V
RT = 169 k

0.5

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5

MC34271

1000

VDD = 6.0 V
TA = 25°C

100

FREQUENCY (kHz)

10

TIMING RESISTANCE (kΩ, s)

Figure 9. Frequency versus Timing

100 1000 1.0 2.0 3.0 4.0 5.0 6.0

OPERATING DESCRIPTION

The MC34271 is a monolithic, fixed frequency power
switching regulator specifically designed for dc to dc
converter and battery powered applications. This device
operates as a fixed frequency, voltage mode regulator
containing all the active functions required to directly
implement step–up, step–down and voltage inverting
converters with a minimum number of external components.
Potential markets include battery powered, handheld,
automotive, computer, industrial and cost sensitive
consumer products. A description of each section is given
below with the representative block diagram shown in
Figure 11.

Oscillator

The oscillator frequency is programmed by resistor RT.
The charge to discharge ratio is controlled to yield a 95%
maximum duty cycle at the switch outputs. During the fall
time of the internal sawtooth waveform, the oscillator
generates an internal blanking pulse that holds the inverting
input of the AND gates high, disabling the output switching
MOSFET s. The internal sawtooth waveform has a nominal
peak voltage of 3.3 V and a valley voltage of 1.7 V.

Pulse Width Modulators

Both pulse width modulators consist of a comparator with
the oscillator ramp voltage applied to the noninverting input,
while the error amplifier output is applied to the inverting
input. A third input to the comparator has a 0.5 mA typical
current source that can be used to implement soft start.
Output switch conduction is initiated when the ramp
waveform is discharged to the valley voltage. As the ramp
voltage increases to a voltage that exceeds the error
amplifier output, the latch resets, terminating output
MOSFET conduction for the duration of the oscillator ramp.
This PWM/latch combination prevents multiple output
pulses during a given oscillator cycle.

Each PWM circuit is enabled by a logic input. When
disabled, the entire block is turned off, drawing only leakage
current from the power source. Shared circuits, like the

5.0

REFERENCE VOLTAGE (V)

4.0

3.0

2.0

1.0

RT = 169 k
TA = 25°C

0

00

VDD LEVEL (V)

Figure 10. VA, V

versus V

ref

DD

V

A

V

ref

reference and oscillator, can be activated by either EN
or EN2.

Circuit #1 has an ELD output which may be used to drive
an LCD or backlight. Its output frequency is the oscillator
frequency divided by 1024.

Error Amplifiers and Reference

Each error amplifier is provided with access to both
inverting and noninverting inputs, and the output. The Error
Amplifiers’ Common Mode Input Range is 0 to 2.5 V. The
amplifiers have a minimum dc voltage gain of 60 dB. The

1.25 V reference has an accuracy of ±4.0% at room
temperature.

External loop compensation is required for converter
stability. A simple low–pass filter is formed by connecting
a resistive divider from the output to the error amplifier
inverting input, and a series resistor–capacitor from the error
amplifier output also to the to the inverting input. The step
down converter is easiest to compensate for stability. The
step–up and voltage inverting configurations, when
operated as continuous conduction boost or flyback
converters, are more difficult to compensate, and may
require a lower loop design bandwidth.

MOSFET Switch Outputs

The output MOSFET s are designed to switch a maximum
of 60 V, with a peak drain current capability of 500 mA. In
circuit #1 an additional DRV1 output is provided for
interfacing with an external MOSFET.The gates of the
MOSFETs are held low when the circuit is disabled.

Auxiliary Output Voltages

Output voltages V0 through V4 are provided for use as
references or bias voltages. V0 is the circuit #2 output
voltage, when an internal FET switch is activated. The other
auxiliary output voltages are proportional to VB. The
amplifiers for V1 and V2 are powered from V0, while the
amplifiers for V3 and V4 are powered from VDD.

1

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6

EL

Panel

MC34271

Figure 11. Representative Block Diagram Electroluminescent Backlight Configuration

SW

V

B

169 k

Brightness

DAC

1

32

DS

1

1

EN

1

26

31
30

27

23
22

21
20

24

8

2

3

4

5

Drv

Sync
R

T

Ref

FB

1

Comp
SS

1

Ref

FB

2

Comp
SS

2

DS

1

÷ 2

V

ref

1.25 V
1

1

2

2

2

V

DD

Circuit #1 Bias Supply

÷ N

OSC

S
R

En

S

Q

R

Q

En

V

DD

V

DD2

Circuit #2

Bias Supply

D

1

7

S

6

1

ELD

9

V

DD

Mode

D

S

V

V

V

11

10

2

18
19

2

B

17

V

0

16

1

15

0

V

1

“On/Off”

V

DD

V

B

6.0 V to 30 V

V

2

V

3

V

4

LCD

Display

V

V

DD2

DD2

V

2

14

V

3

13

V

4

12

25

EN

2

V

A

28

Gnd

29

BIAS

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7

MC34271

Figure 12. Auxiliary Supply Configuration

12 V

V

169 k

B

LCD

Contrast

DAC

SW

1

32

DS

1

1

EN

1

26

31
30

27

23
22

21
20

24

8

2

3

4

5

Drv

Sync
R

T

Ref

FB

1

Comp
SS

1

Ref

FB

2

Comp
SS

2

DS

2

V

1

÷ 2

V

ref

1.25 V
1

1

2

2

DD

Circuit #1 Bias Supply

÷ N

OSC

S
R

En

En

S

Q
R

Q

Circuit #2

Bias Supply

V

V

DD

DD2

D

1

7

S

6

1

ELD

9

V

DD

Mode

D

S

V

V

V

11

10

2

18
19

2

B

17

V

0

16

1

15

0

V

1

12 V

–27 V

V

DD

5.0 V to 16 V

V

B

6.0 V to 30 V

25

EN

2

V

A

28

Gnd

29

BIAS

V

V

DD2

DD2

V

2

14

V

3

13

V

4

12

V

2

V

3

V

4

LCD

Display

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8

2.2 M

160 k

8.25 k

9.1 k

MC34271

Figure 13. EL PANEL Drive Circuit

Vin 6.0 V

+

MC34271

SW

1

32

EN

1

26

31
30

V

ref

27

0.1
µF

V

DD

Drv

8

1

÷ 2

Sync
R

T

V

ref

1.25 V

Ref

2

1

Circuit #1 Bias Supply

÷ N

OSC

S
R

D

En

S

Q

R

Q

1

7

S

6

1

ELD

V

DD

Mode

400 Hz

9

0.1
µF

11

10

D

2

18

S

19

2

10 µF

34

4T

#364T#36

65

10

2.2 k

MR856

8

1

7

MPSA44
120T
#36

2

MR856

MTP3055EL

120T
#36

0.22 µF
200 V

15 k

EL

PANEL

1.0 k

1.0 k

8.2 k

22 k

1.0 k

10 k

V

B

4.3 M

DAC

15 pF

0.1 µF

MMBT2907

FB

3

1

Comp

4

1

SS

1

5

DS

1

1

Ref

2
23
22

FB

2

Comp

2

21

SS

2

20

DS

2
24

25

EN

2

V

A

28

Gnd

29

BIAS

V

DD

V

DD2

Circuit #2

Bias Supply

V

V

DD2

DD2

V

B

17

V

0

16

V

1

15

V

2

14

V

3

13

V

4

12

V

0

V

1

V

2

V

3

V

4

LCD

Display

V

B

NOTES::1. Transformer information TDK Core # PC40EEM12.7/13.7–Z

Bobbin # BEPC–10–118G 2 mil gap. LP = 1.6 µhy.

2.EL PANEL: DUREL 3/SL ORANGE

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9

L

24 17

25

MC34271

P ACKAGE DIMENSIONS

QFP–32

FB SUFFIX

CASE 873–01

ISSUE A

16

L

–C–

SEATING
PLANE

–A–

C

S S

S S

–B–

B

V

M

M

B

0.20 (0.008) C A–B D

DETAIL A

32

9

81

0.05 (0.002) A–B

–D–

A

0.20 (0.008) A–B D

0.05 (0.002)

M

A–B

S S

C

S

0.20 (0.008) A–B D

M

E

H

G

S S

H

–H–

DETAIL C

DATUM
PLANE

0.01 (0.004)

M

M

0.20 (0.008) H A–B D

BASE METAL

B

P

–A–,–B–,–D–

DETAIL A

F

J

N

D

0.20 (0.008) A–B D

M

S S

C

SECTION B–B

VIEW ROTATED 90° CLOCKWISE

–H–

DATUM

PLANE

DETAIL C

NOTES:

U

T

R

K

Q

X

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.

4. DATUMS –A–, –B– AND –D– TO BE DETERMINED AT
DATUM PLANE –H–.

5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –C–.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE –H–.

7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.

MILLIMETERS INCHES

MIN MINMAX MAX

DIM

A

6.95
B
C
D
E
F

G

H
J
K
L

M

N
P

Q

R
S
T
U
V
X

7.10

6.95

7.10

1.40

1.60

0.273

0.373

1.30

1.50

0.273

0.80 BSC

–

0.20

0.119

0.197

0.33

0.57

5.6 REF

6°

8°

0.119

0.135

0.40 BSC

5°

10°

0.15

0.25

8.85

9.15

0.15

0.25

5°

11°

8.85

9.15

1.0 REF 0.039 REF

0.280

0.274

0.280

0.274

0.063

0.055

0.015

0.010

0.059

0.051
–

0.010

–

0.031 BSC

0.008

–

0.008

0.005

0.022

0.013

0.220 REF
8°

6°

0.005

0.005

0.016 BSC

10°

5°

0.010

0.006

0.360

0.348

0.010

0.006
11°

5°

0.360

0.348

http://onsemi.com

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Notes

MC34271

http://onsemi.com

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MC34271

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
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MC34271/D