The MC34152/MC33152 are dual noninverting high speed drivers
specifically designed for applications that require low current digital signals to
drive large capacitive loads with high slew rates. These devices feature low
input current making them CMOS/LSTTL logic compatible, input hysteresis
for fast output switching that is independent of input transition time, and two
high current totem pole outputs ideally suited for driving power MOSFETs.
Also included is an undervoltage lockout with hysteresis to prevent system
erratic operation at low supply voltages.
Typical applications include switching power supplies, dc–to–dc
converters, capacitor charge pump voltage doublers/inverters, and motor
controllers.
This device is available in dual–in–line and surface mount packages.
• Two Independent Channels with 1.5 A Totem Pole Outputs
• Output Rise and Fall Times of 15 ns with 1000 pF Load
• CMOS/LSTTL Compatible Inputs with Hysteresis
• Undervoltage Lockout with Hysteresis
• Low Standby Current
• Efficient High Frequency Operation
• Enhanced System Performance with Common Switching Regulator
The MC34152 is a dual noninverting high speed driver
specifically designed to interface low current digital circuitry
with power MOSFETs. This device is constructed with
Schottky clamped Bipolar Analog technology which offers a
high degree of performance and ruggedness in hostile
industrial environments.
Input Stage
The Logic Inputs have 170 mV of hysteresis with the input
threshold centered at 1.67 V. The input thresholds are
insensitive to VCC making this device directly compatible with
CMOS and LSTTL logic families over its entire operating
voltage range. Input hysteresis provides fast output switching
that is independent of the input signal transition time,
preventing output oscillations as the input thresholds are
crossed. The inputs are designed to accept a signal
amplitude ranging from ground to VCC. This allows the output
of one channel to directly drive the input of a second channel
for master–slave operation. Each input has a 30 kΩ
pull–down resistor so that an unconnected open input will
cause the associated Drive Output to be in a known low state.
Output Stage
Each totem pole Drive Output is capable of sourcing and
sinking up to 1.5 A with a typical ‘on’ resistance of 2.4 Ω at
1.0 A. The low ‘on’ resistance allows high output currents to
0
04.08.01216
VCC, SUPPLY VOLTAGE (V)
be attained at a lower VCC than with comparative CMOS
drivers. Each output has a 100 kΩ pull–down resistor to keep
the MOSFET gate low when VCC is less than 1.4 V. No over
current or thermal protection has been designed into the
device, so output shorting to VCC or ground must be avoided.
Parasitic inductance in series with the load will cause the
driver outputs to ring above VCC during the turn–on transition,
and below ground during the turn–off transition. With CMOS
drivers, this mode of operation can cause a destructive
output latch–up condition. The MC34152 is immune to output
latch–up. The Drive Outputs contain an internal diode to V
CC
for clamping positive voltage transients. When operating with
VCC at 18 V, proper power supply bypassing must be
observed to prevent the output ringing from exceeding the
maximum 20 V device rating. Negative output transients are
clamped by the internal NPN pull–up transistor. Since full
supply voltage is applied across the NPN pull–up during the
negative output transient, power dissipation at high
frequencies can become excessive. Figures 19, 20, and 21
show a method of using external Schottky diode clamps to
reduce driver power dissipation.
Undervoltage Lockout
An undervoltage lockout with hysteresis prevents erratic
system operation at low supply voltages. The UVLO forces
the Drive Outputs into a low state as VCC rises from 1.4 V to
MOTOROLA ANALOG IC DEVICE DATA
5
Page 6
MC34152 MC33152
the 5.8 V upper threshold. The lower UVLO threshold is 5.3 V ,
yielding about 500 mV of hysteresis.
Power Dissipation
Circuit performance and long term reliability are enhanced
with reduced die temperature. Die temperature increase is
directly related to the power that the integrated circuit must
dissipate and the total thermal resistance from the junction to
ambient. The formula for calculating the junction temperature
with the package in free air is:
TA + PD (R
TJ=
where:
R
Junction Temperature
TJ=
Ambient Temperature
TA=
Power Dissipation
PD=
Thermal Resistance Junction to Ambient
=
θJA
There are three basic components that make up total
power to be dissipated when driving a capacitive load with
respect to ground. They are:
PQ + PC + PT
PD=
where:
PQ=
Quiescent Power Dissipation
PC=
Capacitive Load Power Dissipation
PT=
Transition Power Dissipation
The quiescent power supply current depends on the
supply voltage and duty cycle as shown in Figure 16. The
device’s quiescent power dissipation is:
PQ=
VCC (I
where:
I
CCL
=
Supply Current with Low State Drive
Outputs
I
=
CCH
Supply Current with High State Drive
Outputs
D=
Output Duty Cycle
The capacitive load power dissipation is directly related to
the load capacitance value, frequency, and Drive Output
voltage swing. The capacitive load power dissipation per
driver is:
VCC (VOH – VOL) CL f
PC=
where:
VOH=
VOL=
CL=
f=
High State Drive Output Voltage
Low State Drive Output Voltage
Load Capacitance
Frequency
When driving a MOSFET , the calculation of capacitive load
power PC is somewhat complicated by the changing gate to
source capacitance CGS as the device switches. T o aid in this
calculation, power MOSFET manufacturers provide gate
charge information on their data sheets. Figure 17 shows a
curve of gate voltage versus gate charge for the Motorola
MTM15N50. Note that there are three distinct slopes to the
curve representing different input capacitance values. To
CCL
)
θJA
[1–D] + I
CCH
[D])
completely switch the MOSFET ‘on,’ the gate must be
brought to 10 V with respect to the source. The graph shows
that a gate charge Qg of 110 nC is required when operating
the MOSFET with a drain to source voltage VDS of 400 V.
Figure 17. Gate–to–Source V oltage
versus Gate charge
16
MTM15B50
ID = 15 A
°
C
TA = 25
12
8.0
4.0
2.0 nF
, GATE–T O–SOURCE VOL TAGE (V)
GS
V
0
04080120160
VDS= 100 VVDS= 400 V
8.9 nF
CGS =
Qg, GATE CHARGE (nC)
∆
Q
g
∆
V
GS
The capacitive load power dissipation is directly related to the
required gate charge, and operating frequency. The
capacitive load power dissipation per driver is:
P
C(MOSFET)
= VCC Qg f
The flat region from 10 nC to 55 nC is caused by the
drain–to–gate Miller capacitance, occurring while the
MOSFET is in the linear region dissipating substantial
amounts of power. The high output current capability of the
MC34152 is able to quickly deliver the required gate charge
for fast power efficient MOSFET switching. By operating the
MC34152 at a higher VCC, additional charge can be provided
to bring the gate above 10 V. This will reduce the ‘on’
resistance of the MOSFET at the expense of higher driver
dissipation at a given operating frequency.
The transition power dissipation is due to extremely short
simultaneous conduction of internal circuit nodes when the
Drive Outputs change state. The transition power dissipation
per driver is approximately:
PT ≈ VCC (1.08 VCC CL f – 8 x 10–4)
PT must be greater than zero.
Switching time characterization of the MC34152 is
performed with fixed capacitive loads. Figure 13 shows that
for small capacitance loads, the switching speed is limited by
transistor turn–on/off time and the slew rate of the internal
nodes. For large capacitance loads, the switching speed is
limited by the maximum output current capability of the
integrated circuit.
6
MOTOROLA ANALOG IC DEVICE DATA
Page 7
MC34152 MC33152
LAYOUT CONSIDERATIONS
High frequency printed circuit layout techniques are
imperative to prevent excessive output ringing and
overshoot. Do not attempt to construct the driver circuiton wire–wrap or plug–in prototype boards. When driving
large capacitive loads, the printed circuit board must contain
a low inductance ground plane to minimize the voltage spikes
induced by the high ground ripple currents. All high current
loops should be kept as short as possible using heavy copper
runs to provide a low impedance high frequency path. For
Figure 18. Enhanced System Performance with
Common Switching Regulators
V
CC
470.1
6
+
–
5.7V
2
TL494
or
TL594
7
optimum drive performance, it is recommended that the initial
circuit design contains dual power supply bypass capacitors
connected with short leads as close to the VCC pin and
ground as the layout will permit. Suggested capacitors are a
low inductance 0.1 µF ceramic in parallel with a 4.7 µF
tantalum. Additional bypass capacitors may be required
depending upon Drive Output loading and circuit layout.
Proper printed circuit board layout is extremely critical
and cannot be over emphasized.
Figure 19. MOSFET Parasitic Oscillations
V
V
in
R
g
D
100k
1
1N5819
in
4
3
The MC34152 greatly enhances the drive capabilities of common switching
regulators and CMOS/TTL logic devices.
5
100k100k
Series gate resistor Rg may be needed to damp high frequency parasitic oscillations
caused by the MOSFET input capacitance and any series wiring inductance in the
gate–source circuit. Rg will decrease the MOSFET switching speed. Schottky diode
D1 can reduce the driver’s power dissipation due to excessive ringing, by preventing
the output pin from being driven below ground.
Figure 20. Direct Transformer DriveFigure 21. Isolated MOSFET Drive
7
4 X
1N5819
5
100k100k
3
Isolation
Boundary
100k
3
1N
5819
Output Schottky diodes are recommended when driving inductive loads at high
frequencies. The diodes reduce the driver’s power dissipation by preventing the
output pins from being driven above VCC and below ground.
In noise sensitive applications, both conducted and radiated EMI can
be reduced significantly by controlling the MOSFET’s turn–on and
turn–off times.
Figure 24. Dual Charge Pump Converter
VCC = 15V
470.1
+
6
+
–
+
5.7V
2
V
CC
10k
2N3904
330
100k
4
pF
The totem–pole outputs can furnish negative base current for
enhanced transistor turn–off, with the addition of capacitor C1.
7
5
100k100k
6.810
6.810
+
+
1N5819
47
1N5819
47
≈
2 .0V
+ VO
+
– VO
+
CC
≈
–V
CC
3
Output Load Regulation
The capacitor’s equivalent series resistance limits the Drive Output Current to 1.5 A. An
additional series resistor may be required when using tantalum or other low ESR capacitors.
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola
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Opportunity/Affirmative Action Employer.
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10
◊
MOTOROLA ANALOG IC DEVICE DATA
MC34152/D
*MC34152/D*
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