Datasheet MC34065P, MC34065DW, MC33065P, MC33065DW Datasheet (Motorola)

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The MC34065 is a high performance, fixed frequency , dual current mode
controllers. It is specifically designed for off–line and dc–to–dc converter
applications offering the designer a cost effective solution with minimal
external components. This integrated circuit feature a unique oscillator for
precise duty cycle limit and frequency control, a temperature compensated
reference, two high gain error amplifiers, two current sensing comparators,
Drive Output 2 Enable pin, and two high current totem pole outputs ideally
suited for driving power MOSFETs.

Also included are protective features consisting of input and reference
undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting,
and a latch for single pulse metering of each output.

The MC34065 and MC33065 are available in dual–in–line and surface
mount packages.

• Unique Oscillator for Precise Duty Cycle Limit and Frequency Control

• Current Mode Operation to 500 kHz

• Automatic Feed Forward Compensation

• Separate Latching PWMs for Cycle–By–Cycle Current Limiting

• Internally Trimmed Reference with Undervoltage Lockout

• Drive Output 2 Enable Pin

• Two High Current Totem Pole Outputs

• Input Undervoltage Lockout with Hysteresis

• Low Startup and Operating Current

HIGH PERFORMANCE

DUAL CHANNEL CURRENT

MODE CONTROLLER

SEMICONDUCTOR

TECHNICAL DATA

P SUFFIX

PLASTIC PACKAGE

CASE 648

DW SUFFIX

PLASTIC PACKAGE

CASE 751G

(SO–16L)

16

1

16

1

Representative Block Diagram

V

ref

Lockout

5.0 V

Reference

V

ref

Sync Input

R

T

C

T

Voltage

Feedback 1

Compensation 1

Drive Output 2

Enable

Voltage

Feedback 2

Compensation 2

15

1
3

2

4

5

14

13

12

R

R

Undervoltage

Oscillator

+
–

Error

Amp 1

+
–

Error

Amp 2

Gnd 8 Drive Gnd 9

This device contains 208 active transistors.

MOTOROLA ANALOG IC DEVICE DATA

V

CC

Undervoltage

Lockout

Latching

PWM 1

Latching

PWM 2

PIN CONNECTIONS

V

16

CC

Drive
Output 1

7

Current
Sense 1

6

Drive
Output 2

10

Current
Sense 2

11

 Motorola, Inc. 1996 Rev 1

Sync Input

Voltage Feedback 1

Compensation 1
Current Sense 1

Drive Output 1

ORDERING INFORMATION

Device

MC34065DW
MC34065P
MC33065DW
MC33065P

1
2

C

T

3

R

T

4
5
6
7
89

Gnd

(Top View)

Operating

Temperature Range

TA = 0° to +70°C

TA = –40° to +85°C

16

V

CC

15

V

ref

Drive Output 2

14

Enable

13

Voltage Feedback 2

12

Compensation 2

11

Current Sense 2

10

Drive Output 2
Drive Gnd

Package

SO–16L

Plastic DIP

SO–16L

Plastic DIP

1

MC34065 MC33065

MAXIMUM RATINGS

Rating Symbol Value Unit

Total Power Supply and Zener Current (ICC + IZ) 50 mA
Output Current, Source or Sink (Note 1) I

O

Output Energy (Capacitive Load per Cycle) W 5.0 µJ
Current Sense, Enable, and Voltage Feedback Inputs V

in

Sync Input

High State (Voltage) V
Low State (Reverse Current) I

Error Amp Output Sink Current I

IH

IL
O

Power Dissipation and Thermal Characteristics

DW Suffix, Plastic Package Case 751G

Maximum Power Dissipation @ TA = 25°C P
Thermal Resistance, Junction–to–Air R

D

θJA

P Suffix, Plastic Package Case 648

Maximum Power Dissipation @ TA = 25°C P
Thermal Resistance, Junction–to–Air R

Operating Junction Temperature T
Operating Ambient Temperature T

D

θJA

J

A

MC34065 0 to +70
MC33065 –40 to +85

Storage Temperature Range T

NOTE: ESD data available upon request.

stg

1.0 A

–0.3 to +5.5 V

5.5 V

–5.0 mA

10 mA

862 mW
145 °C/W

1.25 W
100 °C/W

+150 °C

–65 to +150 °C

°C

ELECTRICAL CHARACTERISTICS (V

= 15 V [Note 2], RT = 8.2 kΩ, CT = 3.3 nF, for typical values TA = 25°C, for

CC

min/max values TA is the operating ambient temperature range that applies [Note 3].)

Characteristics

Symbol Min Typ Max Unit

REFERENCE SECTION

Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) V
Line Regulation (VCC = 11 V to 15 V) Reg
Load Regulation (IO = 1.0 mA to 10 mA) Reg
Total Output Variation over Line, Load, and Temperature V
Output Short Circuit Current I

ref

line

load

ref

SC

4.9 5.0 5.1 V
– 2.0 20 mV
– 3.0 25 mV

4.85 – 5.15 V
30 100 – mA

OSCILLATOR AND PWM SECTIONS

Total Frequency Variation over Line and Temperature f

VCC = 11 V to 15 V, TA = T

low

to T

high

osc

MC34065 46.5 49 51.5
MC33065 45 49 53

Frequency Change with Voltage (VCC = 11 V to 15 V) ∆f

/∆V – 0.2 1.0 %

osc

Duty Cycle at each Output %

Maximum DC
Minimum DC

max

min

46 49.5 52

– – 0

Sync Input Current µA

High State (Vin = 2.4 V) I
Low State (Vin = 0.8 V) I

NOTES: 1. Maximum package power dissipation limits must be observed.

2.Adjust VCC above the startup threshold before setting to 15 V.

3.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible:
T

= 0°C for the MC34065 T

low

T

= –40°C for the MC33065 T

low

4.This parameter is measured at the latch trip point with VFB = 0 V

5.Comparator gain is defined as

AV

+

= +70°C for MC34065

high

= +85°C for MC33065

high

D

V Compensation

D

V Current Sense

IH

IL

– 170 250
– 80 160

kHz

2

MOTOROLA ANALOG IC DEVICE DATA

MC34065 MC33065

ELECTRICAL CHARACTERISTICS (continued) (V

= 15 V [Note 2], RT = 8.2 kΩ, CT = 3.3 nF, for typical values TA = 25°C, for

CC

min/max values TA is the operating ambient temperature range that applies [Note 3].)

Characteristics UnitMaxTypMinSymbol

ERROR AMPLIFIERS

Voltage Feedback Input (VO = 2.5 V) V
Input Bias Current (VFB = 5.0 V) I
Open Loop Voltage Gain (VO = 2.0 to 4.0 V) A

FB
IB

VOL

2.42 2.5 2.58 V
– – 0.1 –1.0 µA

65 100 – dB
Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 – MHz
Power Supply Rejection Ratio (VCC = 11 V to 15 V) PSRR 60 90 – dB
Output Current mA

Source (VO = 3.0 V, VFB = 2.3 V) I
Sink (VO = 1.2 V, VFB = 2.7 V) I

source

sink

–0.45 –1.0 –

2.0 12 –

Output Voltage Swing V

High State (RL = 15 k to ground, VFB = 2.3 V) V
Low State (RL = 15 k to V

, VFB = 2.7 V) V

ref

OH
OL

5.0 6.2 –
– 0.8 1.1

CURRENT SENSE SECTION

Current Sense Input Voltage Gain (Notes 4 and 5) A
Maximum Current Sense Input Threshold (Note 4) V
Input Bias Current I
Propagation Delay (Current Sense Input to Output) t

PLN(In/Out)

V
th

IB

2.75 3.0 3.25 V/V
430 480 530 mV

– –2.0 –10 µA
– 150 300 ns

DRIVE OUTPUT 2 ENABLE PIN

Enable Pin Voltage V

High State (Output 2 Enabled) V
Low State (Output 2 Disabled) V

Low State Input Current (VIL = 0 V) I

IH

IL

IB

3.5 – V

ref

0 – 1.5

100 250 400 µA

DRIVE OUTPUTS

Output Voltage V

Low State (I

High State(I

Output Voltage with UVLO Activated (VCC = 6.0 V, I
Output Voltage Rise T ime (CL = 1.0 nF) t
Output Voltage Fall T ime (CL = 1.0 nF) t

= 20 mA) V

sink

(I

= 200 mA) – 1.6 2.5

sink

= 20 mA) V

source

(I

= 200 mA) 12 13.4 –

source

= 1.0 mA) V

sink

OL

OH

OL(UVLO)

r
f

– 0.1 0.4

13 13.5 –

– 0.1 1.1 V
– 28 150 ns
– 25 150 ns

UNDERVOLTAGE LOCKOUT SECTION

Startup Threshold V
Minimum Operating Voltage After Turn–On V

CC(min)

th

13 14 15 V

9.0 10 11 V

TOTAL DEVICE

Power Supply Current I

CC

Startup (VCC = 12 V) – 0.6 1.0
Operating (Note 2) – 20 25

Power Supply Zener Voltage (ICC = 30 mA) V

NOTES: 1. Maximum package power dissipation limits must be observed.

2.Adjust VCC above the startup threshold before setting to 15 V.

3.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible:
T

= 0°C for the MC34065 T

low

T

= –40°C for the MC33065 T

low

4.This parameter is measured at the latch trip point with VFB = 0 V

5.Comparator gain is defined as

AV

+

= +70°C for MC34065

high

= +85°C for MC33065

high

D

V Compensation

D

V Current Sense

Z

15.5 17 19 V

mA

MOTOROLA ANALOG IC DEVICE DATA

3

MC34065 MC33065

PIN FUNCTION DESCRIPTION

Pin Function Description

1 Sync Input A narrow rectangular waveform applied to this input will synchronize the oscillator. A dc voltage

2 C

3 R

T

T

4 Voltage Feedback 1 This pin is the inverting input of Error Amplifier 1. It is normally connected to the switching power

5 Compensation 1 This pin is the output of Error Amplifier 1 and is made available for loop compensation.
6 Current Sense 1 A voltage proportional to the inductor current is connected to this input. PWM 1 uses this

7 Drive Output 1 This pin directly drives the gate of a power MOSFET Q1. Peak currents up to 1.0 A are sourced

8 Gnd This pin is the control circuitry ground return and is connected back to the source ground.
9 Drive Gnd This pin is a separate power ground return that is connected back to the power source. It is used

10 Drive Output 2 This pin directly drives the gate of a power MOSFET Q2. Peak currents up to 1.0 A are sourced

11 Current Sense 2 A voltage proportional to inductor current is connected to this input. PWM 2 uses this information

12 Compensation 2 This pin is the output of Error Amplifier 2 and is made available for loop compensation.
13 Voltage Feedback 2 This pin is the inverting input of Error Amplifier 2. It is normally connected to the switching power

14 Drive Output 2 Enable A logic low at this input disables Drive Output 2.
15 V
16 V

ref
CC

within the range of 2.4 V to 5.5 V will inhibit the oscillator.
Timing capacitor CT connects from this pin to ground setting the free–running oscillator frequency

range.
Resistor RT connects from this pin to ground precisely setting the charge current for CT. RT must

be between 4.0 k and 16 k.

supply output through a resistor divider.

information to terminate conduction of output switch Q1.

and sunk by this pin.

to reduce the effects of switching transient noise on the control circuitry .

and sunk by this pin.

to terminate conduction of output switch Q2.

supply output through a resistor divider.

This is the 5.0 V reference output. It can provide bias for any additional system circuitry.
This pin is the positive supply of the control IC. The minimum operating voltage range after startup

is 11 V to 15.5 V.

Figure 1. Timing Resistor versus

Oscillator Frequency

16

3.3 nF

)

14

Ω

12

10

8.0

, TIMING RESISTOR (k

T

R

6.0

4.0
10 k 30 k 50 k 300 k 500 k100 k 1.0 M

5.0 nF

CT=
10 nF

VCC=15V

°

C

TA=25

f

osc, OSCILLATOR FREQUENCY (Hz)

500 pF

1.0 nF

2.2 nF

100 pF

220 pF

330 pF

4

Figure 2. Maximum Output Duty Cycle

50

48

46

44

VCC=15V

42

, DUTY CYCLE MAXIMUM (%)

RT= 4.0 k to 16 k
CL=15pF

max

40

TA = 25

DC

38

10 k 30 k 50 k 300 k 500 k100 k 1.0 M

versus Oscillator Frequency

°

f

osc, OSCILLATOR FREQUENCY (Hz)

Output 2

Output 1

MOTOROLA ANALOG IC DEVICE DATA

MC34065 MC33065

Figure 3. Error Amp Small–Signal

Transient Response

2.55 V

2.50 V

2.45 V

1.0 µs/DIV

Figure 5. Error Amp Open Loop Gain and

Phase versus Frequency

100

80

60

40

20

Gain

VCC=15V
AV= –1.0
TA=25

VCC=15V
VO= 1.5 V to 2.5 V
RL= 100 k

°

C

TA=25

Phase

°

C

0

30

60

90

120

3.0 V

2.5 V

20 mV/DIV

2.0 V

Figure 4. Error Amp Large–Signal

Transient Response

1.0 µs/DIV

Figure 6. Current Sense Input Threshold

versus Error Amp Output Voltage

0.6
VCC = 15 V

0.5

0.4

0.3

0.2

TA = 25°C

TA = 125°C

TA = –55°C

VCC=15V
AV= –1.0

°

C

TA=25

200 mV/DIV

, OPEN LOOP VOL TAGE GAIN (dB)

0

VOL

A

–20

10 100 1.0 k 10 k 100 k 1.0 M 10 M

f, FREQUENCY (Hz)

Figure 7. Reference V oltage Change

versus Source Current

0

VCC = 15 V

–4.0

–8.0

–12

–16

–20

, REFERENCE VOLTAGE CHANGE (mV)

ref

V

∆

–24

0

20 40 60 80 100 120

I

, REFERENCE SOURCE CURRENT (mA)

ref

TA = 25°C

TA = 125°C

TA = –55°C

, EXCESS PHASE (DEGREES)

150

φ

180

0.1

, CURRENT SENSE INPUT THRESHOLD (V)

0

th

V

0 1.0 2.0 3.0 4.0 7.05.0 6.0

120

100

80

60

, REFERENCE SHORT CIRCUIT CURRENT (mA)

–55

SC

I

VO, ERROR AMP OUTPUT VOLTAGE (V)

Figure 8. Reference Short Circuit Current

versus T emperature

VCC=15V

≤

0.1

R

L

–25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (°C)

Ω

MOTOROLA ANALOG IC DEVICE DATA

5

MC34065 MC33065

Figure 9. Reference Load Regulation Figure 10. Reference Line Regulation

, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

O

V

∆

Figure 11. Output Saturation Voltage

versus Load Current

0

V

–1.0

–2.0

CC

TA= –55°C

VCC=15V
IO= 1.0 mA to 10 mA

°

C

TA=25

, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)

O

V

1.0 ms/DIV 1.0 ms/DIV

∆

Figure 12. Output Waveform

Source Saturation

(Load to Ground)

TA=25°C

VCC=15V

µ

s Pulsed Load

80

120 Hz Rate

90% –

VCC= 11 V to 15 V

°

C

TA=25

VCC=15V
CL= 1.0 nF

TA=25

°

C

2.0

TA= –55°C

1.0

, OUTPUT SA TURATION VOLTAGE (V)

sat

V

0

0 200 400 600 800

TA=25°C

IO, OUTPUT LOAD CURRENT (mA)

Gnd

Sink Saturation

(Load to VCC)

10% –

50 ns/DIV

Figure 13. Output Cross Conduction Current Figure 14. Supply Current versus Supply Voltage

32

RT= 8.2 k
CT= 3.3 nF
VFB1,2 = 0 V

24

Current Sense 1,2 = 0 V

°

C

TA=25

16

, SUPPLY CURRENT (mA)

8.0

CC

I

0
0 4.0 8.0 12 16 20

VCC, SUPPLY VOLTAGE (V)

, OUTPUT VOL TAGE 1

O1

, SUPPLY CURRENT

CC

I

, OUTPUT VOL TAGE 2; V

O2

V

100 ns/DIV

VCC=15V
CL=15pF

TA=25°C

10 V/DIV

50 mA/DIV

10 V/DIV

6

MOTOROLA ANALOG IC DEVICE DATA

MC34065 MC33065

OPERA TING DESCRIPTION

The MC34065 series are high performance, fixed
frequency , dual channel current mode controllers specifically
designed for Off–Line and dc–to–dc converter applications.
These devices offer the designer a cost effective solution with
minimal external components where independent regulation
of two power converters is required. The Representative
Block Diagram is shown in Figure 15. Each channel contains
a high gain error amplifier, current sensing comparator, pulse
width modulator latch, and totem pole output driver. The
oscillator, reference regulator, and undervoltage lock–out
circuits are common to both channels.

Oscillator

The unique oscillator configuration employed features
precise frequency and duty cycle control. The frequency is
programmed by the values selected for the timing
components RT and CT. Capacitor CT is charged and
discharged by an equal magnitude internal current source
and sink, generating a symmetrical 50 percent duty cycle
waveform at Pin 2. The oscillator peak and valley thresholds
are 3.5 V and 1.6 V respectively. The source/sink current
magnitude is controlled by resistor RT. For proper operation
over temperature it must be in the range of 4.0 kΩ to 16 kΩ as
shown in Figure 1.

As CT charges and discharges, an internal blanking pulse
is generated that alternately drives the center inputs of the
upper and lower NOR gates high. This, in conjunction with a
precise amount of delay time introduced into each channel,
produces well defined non–overlapping output duty cycles.
Output 2 is enabled while CT is charging, and Output 1 is
enabled during the discharge. Figure 2 shows the Maximum
Output Duty Cycle versus Oscillator Frequency. Note that
even at 500 kHz, each output is capable of approximately
44% on–time, making this controller suitable for high
frequency power conversion applications.

In many noise sensitive applications it may be desirable to
frequency–lock the converter to an external system clock.
This can be accomplished by applying a clock signal as
shown in Figure 17. For reliable locking, the free–running
oscillator frequency should be set about 10% less than the
clock frequency. Referring to the timing diagram shown in
Figure 16, the rising edge of the clock signal applied to the
Sync input, terminates charging of CT and Drive Output 2
conduction. By tailoring the clock waveform symmetry,
accurate duty cycle clamping of either output can be
achieved. A circuit method for this, and multi–unit
synchronization, is shown in Figure 18.

Error Amplifier

Each channel contains a fully–compensated Error
Amplifier with access to the inverting input and output. The
amplifier features a typical dc voltage gain of 100 dB, and a
unity gain bandwidth of 1.0 MHz with 71° of phase margin
(Figure 5). The noninverting input is internally biased at 2.5 V
and is not pinned out. The converter output voltage is
typically divided down and monitored by the inverting input
through a resistor divider. The maximum input bias current is
–1.0 µA which will cause an output voltage error that is equal
to the product of the input bias current and the equivalent
input divider source resistance.

The Error Amp output (Pin 5, 12) is provided for external
loop compensation. The output voltage is offset by two diode

drops (≈1.4 V) and divided by three before it connects to the
inverting input of the Current Sense Comparator. This
guarantees that no pulses appear at the Drive Output
(Pin 7, 10) when the error amplifier output is at its lowest
state (VOL). This occurs when the power supply is operating
and the load is removed, or at the beginning of a soft–start
interval (Figures 20, 21).

The minimum allowable Error Amp feedback resistance is
limited by the amplifier’s source current (0.5 mA) and the
output voltage (VOH) required to reach the comparator’s

0.5 V clamp level with the inverting input at ground. This
condition happens during initial system startup or when the
sensed output is shorted:

R

f(min)

Current Sense Comparator and PWM Latch

The MC34065 operates as a current mode controller,
whereby output switch conduction is initiated by the oscillator
and terminated when the peak inductor current reaches the
threshold level established by the Error Amplifier output.
Thus the error signal controls the peak inductor current on a
cycle–by–cycle basis. The Current Sense Comparator–PWM
Latch configuration used ensures that only a single pulse
appears at the Drive Output during any given oscillator cycle.
The inductor current is converted to a voltage by inserting a
ground–referenced sense resistor RS in series with the
source of output switch Q1. This voltage is monitored by the
Current Sense Input (Pin 6, 11) and compared to a level
derived from the Error Amp output. The peak inductor current
under normal operating conditions is controlled by the
voltage at Pin 5, 12 where:

Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 0.5 V. Therefore the
maximum peak switch current is:

When designing a high power switching regulator it may
be desirable to reduce the internal clamp voltage in order to
keep the power dissipation of RS to a reasonable level. A
simple method to adjust this voltage is shown in Figure 19.
The two external diodes are used to compensate the internal
diodes, yielding a constant clamp voltage over temperature.
Erratic operation due to noise pickup can result if there is an
excessive reduction of the I

A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense input with a
time constant that approximates the spike duration will
usually eliminate the instability , refer to Figure 24.

3.0 (0.5 V))1.4 V

[

Ipk+

0.5 mA

V

(Pin 5, 12)

I

pk(max)

3R

+

pk(max)

+

5800

–1.4V

S

0.5 V
R

S

clamp voltage.

W

MOTOROLA ANALOG IC DEVICE DATA

7

MC34065 MC33065

V

ref

15

Sync Input

R

T

C

T

Voltage

Feedback 1

Compensation 1

Drive Enable

Feedback 2

Compensation 2

14

Voltage

13

12

Figure 15. Representative Block Diagram

VCC16

17 V

+

14 V

–

Drive Output 1
7

Current Sense 1
6

Drive Output 2

10

Current Sense 2

11

+
–

Sink Only

=

Positive True Logic

UVLO

V

ref

PWM

Q

PWM

Q

+
–

V

CC

Reference

R

2.5 V

1
3

2

4

5

+
–

Error

Amp 1

+
–

Error

Amp 2

R

Oscillator

Internal

Bias

20 k

1.0 mA

µ

250

1.0 mA

Current Sense

Comparator 1

2R

0.5 V R

A

2R

0.5 V R

Gnd 8 Drive Gnd 9

Regulator

3.6 V

–
+

Current Sense

Comparator 2

–
+

+
–

+
–

UVLO

Latch 1

S
R

Latch 2

S
R

R

Vin= 15 V

Q1

R

S

Q2

R

S

Figure 16. Timing Diagram

Sync Input

Capacitor C

Compensation 1
Current Sense 1

“Reset” Input

Drive Output 1

Drive Output 2

Compensation 2
Current Sense 2

“Reset” Input

Drive Output 2

T

Latch 1

“Set” Input

Latch 1

Enable

Latch 2

“Set” Input

Latch 2

8

MOTOROLA ANALOG IC DEVICE DATA

MC34065 MC33065

Undervoltage Lockout

Two Undervoltage Lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stages are enabled. The positive power
supply terminal (VCC) and the reference output (V
each monitored by separate comparators. Each has built–in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 14 V and 10 V respectively.
The hysteresis and low startup current makes these devices
ideally suited to off–line converter applications where
efficient bootstrap startup techniques are required
(Figure 28). The V
until the internal circuitry is functional. This comparator has
upper and lower thresholds of 3.6 V and 3.4 V. A 17 V zener
is connected as a shunt regulator from VCC to ground. Its
purpose is to protect the IC and power MOSFET gate from
excessive voltage that can occur during system startup. The
guaranteed minimum operating voltage after turn–on is 1 1 V.

Drive Outputs and Drive Ground

Each channel contains a single totem–pole output stage
that is specifically designed for direct drive of power
MOSFETs. The Drive Outputs are capable of up to ±1.0 A
peak current with a typical rise and fall time of 28 ns with a

1.0 nF load. Internal circuitry has been added to keep the
outputs in a sinking mode whenever an Undervoltage
Lockout is active. This characteristic eliminates the need for
an external pull–down resistor. Cross–conduction current in
the totem–pole output stage has been minimized for high
speed operation, as shown in Figure 13. The average added
power due to cross–conduction with VCC = 15 V is only
60 mW at 500 kHz.

Although the Drive Outputs were optimized for MOSFETs,
they can easily supply the negative base current required by
bipolar NPN transistors for enhanced turn–off (Figure 25).
The outputs do not contain internal current limiting, therefore
an external series resistor may be required to prevent the
peak output current from exceeding the 1.0 A maximum
rating. The sink saturation (VOL) is less than 0.4 V at 100 mA.

comparator disables the Drive Outputs

ref

ref

) are

A separate Drive Ground pin is provided and, with proper
implementation, will significantly reduce the level of switching
transient noise imposed on the control circuitry. This
becomes particularly useful when reducing the I
level. Figure 23 shows the proper ground connections
required for current sensing power MOSFET applications.

Drive Output 2 Enable Pin

This input is used to enable Drive Output 2. Drive Output 1
can be used to control circuitry that must run continuously
such as volatile memory and the system clock, or a remote
controlled receiver, while Drive Output 2 controls the high
power circuitry that is occasionally turned off.

Reference

The 5.0 V bandgap reference is trimmed to ±2.0%
tolerance at TJ = 25°C. The reference has short circuit
protection and is capable of providing in excess of 30 mA for
powering any additional control system circuitry.

Design Considerations

Do not attempt to construct the converter on
wire–wrap or plug–in prototype boards. High frequency

circuit layout techniques are imperative to prevent
pulse–width jitter. This is usually caused by excessive noise
pick–up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout
should contain a ground plane with low current signal and
high current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 µF) connected directly to VCC and
V

may be required depending upon circuit layout. This

ref

provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and the
converter output voltage–divider should be located close to
the IC and as far as possible from the power switch and
other noise generating components.

pk(max)

clamp

MOTOROLA ANALOG IC DEVICE DATA

9

MC34065 MC33065

Figure 17. External Clock Synchronization Figure 18. External Duty Cycle Clamp and

Multi–Unit Synchronization

V

ref

15

External
Sync
Input

220 pF

R

T

The external diode clamp is required if the negative Sync current
is greater than –5.0 mA.

1

3

2

C

T

4

5

R

Bias

R

5.0 k

20 k

Osc

+
–

EA1

2R

0.5 V

R

6

+
–

5

5.0 k
+

2

–

5.0 k

1

C

D

Drive Output 1 = D

max

48

R

Q

S

MC1455

f

+

ǒ

R

A

R

1.08

)

R

A

R

7

3

R

B

Ǔ

R

C

B

B

)

R

B

15

A

1

3

2

+

4

–

5

To additional MC34065’s

Drive Output 2 =

max

R
R

EA1

Osc

R

Bias

R

A

20 k

2R

R0.5 V

A

)

R

B

Figure 19. Adjustable Reduction of Clamp Level Figure 20. Soft–Start Circuit

V

ref
15

1

3

2

4

R2 EA1

5

R1

V

Clamp

R
R

+
–

1.67

[

R2

ǒ

Ǔ

)

1

R1

Osc

)

Bias

20 k

1.0 mA

2R

0.5 V

0.33 x 10

V

Clamp

–3

ǒ

5.0 V

+
_

R

R1R2

R1

V

CC

16

R2

PWM

Latch 1

Ǔ

+
–

S

Q

R

I

pk(max)

Where: 0 ≤ V

ref

+
–

–
+

)

17 V

+

_

V

Clamp

[

R

Clamp

7

6

S

≤ 0.5 V

V

in

Q1

R

S

V

ref
15

1

3

2

4

1.0 M

C

5

R
R

+
–

EA1

t

Soft–Start

Bias

20 k

Osc

1.0 mA

≈

2100 C in µF

2R

0.5 V

R

10

MOTOROLA ANALOG IC DEVICE DATA

MC34065 MC33065

Figure 21. Adjustable Reduction of Clamp Level

with Soft–Start

R1R2

C

R1)R2

V

in

Q1

7

6

R

V

CC

16

V

ref

15

1
3

2

4

R2

5

R1

V

Clamp

MPSA63

[

C

R
R

+
–

EA1

Where: 0 ≤ V

1.67

R2

ǒ

Ǔ

)

1

R1

Bias

Osc

Clamp

20 k

2R

0.5 V

≤ 0.5 V

V

Clamp

t

5.0 V

ref

+
_

–
+

R

I

pk(max)

Soft–Start

+
–

Latch 1

+

PWM

S

Q

R

[

ln

+
–

V

1–

+
_

Clamp

R

S

1

V

3V

Clamp

17 V

C

Figure 22. MOSFET Parasitic Oscillations

V

CC

16

+

5.0 V

ref

+
–

+
–

PWM

Latch 1

S

–
+

S

Series gate resistor Rg may be needed to damp high frequency
parasitic oscillations caused by the MOSFET input capacitance
and any series wiring inductance in the gate–source circuit. R
will decrease the MOSFET switching speed. Schottky diode
D1 is required if circuit ringing drives the output pin below
ground.

Q

R

17 V

–

+

_

7

1N5819

6

R

D1

V

in

Q1

g

R

S

g

Figure 23. Current Sensing Power MOSFET Figure 24. Current Waveform Spike Suppression

V

CC

16

+

5.0 V

ref

+
–

+
_

PWM

Latch 1

S

–

+

Virtually lossless current sensing can be achieved with the implementation
of a SENSEFET power switch. For proper operation during over current
conditions, a reduction of the I
Refer to Figures 19 and 21.

Q

R

17 V

–

+
_

Control Circuitry

Ground to Pin 8

pk(max)

V

in

D

SENSEFET

S

G

7

M

6

R

S

1/4W

clamp level must be implemented.

Power Ground to
Input Source Return

K
Drive Ground

to Pin 9

R

R

I

pk

V

Pin 6

If: SENSEFET = MTP10N10M

Then: V

S

[

R

DM(on)

RS = 200
Pin 6

= 0.075 I

DS(on)

)

V

CC

16

+

5.0 V

ref

+
–

+
–

PWM

Latch 1

S

–

R

S

pk

+

The addition of the RC filter will eliminate instability caused by
the leading edge spike on the current waveform.

Q

R

17 V

–

+
_

7

6

V

in

Q1

R

R

C

S

MOTOROLA ANALOG IC DEVICE DATA

11

MC34065 MC33065

Figure 25. Bipolar Transistor Drive Figure 26. Isolated MOSFET Drive

V

PWM

S

Q

R

V

(Pin 6)

+
–

3R

CC

16

17 V

+

_

7

6

–

1.4

N

P

ǒ

Ǔ

N

S

S

I

B
+
0
–

The totem–pole outputs can furnish negative base current for
enhanced transistor turn–off, with the addition of capacitor C1.

Base Charge

Removal

C1

V

in

R

S

Figure 27. Dual Charge Pump Converter

5.0 V Ref

+
–

+

–

–
+

Ipk+

Latch 1

Isolation

Boundary

D1

C

V

in

Q1

R

N

N

S

P

12 k

1.0 nF

15

14

13

12

VCC= 15 V

16

17 V

5.0 V

R

2.5 V

1
3

2

+

4

–

5

+
–

R

EA1

EA2

Bias

Osc

1.0 mA

250

1.0 mA

20 k

2R

0.5 V

µ

A

2R

0.5 V

R

89

ref

+
–

+
_

–
+

R

–

+

+
–

+
_

PWM

Latch 1

S

Q

R

PWM

Latch 2

S

Q

R
R

+

47

15 10

7

Connect to Pin 4 for

closed–loop regulation.

6

15 10

10

11

1N5819

+

47

)

VO+

1N5819

+

47

Output Load Regulation

IO (mA) +VO (V) –VO (V)

0

1.0

5.0
10
50

+

2.5

29.8

28.3

27.9

27.5

24.4

+V

≈

2.0 V

O

CC

R2
R1

R2

ǒ

+

R1

)

–V

Ǔ

1

≈

O

–14.7
–13.4
–12.9
–12.5

–9.5

–V

CC

12

The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor
may be required when using tantalum or other low ESR capacitors. The positive output can provide excellent line and
load regulation by connecting the R2/R1 resistor divider as shown.

MOTOROLA ANALOG IC DEVICE DATA

75 k

16.2 k

92 to 138 Vac

4.7 k

5.6 k

1.0 M

1/2
4N35

47 k

47 k

4.7
nF

15

100
pF

14

13

180
pF

12

1
3

2
4

5

10 Cold

<1 Hot

T

3.0 A

0.22

+
–

+
–

R
R

EA1

EA2

Osc

T1

Bias

2R

0.5 V

0.5 V

20 k

2R

MC34065 MC33065

Figure 28. 125 Watt Off–Line Converter

MDA

+

270

56 k

16

+
–

PWM

Latch 1

S

Q

R

PWM

Latch 2

S

Q

R
R

98

+
–

+
_

ref

100

7

6

10

11

0.05

970G5

5.0 V

+
_

–

+

R

–
+

R

MUR110

22

MTD
2N50

1.0 k

470
pF

470 pF

22

1.0 k

T2

12 k

3.3

MUR110

220

10 k

330

pF

3300

pF
1N

4937

MTH
8N45

0.082

L1

++

MUR415

T3

0.001

10

MUR415

MUR

440

100

0.001

Shutdown

L3

+

1000

1000

+

L2
MPS

A20

+

10 k

Output 2

1N4148

L4

0.01

TL431A

330

1/2
4N35

68 k

0.013.3 k

330

10

10

10

51 k

100

1.3 k

+

+

+

+

9.0 V

0.1 A

RTN

12 V

1.0 A
RTN

–12 V

1.0 A
100 V

1.0 A

RTN

Test Conditions Results

Line Regulation

100 V Output
±12 V Outputs

9.0 V Output

Load Regulation

100 V Output
±12 V Outputs

9.0 V Output

Output Ripple

100 V Output
±12 V Outputs

9.0 V Output

Short Circuit Current

100 V Output
±12 V Outputs

9.0 V Output

Efficiency

Vin = 92 to 138 Vac

IO = 1.0 A
IO = ±1.0 A
IO = 0.1 A

Vin = 115 Vac

IO = 0.25 A to 1.0 A
IO = ±0.25 A to ±1.0 A
IO = 0.08 A to 0.1 A

Vin = 115 Vac

IO = 1.0 A
IO = ±1.0 A
IO = 0.1 A

Vin = 115 Vac, RL = 0.1 Ω

Vin = 115 Vac, PO = 125 W

∆ = 40 mV or ±0.02%
∆ = 32 mV or ±0.13%
∆ = 55 mV or ±0.31%

∆ = 50 mV or ±0.025%
∆ = 320 mV or ±1.2%
∆ = 234 mV or ±1.3%

40 mVpp

100 mVpp

60 mVpp

4.3 A
17 A

Output Hiccups

86%

468 µH per section at 2.5 A,

T1 –

Coilcraft E3496A.
Primary: 156 Turns, #34 AWG

T2 –

Primary Feedback: 19 Turns, #34 AWG
Secondary: 17 Turns, #28 AWG
Core: TDK H7C1EE22–Z
Bobbin: BE22–6H

Gap: ≈0.001″ for a primary
inductance of 6.8 mH

Primary: 56 Turns, #23 AWG

T3 –

(2 strands) Bifiliar Wound
Secondary: ±12 V, 4 Turns, #23 AWG
(4 strands) Quadfiliar Wound
Secondary 100 V: 32 Turns, #23 AWG
(2 strands) Bifiliar Wound
Core: Ferroxcube EEC 40–3C8
Bobbin: Ferroxcube 40–1112CP
Gap: ≈0.030″ for a primary

inductance of 212 µH
L1, L3, L4 –
L2 –

25 µH at 1.0 A, Coilcraft Z7157.

10 µH at 3.0 A, Coilcraft PCV–0–010–03.

MOTOROLA ANALOG IC DEVICE DATA

13

MC34065 MC33065

Figure 29. 125 Watt Off–Line Converter

5 11/16

″

4 1/2

″

3AG Fuse

4N35

5.4 k

16.2 k

1.0 M

100

Circuit View

1N4140

.01

0.001

1.0 kV

3300 pF 500 V

*

10 µF

16 V

L2

12 k 2.0 W

100 µF

200 V

1N4937

AC Input 9.0 V 100 V 12 V–12 V

3.3 k

TL431

1.3 k

MDA97005

MUR110

100 µF

16 V

56 k 5.0 W

Ω

5.0 W

3300

10 k
3300

L1

0.01

6.9 k
51 k

220 µF

16 V

MUR110

T2

270 µF

250 V

1N4937
10 k 5.0 W

330 pF

1.0 kV

MTD2N50

0.082

Ω

2.0 W

4700

470

0.22 µF 250 V

0.05 µF 250 V

4.7 k

229

1.0 k

AC Line Input

T

T1

75 k

MC34065

47 k

180

1.0 k

MP5A30

47 k

3.3

470

229

T3

10 µF

16 V

MTH8N45

10 µF

16 V

100 µF

200 V

0.001

1.0 kV

Heat Sink

L3 L4

MUR440

MUR415

198

MUR415

1000 µF

16 V

1000 µF

16 V

14

Component View

±

*100 V and

12 V Shutdown

MOTOROLA ANALOG IC DEVICE DATA

MC34065 MC33065

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC PACKAGE

CASE 648–08

–A–

916

B

18

F

C

S

–T–

H

G

D

16 PL

0.25 (0.010) T

K

M

A

–A–

16 9

–B– P8X

0.010 (0.25)

81

D16X

0.010 (0.25) B

M

S

A

T

S

C

–T–

G14X

K

SEATING
PLANE

ISSUE R

SEATING
PLANE

J

M

DW SUFFIX

PLASTIC PACKAGE

CASE 751G–02

(SO–16L)

ISSUE A

M

J

F

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

L

M

M

B

R

X 45

_

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 10.15 10.45 0.400 0.411
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7

____

P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029

MILLIMETERSINCHES

____

INCHESMILLIMETERS

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

How to reach us:
USA/EUROPE/ Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 3–14–2 Tatsumi Koto–Ku, T okyo 135, Japan. 03–81–3521–8315

MFAX: RMF [e-mail] – TOUCHT ONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T ., Hong Kong. 852–26629298

MOTOROLA ANALOG IC DEVICE DATA

◊

MC34065/D

15

*MC34065/D*