Datasheet MC33680FTB, MC33680FTBR2 Datasheet (MOTOROLA)

MC33680

N

V

Dual DC-DC Regulator for
Electronic Organizer

The MC33680 is a dual DC–DC regulator designed for electronic
organizer applications. Both regulators apply
Pulse–Frequency–Modulation (PFM). The main step–up regulator
output can be externally adjusted from 2.7V to 5V. An internal
synchronous rectifier is used to ensure high efficiency (achieve 87%).
The auxiliary regulator with a built–in power transistor can be
configured to produce a wide range of positive voltage (can be used
for LCD contrast voltage). This voltage can be adjusted from +5V to
+25V by an external potentiometer.

The MC33680 has been designed for battery powered hand–held
products. With the low start–up voltage from 1V and the low quiescent
current (typical 35 µA); the MC33680 is best suited to operate from 1
to 2 AA/ AAA cell. Moreover, supervisory functions such as low
battery detection, CPU Power–Good signal, and back–up battery
control, for lithium battery or supercap are also included in the chip.

FEATURES:

• Low Input Voltage, 1V up

• Low Quiescent Current in Standby Mode: 35µA typical

• PFM and Synchronous Rectification to ensure high efficiency

(87% @60mA Load)

• Adjustable Main Output: +2.7V to +5V

nominal 3.3V @ 100mA max, with 1.8V input

• Auxiliary Output Voltage: +5V to +25V

+5V @ 25mA max, with 1.8V input
+25V @ 15mA max, with 1.8V input

• Current Limit Protection

VAUXSW

VAUXEMR

LIBATIN

LIBATOUT

NC

MAINGND

VMAINSW

VMAIN

• Power–Good Signal with Programmable Delay

• Battery Low Detection

• Lithium Battery or Supercap Back–up

• 32–Pin LQFP Package

APPLICATIONS:

• Digital Organizer and Dictionary

• Dual Output Power Supply (For MPU, Logic, Memory, LCD)

• Handheld Battery Powered Device (1–2 AA/AAA cell)

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132

32–LEAD LQFP

FTB SUFFIX

CASE 873A

PIN CONNECTIONS &

DEVICE MARKING

NC

VAUXBASE

VAUXCHG

VAUXFBN

VAUXBDVNCVAUXFBP

MC33680

FTB

AWLYYWW

VDD

VBAT

VBAT

VMAINFB

(Top View)

VREF

AGND

PDELAY

VAUXEN

NC
DGND
LIBATCL
LIBATON
LOWBATB
PORB
DGND
LOWBATSE

IREF

 Semiconductor Components Industries, LLC, 2000

May, 2000 – Rev. 3

ORDERING INFORMATION

Device Package Shipping

MC33680FTB LQFP 1250 Tray / Drypack
MC33680FTBR2 LQFP 1800 / Tape & Reel

1 Publication Order Number:

MC33680/D

MC33680

VBAT

RIref
480 k

300 k
RLBa

LOBAT–

SEN

900 k
RLBb

DGND

PORB

W

8

W

9

W

10

11

IREF7AGND

Power–On

Reset

x2

Figure 1. Detailed Application Block Diagram

+ +

CPOR

80 nF

VREF

6

5

CVDD

20 mF

PDELAY

+ve Edge Delay

for Max. ON Time

for Min. OFF Time

VDD

4

RSQ

1–SHOT

3

5

ZLC

Qb

VBAT2VBAT

V

DGND

VBAT

COMP3

DD

RSQ

ILIM

1

VMAINFB

M1

COMP2

CMAINb

100 pF

RMAINb
1000 k

senseFET

V

DD

DGND

VBAT

L1

33 mH

MBRA130LT1

W

31
VMAINSW

VMAIN

32

M2

CMAIN
100 mF

VMAINGND
30

LIBATOUT

28

LIBATIN

27

VBAT

+

LOWBATB

LIBATON

LIBATCL

DGND

12

13

14

15

VAUXEN

Voltage

Reference

Voltage Reference
Current Bias
& Supervisory

1.22 V

AGND

0.85 V,

1.1 V

Lithium
Battery
Backup

17

0.5 V

VAUXFBP

COMP1

Main Regulator
with Synchronous Rectifier

VCOMP

COMP1

18

20
VAUXFBN

200 k

W

RAUXa

VCOMP

+ve Edge Delay

for Max. ON Time

RSQ

1–SHOT

for Min. OFF Time

Auxiliary Regulator

2200 k

W

RAUXb

VAUXBDV

Qb

L2

AGND

senseBJT

Q1

ILIM

COMP2

AGND

21

VBAT

22
VAUXCHG

23
VAUXBASE

33 mH

MBRA140T3

25

VAUXSW

CAUX

30 mF

VAUXEMR

26

+

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2

TIMING DIAGRAMS

VBAT

VMAIN

PORB

VAUXEN

V

MAINreg

– 0.15 V

MC33680

Figure 2. Startup Timing

T

POR

t

PORC

+

V

MAINreg

1.22

ǒ

0.5

Ǔ

C

RIref

por

VBAT

LOWBATB

VMAIN

PORB

LOWBAT Threshold

Figure 3. Power Down Timing

V

MAINreg

– 0.5 V

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3

Pin

ББББББ

ББББББ

ББББББ

ББББББ

ББББББ

ББББББ

ББББББ

ББББББ

ББББББ

ББББББ

Á

ББББББ

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

No.

1
2
3
4
5
6
7
8
9

10

ÁÁ

11

ÁÁ

12
13

14

ÁÁ

15
16
17
18
19
20
21
22
23

ÁÁ

24
25
26
27
28
29
30
31
32

MC33680

PIN FUNCTION DESCRIPTION

Function Type/Direction Description

VMAINFB

VBAT
VBAT

VDD

PDELAY

VREF

AGND

IREF

LOWBATSEN

DGND

ÁÁÁÁ

PORB

ÁÁÁÁ

LOWBATB

LIBATON

LIBATCL

ÁÁÁÁ

DGND

NC

VAUXEN

VAUXFBP

NC
VAUXFBN
VAUXBDV
VAUXCHG

VAUXBASE

ÁÁÁÁ

NC

VAUXSW

VAUXEMR

LIBATIN

LIBATOUT

NC

VMAINGND

VMAINSW

VMAIN

Analog / Input

Power
Power

Analog / Output

Analog / Input

Analog / Output

Analog Ground

Analog / Input
Analog / Input

Digital Ground

БББББ

CMOS / Output

БББББ

CMOS / Output

CMOS / Input

CMOS / Input

БББББ

Digital Ground

CMOS / Input
Analog / Input

Analog / Input

Power
Analog / Output
Analog / Output

БББББ

Analog / Output
Analog / Output

Analog / Input

Analog / Output

Power Ground

Analog / Input

Analog / Output

Feedback pin for VMAIN
Main battery supply
Main battery supply
Connect to decoupling capacitor for internal logic supply
Capacitor connection for defining Power–On signal delay
Bandgap Reference output voltage. Nominal voltage is 1.25V

Resistor connection for defining internal current bias and PDELAY current
Resistive network connection for defining low battery detect threshold

БББББББББББББББББ

Active LOW Power–On reset signal

БББББББББББББББББ

Active LOW low battery detect output
microprocessor control signal for Lithium battery backup switch, the switch is

ON when LIBATON=HIGH and LIBATCL=HIGH
microprocessor control signal for Lithium battery backup switch, if it is HIGH,

БББББББББББББББББ

the switch is controlled by LIBATON, otherwise, controlled by internal logic

no connection
VAUX enable, Active high
Feedback pin for VAUX
no connection
Feedback pin for VAUX
VAUX BJT base drive circuit power supply
test pin
test pin

БББББББББББББББББ

no connection
Collector output of the VAUX power BJT
Emitter output of the VAUX power BJT
Lithium battery input for backup purposes
Lithium battery output
no connection
Ground for VMAIN low side switch
VMAIN inductor connection
VMAIN output

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4

MC33680

ABSOLUTE MAXIMUM RATINGS (T

Parameter

Power Supply Voltage
Digital Pin Voltage V
General Analog Pin Voltage V
Pin VAUXSW to Pin VAUXEMR Voltage (Continuous) V

Pin VMAINSW to Pin VMAIN Voltage (Continuous)
Operating Junction Temperature
Ambient Operating Temperature
Storage Temperature

STATIC ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VP = 1.8V, I

= 25°C, unless otherwise noted.)

A

Symbol Min Max Unit

V

BAT

digital

analog

AUXCE

V

syn

Tj

(max)

T

a

T

stg

load

–0.3

7.0
–0.3 7.0 Vdc
–0.3 7.0 Vdc
–0.3 30 Vdc

0.3

150

0

–50

70

150

= 0 mA, TA = 0 to 70°C unless

Vdc

Vdc

°C
°C
°C

otherwise noted.)

Rating

Operating Supply Voltage

1

VMAIN output voltage V
VMAIN output voltage range
VMAIN output current
VMAIN maximum switching frequency

2

3

4

VMAIN peak coil static current limit I

Symbol Min Typ Max Unit

V

BAT

main

V

main_range

I

3.3_1.8

Freq

max_VM

LIM_VM

1.0 V

3.1 3.3 3.5 V

2.7 5.0 V
200 mA
100 kHz

0.85 1.0 1.15 A
VAUX output voltage range VAUX_range 5.0 25 V
VAUX maximum switching frequency Freq
VAUX peak coil static current limit I
Quiescent Supply Current at Standby Mode

5

Reference Voltage @ no load Vref
Battery Low Detect lower hysteresis threshold

6

Battery Low Detect upper hysteresis threshold V
PDELAY Pin output charging current Ichg
PDELAY Pin voltage threshold Vth

NOTE: 1. Output current capability is reduced with supply voltage due to decreased energy transfer. The supply voltage must not be higher than
NOTE: 2. Output voltage can be adjusted by external resistor to the VMAINFB pin.

NOTE: 3. At VBAT = 1.8V, output current capability increases with VBAT .
NOTE: 4. Only when current limit is not reached.
NOTE: 5. This is average current consumed by the IC from VDD, which is low–pass filtered from VMAIN, when only VMAIN is enabled and at no loading.
NOTE: 6. This is the minimum of ”LOWBATB” threshold for battery voltage, the threshold can be increased by external resistor divider from ”VBA T” to

VMAIN+0.6V to ensure boost operation. Max Start–up loading is typically 1V at 400 µA, 1.8V at 4.4 mA, and 2.2V at 88 mA.

”LOWBATSEN”.

max_VL

LIM_VL

Iq

standby

no_load

V

LOBAT_L

LOBAT_H

PDELAY

PDELAY

1.0 A
35 60 µA

1.16 1.22 1.28 V

0.8 0.85 0.9 V

1.05 1.1 1.15 V

0.8 1.0 1.2 µA

1.16 1.22 1.28 V

120 kHz

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5

MC33680

IN

Eff

,

EFFICIENCY

OF

VAUX

%

OUT_AUX

Eff

,

EFFICIENCY

OF

VMAIN

%

DYNAMIC ELECTRICAL CHARACTERISTICS (Refer to TIMING DIAGRAMS, T

Rating

Minimum PORB to Control delay t

Figure 4. Efficiency of VMAIN versus Output

Current (VMAIN = 3.3 V, L = 33 uH, Various VIN)

90%

)
(

85%

80%

75%

VMAIN

70%

0

10 60 70 80 90 100

I

Vin = 3V
Vin = 1.8V
Vin = 1.5V
Vin = 1V

20 30 40 50
OUT_MAIN

, MAIN OUTPUT CURRENT (mA)

Figure 6. Efficiency of VAUX versus Output

Current (VAUX = 25 V, L2 = 33 uH, Various VIN)

80%
)
(

75%

Symbol Min Typ Max Unit

PORC

Figure 5. Efficiency of VMAIN versus Input

V oltage (VMAIN = 3.3 V, L1 = 33 uH, Various I

90%

85%

80%

, EFFICIENCY OF VMAIN (%)

75%

VMAIN

Eff

70%

1

Figure 7. Efficiency of V AUX versus Input

Voltage (VAUX = 25 V, L2 = 33 uH, Various I

80%

75%

= 0 to 70°C unless otherwise noted.)

A

500 nS

1.5 2 3
VIN, INPUT VOLTAGE (V)

2.5

I

out

I

out

I

out

OUT

= 10mA
= 60mA
= 100mA

OUT

)

)

VAUX

70%

65%

60%

55%
50%

Vin = 3V
Vin = 1.8V
Vin = 1.5V
Vin = 1V

1

357 111315

I

, AUX OUTPUT CURRENT (mA)

9

, EFFICIENCY OF VAUX (%)

VAUX

Eff

70%

65%

60%

55%
50%

I

= 1mA

out

I

= 5mA

out

I

= 10mA

out

I

= 15mA

out

1

1.5 2 2.5 3

, INPUT VOLTAGE (V)

V

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6

MC33680

Eff

,

EFFICIENCY

OF

VAUX

%

IN

OUT_AUX

Figure 8. Efficiency of VAUX versus Output

Current (VAUX = 20 V, L2 = 33 uH, Various VIN)

80%
)
(

75%

70%

65%

VAUX

60%

55%

50%

1

Vin = 3V
Vin = 1.8V
Vin = 1.5V
Vin = 1V

3 5 7 11 13 15

I

OUT_AUX

, AUX OUTPUT CURRENT (mA)

9

Figure 10. Efficiency of VAUX versus Output

Current (VAUX = 5 V, L2 = 82 uH, Various VIN)

85%

80%

75%

70%

65%

, EFFICIENCY OF VAUX (%)

VAUX

Eff

60%

55%

50%

45%

40%

5 1015 3035

1

I

, AUX OUTPUT CURRENT (mA)

Vin = 3V
Vin = 2.4V
Vin = 1.8V
Vin = 1.5V
Vin = 1V

Figure 9. Efficiency of V AUX versus Input

Voltage (VAUX = 20 V, L2 = 33 uH, Various I

80%

75%

70%

65%

60%

, EFFICIENCY OF VAUX (%)

55%

VAUX

Eff

50%

1

1.5 2 2.5 3
VIN, INPUT VOLTAGE (V)

Figure 11. Efficiency of VAUX versus Input

Voltage (VAUX = 5 V, L2 = 82 uH, Various I

85%

80%

75%

70%

, EFFICIENCY OF VAUX (%)

65%

VAUX

Eff

50%

1

1.5

V

2 2.5 320 25

, INPUT VOLTAGE (V)

I

out

I

out

I

out

I

out

= 1mA
= 5mA
= 10mA
= 15mA

I

= 1V

out

I

= 5V

out

I

= 10V

out

I

= 15V

out

I

= 25V

out

OUT

OUT

)

)

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7

MC33680

Figure 12. VMAIN Output Ripple (Medium Load) Figure 13. VMAIN Output Ripple (Heavy Load)

20 uS / div

1: VMAIN = 3.3 V (50 mV/div, AC COUPLED)
2: Voltage at VMAINSW (1 V/div)

1: VMAIN = 3.3 V (50 mV/div, AC COUPLED)
2: Voltage at VMAINSW (1 V/div)

10 uS / div

Figure 14. VAUX Output Ripple (Medium Load) Figure 15. VAUX Output Ripple (Heavy Load)

20 uS / div

1: VAUX = 20 V (50 mV/div, AC COUPLED)
2: Voltage at VAUXSW (10 V/div)

Figure 16. VMAIN Startup and Power–Good Signal

1: VAUX = 20 V (50 mV/div, AC COUPLED)
2: Voltage at VAUXSW (10 V/div)

Figure 17. V AUX Startup

10 uS / div

50 mS / div

1: VMAIN from 1 V to 3.3 V (1 V/div)
2: Voltage of PORB (2 V/div)
3: Voltage of ENABLE (2 V/div)

5 mS / div

1: VAUX from 1.8 V to 20 V (5 V/div)
2: VAUXEN (2 V/div)

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8

MC33680

DET AILED OPERATING DESCRIPTION

General

The MC33680 is a dual DC–DC regulator designed for
electronic organizer applications. Both regulators apply
Pulse–Frequency–Modulation (PFM). The main boost
regulator output can be externally adjusted from 2.7V to 5V .
An internal synchronous rectifier is used to ensure high
efficiency (achieve 87%). The auxiliary regulator with a
built–in power transistor can be configured to produce a
wide range of positive voltage (can be used for LCD contrast
voltage). This voltage can be adjusted from +5V to +25V by
an external potentiometer.

The MC33680 has been designed for battery powered
hand–held products. With the low start–up voltage from 1V
and the low quiescent current (typical 35 µA), the MC33680
is best suited to operate from 1 to 2 AA/ AAA cell.
Moreover, supervisory functions such as low battery
detection, CPU Power–Good signal, and back–up battery
control, are also included in the chip. It makes the MC33680
the best one–chip power management solution for
applications such as electronic organizers and PDAs.

Pulse Frequency Modulation (PFM)

Both regulators apply PFM. With this switching scheme,
every cycle is started as the feedback voltage is lower than
the internal reference. This is normally performed by
internal comparator. As cycle starts, Low–Side switch (i.e.
M1 in Figure 1) is turned ON for a fixed ON time duration
(namely, Ton) unless current limit comparator senses coil
current has reached its preset limit. In the latter case, M1 is
OFF instantly . So Ton is defined as the maximum ON time
of M1. When M1 is ON, coil current ramps up, so energy is
being stored inside the coil. At the moment just after M1 is
OFF , the Synchronous Rectifier (i.e. M2 in Figure 1) or any
rectification device (such as Schottky Diode of Auxiliary
Regulator) is turned ON to direct coil current to charge up
the output bulk capacitor. Provided that coil current limit is
not reached, every switching cycle delivers fixed amount of
energy to the bulk capacitor. For higher loading, a larger
amount of energy (Charge) is withdrawn from the bulk
capacitor, and a larger amount of Char ge is then supplied to
the bulk capacitor to regulate output voltage. This implies
switching frequency is increased; and vice–versa.

Main Regulator

Figure 18 shows the simplified block diagram of Main
Regulator. Notice that precise bias current Iref is generated
by a VI converter and external resistor RIref, where

+

0.5

RIref

(A)

Iref

This bias current is used for all internal current bias as well
as setting VMAIN value. For the latter application, Iref is
doubled and fed as current sink at Pin 1. With external
resistor RMAINb tied from Pin1 to Pin32, a constant voltage
level shift is generated in between the two pins. In
close–loop operation, voltage at Pin 1 (i.e. Output feedback
voltage) is needed to be regulated at the internal reference
voltage level, 1.22V. Therefore, the delta voltage across Pin
1 and Pin 32 which can be adjusted by RMAINb determines
the Main Output voltage. If the feedback voltage drops
below 1.22V, internal comparator sets switching cycle to
start. So, VMAIN can be calculated as follows.

VMAIN

+

1.22

RMAINb

)

RIref

(V)

From the above equation, although VMAIN can be
adjusted by RMAINb and RIref ratio, for setting VMAIN, it
is suggested, by changing RMAINb value with RIref kept at
480K. Since changing RIref will alter internal bias current
which will affect timing functions of Max ON time (T
and Min OFF time (T

). Their relationships are as

OFF1

ON1

follows;

+

1

1

1.7 10

+

6.4 10

T

ON

T

OFF

Continuous Conduction Mode and Discontinuous
Conduction Mode

–11

–12

RIref

RIref

(S)

(S)

In Figure 19, regulator is operating at Continuous
Conduction Mode. A switching cycle is started as the output
feedback voltage drops below internal voltage reference
VREF . At that instant, the coil current is not yet zero, and it
starts to ramp up for the next cycle. As the coil current ramps
up, loading makes the output voltage to decrease as the
energy supply path to the output bulk capacitor is
disconnected. After Ton elapses, M1 is OFF, M2 is ON,
energy is pumped to the bulk capacitor. Output voltage is
increased as excessive charge is pumped in, then it is
decreased after the coil current drops below the loading.
Notice the abrupt spike of output voltage is due to ESR of the
bulk capacitor. Feedback voltage can be resistor–divided
down or level–shift down from the output voltage. As this
feedback voltage drops below VREF, next switching cycle
starts.

)

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9

Iref

IREF

RIref
480 kOhm

8

x2

Voltage

Reference

0.5 V

1.22 V

MC33680

DETAILED OPERATING DESCRIPTION (Cont’d)

CMAINb

100 pF

2 x Iref

VMAINFB

+ve Edge Delay

for Max. ON Time

VCOMP

COMP1

1–SHOT

for Min. OFF Time

RSQ

Qb

RMAINb

1000 kOhm

ZLC

V

DD

DGND

RSQ

COMP3

VBAT

311

L1
33uH

VMAINSW

M1

senseFET

V

DD

M2

VMAIN

32

CMAIN

100 uF

VMAINGND

30

+

AGND

Voltage Reference
& Current Bias

Main Regulator
with Synchronous Rectifier

Figure 18. Simplified Block Diagram of Main Regulator

In Figure 20, regulator is operating at Discontinuous

Conduction Mode, waveforms are similar to those of Figure

19. However, coil current drops to zero before next
switching cycle starts.

To estimate conduction mode, below equation can be

used.

Iroom

where,

if I

room

T

h

+

η

ON

2

L Vout

is efficiency, refer to Figure 4

> 0, the regulator is at Discontinuous Conduction

Vin

2

*

I

LOAD

mode

if I

= 0, the regulator is at Critical Conduction mode

room

where coil current just drops to zero and next cycle starts.

if I

< 0, the regulator is at Continuous Conduction

room

mode

COMP2

AGND

(S);

Vin T

2

DGND

ON

L

(A)

T

I

SW

pk

+

+

1*h

1

*

T

ON

I

LOAD

T

ǒ

T

ǒ

ON
SW

Vin

Vout

Ǔ

ILIM

Ǔ

)

For Discontinuous Conduction mode, provided that
current limit is not reached,

2

T

Vin

@

(A)

@

ON

ǒ

Vout

h

@

Vin

*

(S);

Ǔ

1

T

SW

I

pk

+

+

2

Vin

L

@L@

@

T

I

ON

LOAD

For Continuous Conduction mode, provided that current

limit is not reached,

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10

VREF

Cycle Start

Cycle Start

Feedback Voltage

MC33680

s

t

dl

Loading Current, I

Coil Current

VMAIN Zoom–In

LOAD

VMAIN

V@SW

Feedback Voltage

VREF

M1 ON

M2 OFF

I

pk

VMAIN + 1 V

M1 OFF

t

dh

M2 ON

0 V

M1 ON

M2 OFF

T

ON

T

SW

Figure 19. Waveforms of Continuous Conduction Mode

s

t

dl

M1 ON

M1 OFF M1 OFF M1 OFF

t

dh

M1 ON

M1 OFF

M2 ON

M1 ON

M2 OFF

M1 ON

M1 OFF

M2 ON

Loading Current, I

Coil Current

VMAIN Zoom–In

LOAD

VMAIN

V@SW

M2 OFF

I

pk

VMAIN + 1 V

0 V

M2 OFF

T

ON

V

IN

M2 OFF

T

SW

Figure 20. Waveforms of Discontinuous Conduction Mode

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11

MC33680

DETAILED OPERATING DESCRIPTION (Cont’d)

Synchronous Rectification

A Synchronous Rectifier is used in the main regulator to
enhance efficiency. Synchronous rectifier is normally
realized by powerFET with gate control circuitry which,
however, involved relative complicated timing concerns. In
Figure 19, as main switch M1 is being turned OFF, if the
synchronous switch M2 is just turned ON with M1 not being
completely turned OFF, current will be shunted from the
output bulk capacitor through M2 and M1 to ground. This
power loss lowers overall efficiency . So a certain amount of
dead time is introduced to make sure M1 is completely OFF
before M2 is being turned ON, this timing is indicated as t

dh

in Figure 20.

When the main regulator is operating in continuous mode,
as M2 is being turned OFF, and M1 is just turned ON with
M2 not being completed OFF , the above mentioned situation
will occur. So dead time is introduced to make sure M2 is
completed OFF before M1 is being turned ON, this is
indicated as tdl in Figure 20.

When the main regulator is operating in discontinuous
mode, as coil current is dropped to zero, M2 is supposed to
be OFF. Fail to do so, reverse current will flow from the
output bulk capacitor through M2 and then the inductor to
the battery input. It causes damage to the battery. So
M2–voltage–drop sensing comparator (COMP3 of Figure

18) comes with fixed offset voltage to switch M2 OFF
before any reverse current builds up. However, if M2 is
switch OFF too early, large residue coil current flows
through the body diode of M2 and increases conduction loss.

Therefore, determination on the offset voltage is essential
for optimum performance.

Auxiliary Regulator

The Auxiliary Regulator is a boost regulator, applies PFM
scheme to enhance high efficiency and reduce quiescent
current. An internal voltage comparator (COMP1 of Figure

21) detects when the voltage of Pin V AUXFBN drops below
that of Pin VAUXFBP. The internal power BJT is then
switched ON for a fixed–ON–time (or until the internal
current limit is reached), and coil current is allowed to build
up. As the BJT is switched OFF, coil current will flow
through the external Schottky diode to charge up the bulk
capacitor. After a fixed–mimimum–OFF time elapses, next
switching cycle will start if the output of the voltage
comparator is HIGH. Refer to Figure 21, the VAUX
regulation level is determined by the equation as follows,

R

AUXb
AUXa

Ǔ

(V)

V

AUX

+

VAUXFBP

@ǒ1

)

R

Where Max ON Time, TON2, and Min OFF T ime, TOFF2
can be determined by the following equations.

T

ON

T

OFF

+

2

2

1.7 10

+

2.1 10

–11

–12

RIref

RIref

(S)

(S)

As the Auxiliary Regulator control scheme is the same as
the Main Regulator, equations for conduction mode, Tsw
and Ipk can also be applied, However, h to be used for
calculation is referred to Figures 6, 8, or 10.

VBAT

RAUXa

VREF

Auxiliary Regulator

200 kOhm

VAUXFBN VAUXSWVAUXBDVVAUXFBP

2018

VCOMP

COMP1

Figure 21. Simplified Block Diagram of Auxiliary Regulator

RAUXb

2200 kOhm

+ve Edge Delay

for Max. ON Time

RSQ

1–SHOT

for Min. OFF Time

VBAT

Qb

ILIM

2521

Q1

COMP2

AGND

L2
33uH

senseBJT

+

CAUX
33 uF

VAUXEMR

26

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MC33680

Á

Á

Á

Á

Á

Á

DETAILED OPERATING DESCRIPTION (Cont’d)

Current Limit for Both regulators

From Figure 18 and Figure 21, sense devices (senseFET
or senseBJT) are applied to sample coil current as the
low–side switch is ON. With that sample current flowing
through a sense resistor, sense–voltage is developed.
Threshold detector (COMP2 in both Figures) detects
whether the sense–voltage is higher than preset level. If it
happens, detector output reset the flip–flop to switch OFF
low–side switch, and the switch can only be ON as next
cycle starts.

Power–Good Signal

During the startup period (see Figure 2), the internal
startup circuitry is enabled to pump up VMAIN to a certain
voltage level, which is the user–defined VMAIN output
level minus an offset of 0.15V. The internal Power–Good
signal is then enabled to activate the main regulator and
conditionally the auxiliary regulator . Meanwhile, the startup
circuitry will be shut down. The Power–Good signal block
also starts to charge up the external capacitor tied from Pin
PDELA Y to ground with precise constant current. As the Pin
PDELAY’s voltage reaches an internal set threshold, Pin
PORB will go HIGH to awake the microprocessor. This
delay is stated as follows;

1.22

ǒ

T

POR

+

0.5

Ǔ

C

RIref

por

(S)

From Figure 3, if, by any chance, VMAIN is dropped
below the user–defined VMAIN output level minus 0.5V,
PORB will go LOW to indicate the OUTPUT LOW
situation. And, the IC will continue to function until the
VMAIN is dropped below 2V.

Low–Battery–Detect

The Low–Battery–Detect block is actually a voltage
comparator. Pin LOWBAT is LOW , if the voltage of external
Pin LOWBA TSEN is lower than 0.85V. The IC will neglect
this warning signal. Pin LOWBA T will become HIGH, if the
voltage of external Pin LOWBA TSEN is recovered to more
than 1.1V. From Figure 1, with external resistors RLBa and
RLBb, thresholds of Low–Battery–Detect can be adjusted
based on the equations below .

R

LBa

V

LOBAThigh

V

LOBATlow

+

+

1.1

0.85

ǒ1

ǒ1

)

)

R

R
R

LBb

LBa
LBb

Ǔ

(V)

Ǔ

(V)

Lithium–Battery backup

The backup conduction path which is provided by an
internal power switch (typ. 13 Ohm) can be controlled by
internal logic or microprocessor.

If LIBA TCL is LOW, the switch, which is then controlled
by internal logic, is ON when the battery is removed and
VMAIN is dropped below LIBATIN by more than 100mV,
and returns OFF when the battery is plugged back in.

If LIBATCL is HIGH, the switch is controlled by
microprocessor through LIBA TON. The truth table is shown
in Figure 22.

Efficiency and Output Ripple

For both regulators, when large values are used for
feedback resistors (> 50kOhm), stray capacitance of pin 1
(VMAINFB) and pin 20 (VAUXFBN) can add ”lag” to the
feedback response, destabilizing the regulator and creating
a larger ripple at the output. From Figure 1, ripple of Main
and AUX regulator can be reduced by capacitors in parallel
with RMAINb, RAUXa and RAUXb ranging from 100pF to
100nF respectively. Reducing the ripple is also with
improving efficiency , system designers are recommended to
do experiments on capacitance values based on the PCB
design.

Bypass Capacitors

If the metal lead from battery to coils are long, its stray
resistance can put additional power loss to the system as AC
current is being conducted. In that case, bypass capacitors
should be placed closely to the coil, and connected from
V

to ground. This reduces AC component of coil current

BAT

passing through the long metal lead, thus minimizing that
portion of power loss.

LIBATCL LIBATON Action

0

1
1

БББББ

БББББ

X

ÁÁÁÁ

ÁÁÁÁ

0
1

Figure 22. Lithium Battery Backup Control Truth Table

The switch is ON when the battery is removed and VMAIN is dropped below LIBATIN by

ББББББББББББББББББББ

more than 100mV;
The switch is OFF when the battery is plugged in.

ББББББББББББББББББББ

The switch is OFF
The switch is ON

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13

SEATING

PLANE

9

C

–T–

B1

–AB–
–AC–

E

MC33680

P ACKAGE DIMENSIONS

32–LEAD LQFP

PLASTIC PACKAGE

CASE 873A–02

A

A1

32

1

4X

25

T–U0.20 (0.008) ZAB

BASE

METAL

N

–U–

ISSUE A

VB

DETAIL Y

8

9

–Z–

S1

V1

17

4X

T–U0.20 (0.008) Z

AC

SECTION AE–AE

DF

J

S

G

DETAIL AD

0.10 (0.004) AC

AE

_

8X

M

R

P

AE

DETAIL Y

H

W

_

Q

K

X

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –AB– IS LOCATED AT BOTTOM

T–U

M

0.20 (0.008) ZAC

OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.

4. DATUMS –T–, –U–, AND –Z– TO BE
DETERMINED AT DATUM PLANE –AB–.

5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.

6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.

7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED

0.520 (0.020).

8. MINIMUM SOLDER PLATE THICKNESS SHALL
BE 0.0076 (0.0003).

9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.

–T–, –U–, –Z–

MILLIMETERS

DIMAMIN MAX MIN MAX

7.000 BSC 0.276 BSC

A1 3.500 BSC 0.138 BSC

B 7.000 BSC 0.276 BSC

B1 3.500 BSC 0.138 BSC

C 1.400 1.600 0.055 0.063
D 0.300 0.450 0.012 0.018
E 1.350 1.450 0.053 0.057
F 0.300 0.400 0.012 0.016
G 0.800 BSC 0.031 BSC
H 0.050 0.150 0.002 0.006
J 0.090 0.200 0.004 0.008
K 0.500 0.700 0.020 0.028

__

M 12 REF 12 REF
N 0.090 0.160 0.004 0.006
P 0.400 BSC 0.016 BSC
Q 1 5 1 5

____

R 0.150 0.250 0.006 0.010
S 9.000 BSC 0.354 BSC

S1 4.500 BSC 0.177 BSC

V 9.000 BSC 0.354 BSC

V1 4.500 BSC 0.177 BSC

W 0.200 REF 0.008 REF
X 1.000 REF 0.039 REF

INCHES

DETAIL AD

0.250 (0.010)

GAUGE PLANE

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Notes

MC33680

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15

MC33680

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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MC33680/D