Datasheet MC34151D, MC34151DR2, MC34151P, MC33151D, MC33151DR2 Datasheet (MOTOROLA)

MC34151, MC33151

High Speed Dual
MOSFET Drivers

The MC34151/MC33151 are dual inverting high speed drivers
specifically designed for applications that require low current digital
circuitry to drive large capacitive loads with high slew rates. These
devices feature low input current making them CMOS and LSTTL
logic compatible, input hysteresis for fast output switching that is
independent of input transition time, and two high current totem pole
outputs ideally suited for driving power MOSFETs. Also included is
an undervoltage lockout with hysteresis to prevent erratic system
operation at low supply voltages.

Typical applications include switching power supplies, dc to dc
converters, capacitor charge pump voltage doublers/inverters, and
motor controllers.

These devices are available in dual–in–line and surface mount
packages.

• T wo Independent Channels with 1.5 A Totem Pole Output

• Output Rise and Fall Times of 15 ns with 1000 pF Load

• CMOS/LSTTL Compatible Inputs with Hysteresis

• Undervoltage Lockout with Hysteresis

• Low Standby Current

• Efficient High Frequency Operation

• Enhanced System Performance with Common Switching Regulator

Control ICs

• Pin Out Equivalent to DS0026 and MMH0026

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MARKING

DIAGRAMS

8

PDIP–8

P SUFFIX

8

1

8

1

x = 3 or 4
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W= Work Week

CASE 626

SO–8
D SUFFIX
CASE 751

MC3x151P

AWL

YYWW

1

8

3x151
ALYW

1

PIN CONNECTIONS

Logic Input A

Logic Input B

Representative Block Diagram

V

CC

6

+

+

–

+

+

2

+

4

5.7V

Gnd

3

1

Logic Input A

Logic Input B

+

Drive Output A
7

100k

+

Drive Output B
5

100k

Device Package Shipping

MC34151D SO–8 98 Units/Rail
MC34151DR2 SO–8 2500 Tape & Reel
MC34151P PDIP–8
MC33151D SO–8
MC33151DR2 SO–8 2500 Tape & Reel
MC33151P PDIP–8 50 Units/Rail
MC33151VDR2 SO–8 2500 Units/Rail

2

3

Gnd

45

(Top View)

ORDERING INFORMATION

8N.C.

N.C.

7

Drive Output A

6

V

CC

Drive Output B

50 Units/Rail
98 Units/Rail

 Semiconductor Components Industries, LLC, 2000

April, 2000 – Rev. 1

1 Publication Order Number:

MC34151/D

MC34151, MC33151

MAXIMUM RATINGS

Rating Symbol Value Unit

Power Supply Voltage V
Logic Inputs (Note 1.) V
Drive Outputs (Note 2.)

Totem Pole Sink or Source Current
Diode Clamp Current (Drive Output to VCC)

Power Dissipation and Thermal Characteristics

D Suffix SO–8 Package Case 751

Maximum Power Dissipation @ TA = 50°C
Thermal Resistance, Junction–to–Air

P Suffix 8–Pin Package Case 626

Maximum Power Dissipation @ TA = 50°C

Thermal Resistance, Junction–to–Air
Operating Junction Temperature T
Operating Ambient Temperature

MC34151
MC33151

Storage Temperature Range T

I

CC

in

I

O

O(clamp)

P

D

R

θJA

P

D

R

θJA

J

T

A

stg

20 V

–0.3 to V

–65 to +150 °C

CC

1.5

1.0

0.56
180

1.0

100

+150 °C

0 to +70

–40 to +85

°C/W

°C/W

°C

V
A

W

W

ELECTRICAL CHARACTERISTICS (V

Characteristics

LOGIC INPUTS

Input Threshold Voltage – High State Logic 1

Input Threshold Voltage – Low State Logic 0

Input Current – High State (VIH = 2.6 V)

Input Current – Low State (VIL = 0.8 V)

DRIVE OUTPUT

Output Voltage – Low State (I

Output Voltage – Low State (I
Output Voltage – Low State (I
Output Voltage – High State (I
Output Voltage – High State (I
Output Voltage – High State (I

Output Pull–Down Resistor R

SWITCHING CHARACTERISTICS (TA = 25°C)

Propagation Delay (10% Input to 10% Output, CL = 1.0 nF)

Logic Input to Drive Output Rise
Logic Input to Drive Output Fall

Drive Output Rise Time (10% to 90%) CL = 1.0 nF

Drive Output Rise Time (10% to 90%) CL = 2.5 nF

Drive Output Fall Time (90% to 10%) CL = 1.0 nF

Drive Output Fall Time (90% to 10%) CL = 2.5 nF

TOTAL DEVICE

Power Supply Current

Standby (Logic Inputs Grounded)
Operating (CL = 1.0 nF Drive Outputs 1 and 2, f = 100 kHz)

Operating Voltage V

1. For optimum switching speed, the maximum input voltage should be limited to 10 V or VCC, whichever is less.

2. Maximum package power dissipation limits must be observed.

3. T

=0°C for MC34151 T

low

–40°C for MC33151 +85°C for MC33151

= 10 mA)

Sink

= 50 mA)

Sink

= 400 mA)

Sink
Source
Source
Source

= 10 mA)
= 50 mA)
= 400 mA)

= 12 V, for typical values TA = 25°C, for min/max values TA is the only operating

CC

ambient temperature range that applies [Note 3.], unless otherwise noted.)

Symbol Min Typ Max Unit

= +70°C for MC34151

high

V

IH

V

IL

I

IH

I

IL

V

OL

V

OH

PD

t

PLH(in/out)

t

PHL(in/out)

t

r

t

f

I

CC

CC

2.6
–

–
–

–
–
–

10.5

10.4

9.5
– 100 – kΩ

–
–

–
–

–
–

–
–

6.5 – 18 V

1.75

1.58
200

20

0.8

1.1

1.7

11.2

11.1

10.9

35
36

14
31

16
32

6.0

10.5

–

0.8

500
100

1.2

1.5

2.5
–
–
–

100
100

30

–

30

–

10
15

V

µA

V

ns

ns

ns

mA

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2

12

V

4.7 0.1
+

6

MC34151, MC33151

Logic Input

2.4

2.0

1.6

1.2

+

2

50 C

+

4

+

+

–

+

5.7V

3

+

Drive Output

7

100k

+

5

100k

L

Logic Input

tr, tf ≤ 10 ns

Drive Output

5.0 V

0 V

10%

t

PHL

t

f

90%

90%

t

PLH

10%

t

Figure 1. Switching Characteristics T est Circuit Figure 2. Switching Waveform Definitions

2.2

VCC = 12 V
TA = 25°C

2.0

1.8

1.6

Upper Threshold

Low State Output

VCC = 12 V

r

0.8

, INPUT CURRENT (mA)

in

I

0.4

0

0 2.0 4.0 6.0 8.0 10 12 –55 –25 0 25 50 75 100 125

Vin, INPUT VOLTAGE (V)

Figure 3. Logic Input Current versus

Input Voltage

200

VCC = 12 V
CL = 1.0 nF

160

TA = 25°C

120

80

40

, DRIVE OUTPUT PROPAGATION DELA Y (ns)

0

–1.6 –1.2 –0.8 –0.4 0 0 1.0 2.0 3.0 4.0

Vin, INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V)

PLH(IN/OUT)

t

Overdrive Voltage is with Respect

to the Logic Input Lower Threshold

V

th(lower)

Figure 5. Drive Output Low–to–High Propagation

Delay versus Logic Overdrive V oltage

1.4

, INPUT THRESHOLD VOLTAGE (V)

1.2

th

V

1.0

Lower Threshold

High State Output

TA, AMBIENT TEMPERATURE (°C)

Figure 4. Logic Input Threshold V oltage

versus T emperature

200

160

120

80

40

, DRIVE OUTPUT PROPAGATION DELA Y (ns)

0

Vin, INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V)

PHL(IN/OUT)

t

Overdrive Voltage is with Respect

to the Logic Input Lower Threshold

V

th(upper)

VCC = 12 V
CL = 1.0 nF
TA = 25°C

Figure 6. Drive Output High–to–Low Propagation

Delay versus Logic Input Overdrive V oltage

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3

MC34151, MC33151

V

,

T

T

T

T

N

V

LT

G

(V)

90%

10%

Logic Input

Drive Output

50 ns/DIV

VCC = 12 V
Vin = 5 V to 0 V
CL = 1.0 nF
TA = 25°C

Figure 7. Propagation Delay Figure 8. Drive Output Clamp Voltage

0
E
A

–1.0

O

–2.0

IO

–3.0

URA

3.0

SA
PU

2.0

OU

1.0

sat

0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

IO, OUTPUT LOAD CURRENT (A)

V

CC

Sink Saturation

(Load to VCC)

Source Saturation

(Load to Ground)

VCC = 12 V
80 µs Pulsed Load
120 Hz Rate
TA = 25°C

Gnd

Figure 9. Drive Output Saturation Voltage

versus Load Current

90%

3.0

2.0

1.0

0

, OUTPUT CLAMP VOLTAGE (V)

0

clamp

V

–1.0

High State Clamp

(Drive Output Driven Above VCC)

V

CC

Gnd

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

IO, OUTPUT LOAD CURRENT (A)

(Drive Output Driven Below Ground)

VCC = 12 V
80 µs Pulsed Load
120 Hz Rate
TA = 25°C

Low State Clamp

versus Clamp Current

0

Source Saturation

–0.5

(Load to Ground)

–0.7
–0.9
–1.1

1.9

1.7

1.5

1.0

, OUTPUT SATURATION VOLTAGE(V)

0.8

sat

V

Sink Saturation

0.6

(Load to VCC)

0

–55 –25 0 25 50 75 100 125

V

CC

TA, AMBIENT TEMPERATURE (°C)

I

sink

I

sink

Gnd

I

source

I

source

= 400 mA

= 10 mA

= 10 mA
= 400 mA

VCC = 12 V

Figure 10. Drive Output Saturation Voltage

versus T emperature

90%

VCC = 12 V
Vin = 5 V to 0 V
CL = 1.0 nF
TA = 25°C

10%

VCC = 12 V
Vin = 5 V to 0 V
CL = 1.0 nF
TA = 25°C

10 ns/DIV

10%

10 ns/DIV

Figure 11. Drive Output Rise Time Figure 12. Drive Output Fall Time

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4

MC34151, MC33151

80

80

VCC = 12 V
VIN = 0 V to 5.0 V

60

TA = 25°C

40

t

20

f

–t , OUTPUT RISE-FALL TIME(ns)

r

t

0

0.1 1.0 10 0.1 1.0 10
CL, OUTPUT LOAD CAPACITANCE (nF)

f

t

r

Figure 13. Drive Output Rise and Fall Time

versus Load Capacitance

80

Both Logic Inputs Driven
0 V to 5.0 V,
50% Duty Cycle

60

Both Drive Outputs Loaded
TA = 25°C

1 – VCC = 18 V, CL = 2.5 nF

40

2 – VCC = 12 V, CL = 2.5 nF
3 – VCC = 18 V, CL = 1.0 nF
4 – VCC = 12 V, CL = 1.0 nF

, SUPPLY CURRENT (mA)

20

CC

I

1

2

3

4

VCC = 12 V
Both Logic Inputs Driven
0 V to 5.0 V

60

50% Duty Cycle
Both Drive Outputs Loaded
TA = 25°C

40

, SUPPLY CURRENT (mA)

20

CC

I

0

f = 500 kHz

CL, OUTPUT LOAD CAPACITANCE (nF)

f = 200 kHz

f = 50 kHz

Figure 14. Supply Current versus Drive Output

Load Capacitance

8.0
TA = 25°C

6.0

4.0

, SUPPLY CURRENT (mA)

2.0

CC

I

Logic Inputs at V

Low State Drive Outputs

CC

Logic Inputs Grounded

High State Drive Outputs

0

10 k

f, INPUT FREQUENCY (Hz)

Figure 15. Supply Current versus Input Frequency Figure 16. Supply Current versus Supply Voltage

100 1.0 M

0

0 4.0 8.0 12 16

VCC, SUPPLY VOLTAGE (V)

APPLICATIONS INFORMATION

Description

The MC34151 is a dual inverting high speed driver
specifically designed to interface low current digital
circuitry with power MOSFET s. This device is constructed
with Schottky clamped Bipolar Analog technology which
offers a high degree of performance and ruggedness in
hostile industrial environments.

Output Stage

Each totem pole Drive Output is capable of sourcing and

sinking up to 1.5 A with a typical ‘on’ resistance of 2.4 Ω at

1.0 A. The low ‘on’ resistance allows high output currents
to be attained at a lower VCC than with comparative CMOS
drivers. Each output has a 100 kΩ pull–down resistor to keep
the MOSFET gate low when VCC is less than 1.4 V . No over
current or thermal protection has been designed into the

Input Stage

The Logic Inputs have 170 mV of hysteresis with the input
threshold centered at 1.67 V. The input thresholds are
insensitive to VCC making this device directly compatible
with CMOS and LSTTL logic families over its entire
operating voltage range. Input hysteresis provides fast
output switching that is independent of the input signal
transition time, preventing output oscillations as the input
thresholds are crossed. The inputs are designed to accept a
signal amplitude ranging from ground to VCC. This allows
the output of one channel to directly drive the input of a
second channel for master–slave operation. Each input has
a 30 kΩ pull–down resistor so that an unconnected open
input will cause the associated Drive Output to be in a known
high state.

device, so output shorting to VCC or ground must be
avoided.

Parasitic inductance in series with the load will cause the
driver outputs to ring above VCC during the turn–on
transition, and below ground during the turn–off transition.
With CMOS drivers, this mode of operation can cause a
destructive output latch–up condition. The MC34151 is
immune to output latch–up. The Drive Outputs contain an
internal diode to VCC for clamping positive voltage
transients. When operating with VCC at 18 V, proper power
supply bypassing must be observed to prevent the output
ringing from exceeding the maximum 20 V device rating.
Negative output transients are clamped by the internal NPN
pull–up transistor. Since full supply voltage is applied across

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5

MC34151, MC33151

16

the NPN pull–up during the negative output transient, power
dissipation at high frequencies can become excessive.
Figures 19, 20, and 21 show a method of using external
Schottky diode clamps to reduce driver power dissipation.

gate charge information on their data sheets. Figure 17
shows a curve of gate voltage versus gate charge for the ON
Semiconductor MTM15N50. Note that there are three
distinct slopes to the curve representing different input
capacitance values. To completely switch the MOSFET

Undervoltage Lockout

An undervoltage lockout with hysteresis prevents erratic
system operation at low supply voltages. The UVLO forces
the Drive Outputs into a low state as VCC rises from 1.4 V
to the 5.8 V upper threshold. The lower UVLO threshold is

‘on’, the gate must be brought to 10 V with respect to the
source. The graph shows that a gate charge Qg of 110 nC is
required when operating the MOSFET with a drain to source
voltage VDS of 400 V.

5.3 V, yielding about 500 mV of hysteresis.

12

MTM15N50
ID = 15 A
TA = 25°C

VDS = 100 V

VDS = 400 V

Power Dissipation

Circuit performance and long term reliability are
enhanced with reduced die temperature. Die temperature
increase is directly related to the power that the integrated
circuit must dissipate and the total thermal resistance from
the junction to ambient. The formula for calculating the

8.0

8.9 nF

junction temperature with the package in free air is:

TJ =TA + PD (R

θJA

)

where: TJ = Junction Temperature

TA = Ambient Temperature

PD = Power Dissipation

R

Thermal Resistance Junction to Ambient

θJA =

There are three basic components that make up total
power to be dissipated when driving a capacitive load with

4.0

, GATE–TO–SOURCE VOLTAGE (V)
V

GS

2.0 nF

0

0 40 80 120 160

Qg, GATE CHARGE (nC)

Figure 17. Gate–T o–Source Voltage

versus Gate Charge

CGS =

∆ V

∆ Q

g

GS

respect to ground. They are:

PD =PQ + PC + P

T

where: PQ = Quiescent Power Dissipation

PC = Capacitive Load Power Dissipation
PT = Transition Power Dissipation

The quiescent power supply current depends on the
supply voltage and duty cycle as shown in Figure 16. The
device’s quiescent power dissipation is:

PQ = VCC I

CCL

(1–D) + I

CCH

(D)

The capacitive load power dissipation is directly related to
the required gate charge, and operating frequency. The
capacitive load power dissipation per driver is:

P

C(MOSFET)

= VC Qg f

The flat region from 10 nC to 55 nC is caused by the
drain–to–gate Miller capacitance, occurring while the
MOSFET is in the linear region dissipating substantial
amounts of power . The high output current capability of the
MC34151 is able to quickly deliver the required gate charge
for fast power efficient MOSFET switching. By operating

where: I

The capacitive load power dissipation is directly related
to the load capacitance value, frequency, and Drive Output
voltage swing. The capacitive load power dissipation per
driver is:

where: VOH = High State Drive Output Voltage

When driving a MOSFET, the calculation of capacitive
load power PC is somewhat complicated by the changing
gate to source capacitance CGS as the device switches. T o aid

= Supply Current with Low State Drive

CCL

Outputs

I

= Supply Current with High State Drive

CCH

Outputs

D = Output Duty Cycle

PC =VCC (VOH – VOL) CL f

VOL = Low State Drive Output Voltage

CL = Load Capacitance

f = frequency

the MC34151 at a higher VCC, additional charge can be
provided to bring the gate above 10 V. This will reduce the
‘on’ resistance of the MOSFET at the expense of higher
driver dissipation at a given operating frequency.

The transition power dissipation is due to extremely short
simultaneous conduction of internal circuit nodes when the
Drive Outputs change state. The transition power
dissipation per driver is approximately:

PT 9 VCC (1.08 VCC CL f – 8 y 10–4)
PT must be greater than zero.

Switching time characterization of the MC34151 is
performed with fixed capacitive loads. Figure 13 shows that
for small capacitance loads, the switching speed is limited
by transistor turn–on/off time and the slew rate of the
internal nodes. For large capacitance loads, the switching
speed is limited by the maximum output current capability
of the integrated circuit.

in this calculation, power MOSFET manufacturers provide

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MC34151, MC33151

LAYOUT CONSIDERATIONS

High frequency printed circuit layout techniques are

imperative to prevent excessive output ringing and overshoot.

Do not attempt to construct the driver circuit on
wire–wrap or plug–in prototype boards. When driving

large capacitive loads, the printed circuit board must contain
a low inductance ground plane to minimize the voltage spikes
induced by the high ground ripple currents. All high current
loops should be kept as short as possible using heavy copper
runs to provide a low impedance high frequency path. For

V

CC

0.1

47

6

TL494

or

TL594

+

++

–

+

5.7V

+

2

100k100k

+

+

4

V

in

7

5

optimum drive performance, it is recommended that the
initial circuit design contains dual power supply bypass
capacitors connected with short leads as close to the VCC pin
and ground as the layout will permit. Suggested capacitors are
a low inductance 0.1 µF ceramic in parallel with a 4.7 µF
tantalum. Additional bypass capacitors may be required
depending upon Drive Output loading and circuit layout.

Proper printed circuit board layout is extremely
critical and cannot be over emphasized.

V

in

+

R

g

D

100k

1

1N5819

3

The MC34151 greatly enhances the drive capabilities of common switching
regulators and CMOS/TTL logic devices.

Figure 18. Enhanced System Performance with

Common Switching Regulators

+

+

7

100k100k

+

3

4 X

1N5819

+

5

Series gate resistor Rg may be needed to damp high frequency parasitic
oscillations caused by the MOSFET input capacitance and any series
wiring inductance in the gate–source circuit. Rg will decrease the
MOSFET switching speed. Schottky diode D1 can reduce the driver’s
power dissipation due to excessive ringing, by preventing the output pin
from being driven below ground.

Figure 19. MOSFET Parasitic Oscillations

+

100k

3

Isolation

Boundary

1N

5819

Output Schottky diodes are recommended when driving inductive loads at
high frequencies. The diodes reduce the driver’s power dissipation by
preventing the output pins from being driven above VCC and below ground.

Figure 20. Direct Transformer Drive Figure 21. Isolated MOSFET Drive

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7

MC34151, MC33151

V

I

in

+

R

R

g(on)

g(off)

100k

B

+
0

–

+

Base Charge

Removal

100k

V

in

C

1

In noise sensitive applications, both conducted and radiated EMI can
be reduced significantly by controlling the MOSFET’s turn–on and
turn–off times.

The totem–pole outputs can furnish negative base current for enhanced
transistor turn–off, with the addition of capacitor C1.

Figure 22. Controlled MOSFET Drive Figure 23. Bipolar Transistor Drive

VCC = 15 V

4.7 0.1
+

6

+

+

330pF

–

+

5.7V

+

2

+

4

+

6.8 10

7

100k

+

6.8 10

5

100k

+

1N5819

+

47

1N5819

47

+

+

+ VO ≈ 2.0 V

– VO ≈ – V

CC

CC

10k

3

The capacitor’s equivalent series resistance limits the Drive Output Current
to 1.5 A. An additional series resistor may be required when using tantalum or
other low ESR capacitors.

Figure 24. Dual Charge Pump Converter

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8

Output Load Regulation

IO (mA) +VO (V) –VO (V)

0 27.7 –13.3

1.0 27.4 –12.9
10 26.4 –11.9
20 25.5 –11.2
30 24.6 –10.5
50 22.6 –9.4

NOTE 2

–T–

SEATING
PLANE

H

58

–B–

14

F

–A–

C

N

D

G

0.13 (0.005) B

MC34151, MC33151

P ACKAGE DIMENSIONS

PDIP–8

P SUFFIX

CASE 626–05

ISSUE K

L

J

K

M

A

T

M

M

M

NOTES:

1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).

3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

DIM MIN MAX MIN MAX

A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
F 1.02 1.78 0.040 0.070
G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050

J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M ––– 10 ––– 10
N 0.76 1.01 0.030 0.040

INCHESMILLIMETERS

__

C

A

A1

SO–8

D SUFFIX

CASE 751–06

ISSUE T

D

58

0.25MB

E

1

B

e

H

4

M

h

X 45

_

q

C

A

SEATING
PLANE

0.10

L

B

SS

A0.25MCB

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.

2. DIMENSIONS ARE IN MILLIMETER.

3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.

MILLIMETERS

DIM MIN MAX

A 1.35 1.75

A1 0.10 0.25

B 0.35 0.49
C 0.19 0.25
D 4.80 5.00
E

3.80 4.00

1.27 BSCe

H 5.80 6.20
h

0.25 0.50

L 0.40 1.25

0 7

q

__

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Notes

MC34151, MC33151

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Notes

MC34151, MC33151

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11

MC34151, MC33151

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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA

Phone: [phone] or 800–344–3860 Toll Free USA/Canada
Fax: [phone] or 800–344–3867 Toll Free USA/Canada
Email: [e-mail]

Fax Response Line: 303–675–2167 or 800–344–3810 T oll Free USA/Canada

N. American Technical Support: 800–282–9855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor – European Support

German Phone: [phone] (M–F 1:00pm to 5:00pm Munich Time)

Email: ONlit–[e-mail]

French Phone: [phone] (M–F 1:00pm to 5:00pm Toulouse T ime)

Email: ONlit–[e-mail]

English Phone: [phone] (M–F 12:00pm to 5:00pm UK Time)

Email: [e-mail]

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

*Available from Germany, France, Italy, England, Ireland

CENTRAL/SOUTH AMERICA:

Spanish Phone: [phone] (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–[e-mail]

ASIA/PACIFIC : LDC for ON Semiconductor – Asia Support

Phone: [phone] (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

T oll Free from Hong Kong & Singapore:

001–800–4422–3781

Email: ONlit–[e-mail]

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, T okyo, Japan 141–8549

Phone: [phone]
Email: [e-mail]

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

http://onsemi.com

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