Datasheet MC28F008, MF28F008 Datasheet (Intel Corporation)

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

November 1994COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 271232-004

M28F008

8 MBIT (1 MBIT x 8) FLASH MEMORY

Y

High-Density Symmetrically Blocked
Architecture
Ð Sixteen 64 Kbyte Blocks

Y

Extended Cycling Capability
Ð 10K Block Erase Cycles Minimum
Ð 160K Block Erase Cycles per Chip

Y

Automated Byte Write and Block Erase
Ð Command User Interface
Ð Status Register

Y

System Performance Enhancements
Ð RY/BY

Status Output

Ð Erase Suspend Capability

Y

SRAM-Compatible Write Interface

Y

Very High-Performance Read
Ð 100 ns Maximum Access Time

Y

Hardware Data Protection Feature
Ð Erase/Write Lockout during Power

Transitions

Y

Industry Standard Packaging
Ð 40-Lead Sidebrazed DIP
Ð 42-Lead Flatpack

Y

ETOXTMNonvolatile Flash Technology
Ð 12V Byte Write/Block Erase

Y

Independent Software Vendor Support
Ð Microsoft* Flash File System (FFS)

Intel’s M28F008 8-Mbit FlashFile Memory is the highest density nonvolatile read/write solution for solid state
storage. The M28F008’s extended cycling, symmetrically blocked architecture, fast access time, write automa­tion and low power consumption provide a more reliable, lower power, lighter weight and higher performance
alternative to traditional rotating disk technology. The M28F008 brings new capabilities to portable computing.
Application and operating system software stored in resident flash memory arrays provide instant-on, rapid
execute-in-place and protection from obsolescence through in-system software updates. Resident software
also extends system battery life and increases reliability by reducing disk drive accesses.

For high-density data acquisition applications, the M28F008 offers a more cost-effective and reliable alterna­tive to SRAM and battery. Traditional high density embedded applications, such as telecommunications, can
take advantage of the M28F008’s nonvolatility, blocking and minimal system code requirements for flexible
firmware and modular software designs.

The M28F008 is offered in 40-lead sidebrazed DIP and 42-lead Flatpack packages. This device uses an
integrated Command User Interface and state machine for simplified block erasure and byte write. The
M28F008 memory map consists of 16 separately erasable 64 Kbyte blocks.

Intel’s M28F008 employs advanced CMOS circuitry for systems requiring low power consumption and noise
immunity. Its 100 ns access time provides superior performance when compared with magnetic storage media.
A deep powerdown mode lowers power consumption to 500 mW maximum thru V

CC

. The RP power control

input also provides absolute data protection during system powerup/down.

Manufactured on Intel’s ETOX process technology, the M28F008 provides the highest levels of quality, reliabil­ity and cost-effectiveness.

*Microsoft is a trademark of Microsoft Corporation.

M28F008

PRODUCT OVERVIEW

The M28F008 is a high-performance 8 Mbit
(8,388,608 bit) memory organized as 1 Mbyte
(1,048,576 bytes) of 8 bits each. Sixteen 64 Kbyte
(65,536 byte) blocks are included on the M28F008.
A memory map is shown in Figure 4 of this specifica­tion. A block erase operation erases one of the six­teen blocks of memory in typically 1.6 seconds, in­dependent of the remaining blocks. Each block can
be independently erased and written 10,000 cycles.
Erase Suspend mode allows system software to
suspend block erase to read data or execute code
from any other block of the M28F008.

The M28F008 is available in 40-lead sidebrazed
DIP and 42-lead Flatpack packages. Pinouts are
shown in Figures 2a and 2b of this specification.

The Command User Interface serves as the inter­face between the microprocessor or microcontroller
and the internal operation of the M28F008.

Byte Write and Block Erase Automation allow
byte write and block erase operations to be execut­ed using a two-write command sequence to the
Command User Interface. The internal Write State
Machine (WSM) automatically executes the algo­rithms and timings necessary for byte write and
block erase operations, including verifications,
thereby unburdening the microprocessor or micro­controller. Writing of memory data is performed in
byte increments typically within 9 ms, an 80% im­provement over current flash memory products. I

PP

byte write and block erase currents are 30 mA
maximum. V

PP

byte write and block erase volt-

age is 11.4V to 12.6V.

The Status Register indicates the status of the
WSM and when the WSM successfully completes
the desired byte write or block erase operation.

The RY/BY

output gives an additional indicator of
WSM activity, providing capability for both hardware
signal of status (versus software polling) and status
masking (interrupt masking for background erase,
for example). Status polling using RY/BY minimizes
both CPU overhead and system power consump­tion. When low, RY/BY

indicates that the WSM is
performing a block erase or byte write operation.
RY/BY

high indicates that the WSM is ready for new
commands, block erase is suspended or the device
is in deep powerdown mode.

Maximum access time is 100 ns (t

ACC

) over the mili-

tary temperature range (

b

55§Ctoa125§C) and

over V

CC

supply voltage range 4.5V to 5.5V. ICCac-

tive current (CMOS Read) is 35 mA maximum at
8 MHz.

When the CE

and RP pins are at VCC, the ICCCMOS

Standby mode is enabled.

A Deep Powerdown mode is enabled when the RP
pin is at GND, minimizing power consumption and
providing write protection. I

CC

current in deep pow-

erdown is 100 mA maximum. Reset time of 400 ns
is required from RP

switching high until outputs are
valid to read attempts. Equivalently, the device has a
wake time of 1 m s from RP

high until writes to the
Command User Interface are recognized by the
M28F008. With RP

at GND, the WSM is reset and

the Status Register is cleared.

2

M28F008

271232– 1

Figure 1. Block Diagram

Table 1. Pin Description

Symbol Type Name and Function

A0–A

19

INPUT ADDRESS INPUTS for memory addresses. Addresses are internally

latched during a write cycle.

DQ0–DQ7INPUT/OUTPUT DATA INPUT/OUTPUTS: Inputs data and commands during Command

User Interface write cycles; outputs data during memory array, Status
Register and Identifier read cycles. The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled. Data is internally latched during a write cycle.

CE INPUT CHIP ENABLE: Activates the device’s control logic, input buffers,

decoders, and sense amplifiers. CE

is active low; CE high deselects the

memory device and reduces power consumption to standby levels.

RP INPUT RESET/DEEP POWERDOWN: Puts the device in deep powerdown

mode. RP

is active low; RP high gates normal operation. RP also locks
out block erase or byte write operations when active low, providing data
protection during power transitions. RP

active resets internal

automation. Exit from Deep Powerdown sets device to read-array mode.

OE INPUT OUTPUT ENABLE: Gates the device’s outputs through the data buffers

during a read cycle. OE

is active low.

WE INPUT WRITE ENABLE: Controls writes to the Command User Interface and

array blocks. WE

is active low. Addresses and data are latched on the

rising edge of the WE pulse.

3

M28F008

Table 1. Pin Description (Continued)

Symbol Type Name and Function

RY/BY OUTPUT READY/BUSY: Indicates the status of the internal Write State Machine. When

low, it indicates that the WSM is performing a block erase or byte write operation.
RY/BY

high indicates that the WSM is ready for new commands, block erase is

suspended or the device is in deep powerdown mode. RY/BY

is always active and
does NOT float to tri-state off when the chip is deselected or data outputs are
disabled.

V

PP

BLOCK ERASE/BYTE WRITE POWER SUPPLY for erasing blocks of the array
or writing bytes of each block.

NOTE:

With V

PP

k

V

PPLMAX

, memory contents cannot be altered.

V

CC

DEVICE POWER SUPPLY (5Vg10%)

GND GROUND

271232– 2

Figure 2a. DIP Pinout

271232– 14

Figure 2b. Flatpack Pinout

4

M28F008

271232– 3

Figure 3. M28F008 Array Interface to Intel386TMSL Microprocessor Superset through PI Bus

(Including RY/BY

Masking and Selective Powerdown), for DRAM Backup during System SUSPEND,

Resident O/S and Applications and Motherboard Solid-State Disk.

PRINCIPLES OF OPERATION

The M28F008 includes on-chip write automation to
manage write and erase functions. The Write State
Machine allows for: 100% TTL-level control inputs,
fixed power supplies during block erasure and byte
write, and minimal processor overhead with RAM­like interface timings.

After initial device powerup, or after return from
deep powerdown mode (see Bus Operations), the
M28F008 functions as a read-only memory. Manipu­lation of external memory-control pins allow array
read, standby and output disable operations. Both
Status Register and intelligent identifier can

also be accessed through the Command User Inter­face when V

PP

e

V

PPL

.

This same subset of operations is also available
when high voltage is applied to the V

PP

pin. In addi-

tion, high voltage on V

PP

enables successful block
erasure and byte writing of the device. All functions
associated with altering memory contentsÐbyte
write, block erase, status and intelligent identifierÐ
are accessed via the Command User Interface and
verified thru the Status Register.

Commands are written using standard microproces­sor write timings. Command User Interface contents
serve as input to the WSM, which controls the block

5

M28F008

erase and byte write circuitry. Write cycles also inter­nally latch addresses and data needed for byte write
or block erase operations. With the appropriate com­mand written to the register, standard microproces­sor read timings output array data, access the intelli­gent identifier codes, or output byte write and block
erase status for verification.

Interface software to initiate and poll progress of in­ternal byte write and block erase can be stored in
any of the M28F008 blocks. This code is copied to,
and executed from, system RAM during actual flash
memory update. After successful completion of byte
write and/or block erase, code/data reads from the
M28F008 are again possible via the Read Array
command. Erase suspend/resume capability allows
system software to suspend block erase to read
data and execute code from any other block.

FFFFF

64 Kbyte Block

EFFFF

F0000

64 Kbyte Block

DFFFF

E0000

64 Kbyte Block

CFFFF

D0000

64 Kbyte Block

BFFFF

C0000

64 Kbyte Block

AFFFF

B0000

64 Kbyte Block

9FFFF

A0000

64 Kbyte Block

8FFFF

90000

64 Kbyte Block

7FFFF

80000

64 Kbyte Block

6FFFF

70000

64 Kbyte Block

5FFFF

60000

64 Kbyte Block

4FFFF

50000

64 Kbyte Block

3FFFF

40000

64 Kbyte Block

2FFFF

30000

64 Kbyte Block

1FFFF

20000

64 Kbyte Block

0FFFF

10000

64 Kbyte Block

00000

Figure 4. Memory Map

Command User Interface and Write
Automation

An on-chip state machine controls block erase and
byte write, freeing the system processor for other
tasks. After receiving the Erase Setup and Erase
Confirm commands, the state machine controls
block pre-conditioning and erase, returning progress
via the Status Register and RY/BY

output. Byte
write is similarly controlled, after destination address
and expected data are supplied. The program and
erase algorithms of past Intel Flash memories are
now regulated by the state machine, including pulse
repetition where required and internal verification
and margining of data.

Data Protection

Depending on the application, the system designer
may choose to make the V

PP

power supply switcha­ble (available only when memory byte writes/block
erases are required) or hardwired to V

PPH

. When

V

PP

e

V

PPL

, memory contents cannot be altered.
The M28F008 Command User Interface architecture
provides protection from unwanted byte write or
block erase operations even when high voltage is
applied to V

PP

. Additionally, all functions are dis-

abled whenever V

CC

is below the write lockout volt-

age V

LKO

, or when RP is at VIL. The M28F008 ac­commodates either design practice and encourages
optimization of the processor-memory interface.

The two-step byte write/block erase Command User
Interface write sequence provides additional soft­ware write protection.

BUS OPERATION

Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.

Read

The M28F008 has three read modes. The memory
can be read from any of its blocks, and information
can be read from the intelligent identifier or Status
Register. V

PP

can be at either V

PPL

or V

PPH

.

The first task is to write the appropriate read mode
command to the Command User Interface (array, in­telligent identifier, or Status Register). The M28F008
automatically resets to Read Array mode upon initial
device powerup or after exit from deep powerdown.
The M28F008 has four control pins, two of which

6

M28F008

Table 2. Bus Operations

Mode Notes RP CE OE WE A0V

PP

DQ

0–7

RY/BY

Read 1, 2, 3 V

IHVIL

V

ILVIH

XXD

OUT

X

Output Disable 3 V

IHVILVIHVIH

X X High Z X

Standby 3 V

IHVIH

X X X X High Z X

PowerDown V

IL

X X X X X High Z V

OH

Intelligent Identifier (Mfr) V

IHVILVIL

V

IH

V

IL

X 89H V

OH

Intelligent Identifier (Device) V

IHVILVIL

V

IH

V

IH

X A2H V

OH

Write 3, 4, 5 V

IHVILVIHVIL

XX DINX

NOTES:

1. Refer to DC Characteristics. When V

PP

e

V

PPL

, memory contents can be read but not written or erased.

2. X can be V

IL

or VIHfor control pins and addresses, and V

PPL

or V

PPH

for VPP. See DC Characteristics for V

PPL

and V

PPH

voltages.

3. RY/BY

is VOLwhen the Write State Machine is executing internal block erase or byte write algorithms. It is VOHwhen the

WSM is not busy, in Erase Suspend mode or deep powerdown mode.

4. Command writes involving block erase or byte write are only successfully executed when V

PP

e

V

PPH

.

5. Refer to Table 3 for valid D

IN

during a write operation.

must be logically active to obtain data at the outputs.
Chip Enable (CE

) is the device selection control, and
when active enables the selected memory device.
Output Enable (OE

) is the data input/output (DQ0–

DQ

7

) direction control, and when active drives data

from the selected memory onto the I/O bus. RP

and

WE

must also be at VIH. Figure 8 illustrates read bus

cycle waveforms.

Output Disable

With OE at a logic-high level (VIH), the device out­puts are disabled. Output pins (DQ

0

–DQ7) are

placed in a high-impedance state.

Standby

CE at a logic-high level (VIH) places the M28F008 in
standby mode. Standby operation disables much of
the M28F008’s circuitry and substantially reduces
device power consumption. The outputs (DQ

0

–DQ7)
are placed in a high-impedence state independent of
the status of OE

. If the M28F008 is deselected dur­ing block erase or byte write, the device will continue
functioning and consuming normal active power until
the operation completes.

Deep Power-Down

The M28F008 offers a deep powerdown feature, en­tered when RP

is at VIL. Current draw thru VCCis
100 mA maximum in deep powerdown mode, with
current draw through V

PP

20 mA maximum. During

read modes, RP

at a logic-low level (VIL) deselects
the memory, places output drivers in a high-impe­dence state and turns off all internal circuits. The
M28F008 requires time t

PHQV

(see AC Characteris­tics-Read-Only Operations) after return from power­down until initial memory access outputs are valid.
After this wakeup interval, normal operation is re­stored. The Command User Interface is reset to
Read Array mode, and the upper 5 bits of the Status
Register are cleared to value 10000, upon return to
normal operation.

During block erase or byte write modes, RP

at a log-

ic-low level (V

IL

) will abort either operation. Memory
contents of the block being altered are no longer
valid as the data will be partially written or erased.
Time t

PHWL

after RP goes to logic-high (VIH) is re-

quired before another command can be written.

Intelligent Identifier Operation

The intelligent identifier operation outputs the manu­facturer code, 89H; and the device code, A2H for
the M28F008. The system CPU can then automati­cally match the device with its proper block erase
and byte write algorithms.

The manufacturer and device codes are read via the
Command User Interface. Following a write of 90H
to the Command User Interface, a read from ad­dress location 00000H outputs the manufacturer
code (89H). A read from address location 00001H
outputs the device code (A2H). It is not necessary to
have high voltage applied to V

PP

to read the intelli-

gent identifier from the Command User Interface.

7

M28F008

Table 3. Command Definitions

Command Cycles

Req’d

Bus

Notes

First Bus Cycle Second Bus Cycle

Operation Address Data Operation Address Data

Read Array/Reset 1 1 Write X FFH

Intelligent Identifier 3 2, 3, 4 Write X 90H Read IA IID

Read Status Register 2 3 Write X 70H Read X SRD

Clear Status Register 1 Write X 50H

Erase Setup/Erase Confirm 2 2 Write BA 20H Write BA D0H

Erase Suspend/Erase Resume 2 Write X B0H Write X D0H

Byte Write Setup/Write 2 2, 3, 5 Write WA 40H Write WA WD

Alternate Byte Write Setup/Write 2 2, 3, 5 Write WA 10H Write WA WD

NOTES:

1. Bus operations are defined in Table 2.

2. IA

e

Identifier Address: 00H for manufacturer code, 01H for device code.

BA

e

Address within the block being erased.

WA

e

Address of memory location to be written.

3. SRD

e

Data read from Status Register. See Table 4 for a description of the Status Register bits.

WD

e

Data to be written at location WA. Data is latched on the rising edge of WE.

IID

e

Data read from intelligent identifiers.

4. Following the intelligent identifier command, two read operations access manufacture and device codes.

5. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command.

6. Commands other than those shown above are reserved by Intel for future device implementations and should not be
used.

Write

Writes to the Command User Interface enable read­ing of device data and intelligent identifier. They also
control inspection and clearing of the Status Regis­ter. Additionally, when V

PP

e

V

PPH

, the Command
User Interface controls block erasure and byte write.
The contents of the interface register serve as input
to the internal write state machine.

The Command User Interface itself does not occupy
an addressable memory location. The interface reg­ister is a latch used to store the command and ad­dress and data information needed to execute the
command. Erase Setup and Erase Confirm com­mands require both appropriate command data and
an address within the block to be erased. The Byte
Write Setup command requires both appropriate
command data and the address of the location to be
written, while the Byte Write command consists of
the data to be written and the address of the loca­tion to be written.

The Command User Interface is written by bringing
WE

to a logic-low level (VIL) while CE is low. Ad­dresses and data are latched on the rising edge of
WE

. Standard microprocessor write timings are

used.

Refer to AC Write Characteristics and the AC Wave­forms for Write Operations, Figure 9, for specific tim­ing parameters.

COMMAND DEFINITIONS

When V

PPL

is applied to the VPPpin, read opera­tions from the Status Register, intelligent identifier,
or array blocks are enabled. Placing V

PPH

on V

PP

enables successful byte write and block erase oper­ations as well.

Device operations are selected by writing specific
commands into the Command User Interface. Table
3 defines the M28F008 commands.

Read Array Command

Upon initial device powerup and after exit from deep
powerdown mode, the M28F008 defaults to Read
Array mode. This operation is also initiated by writing
FFH into the Command User Interface. Microproces­sor read cycles retrieve array data. The device re­mains enabled for reads until the Command User
Interface contents are altered. Once the internal
Write State Machine has started a block erase or
byte write operation, the device will not recognize

8

M28F008

Table 4. Status Register Definitions

WSMS ESS ES BWS VPPS R R R

76543210

SR.7

e

WRITE STATE MACHINE STATUS

1

e

Ready

0

e

Busy

SR.6

e

ERASE SUSPEND STATUS

1

e

Erase Suspended

0

e

Erase in Progress/Completed

SR.5

e

ERASE STATUS

1

e

Error in Block Erasure

0

e

Successful Block Erase

SR.4

e

BYTE WRITE STATUS

1

e

Error in Byte Write

0

e

Successful Byte Write

SR.3

e

VPPSTATUS

1

e

VPPLow Detect; Operation Abort

0

e

VPPOK

SR.2–SR.0

e

RESERVED FOR FUTURE

ENHANCEMENTS
These bits are reserved for future use and
should be masked out when polling the Status
Register.

NOTES:

RY/BY

or the Write State Machine Status bit must first
be checked to determine byte write or block erase com­pletion, before the Byte Write or Erase Status bit are
checked for success.

If the Byte Write AND Erase Status bits are set to ‘‘1’’s
during a block erase attempt, an improper command se­quence was entered. Attempt the operation again.

If V

PP

low status is detected, the Status Register must be
cleared before another byte write or block erase opera­tion is attempted.

The V

PP

Status bit, unlike an A/D converter, does not

provide continuous indication of V

PP

level. The WSM in-

terrogates the V

PP

level only after the byte write or block
erase command sequences have been entered and in­forms the system if V

PP

has not been switched on. The

V

PP

Status bit is not guaranteed to report accurate feed-

back between V

PPL

and V

PPH

.

the Read Array command, until the WSM has com­pleted its operation. The Read Array command is
functional when V

PP

e

V

PPL

or V

PPH

.

Intelligent Identifier Command

The M28F008 contains an intelligent identifier oper­ation, initiated by writing 90H into the Command
User Interface. Following the command write, a read
cycle from address 00000H retrieves the manufac­turer code of 89H. A read cycle from address 01H
returns the device code of A2H. To terminate the
operation, it is necessary to write another valid com­mand into the register. Like the Read Array com­mand, the intelligent identifier command is functional
when V

PP

e

V

PPL

or V

PPH

.

Read Status Register Command

The M28F008 contains a Status Register which may
be read to determine when a byte write or block
erase operation is complete, and whether that oper­ation completed successfully. The Status Register
may be read at any time by writing the Read Status
Register command (70H) to the Command User In­terface. After writing this command, all subsequent
read operations output data from the Status Regis­ter, until another valid command is written to the

Command User Interface. The contents of the
Status Register are latched on the falling edge of OE
or CE, whichever occurs last in the read cycle. OE or
CE

must be toggled to VIHbefore further reads to
update the Status Register latch. The Read Status
Register command functions when V

PP

e

V

PPL

or

V

PPH

.

Clear Status Register Command

The Erase Status and Byte Write Status bits are set
to ‘‘1’’s by the Write State Machine and can only be
reset by the Clear Status Register Command. These
bits indicate various failure conditions (see Table 4).
By allowing system software to control the resetting
of these bits, several operations may be performed
(such as cumulatively writing several bytes or eras­ing multiple blocks in sequence). The Status Regis­ter may then be polled to determine if an error oc­curred during that sequence. This adds flexibility to
the way the device may be used.

Additionally, the V

PP

Status bit (SR.3) MUST be re­set by system software before further byte writes or
block erases are attempted. To clear the Status
Register, the Clear Status Register command (50H)
is written to the Command User Interface. The Clear
Status Register command is functional when V

PP

e

V

PPL

or V

PPH

.

9

M28F008

Erase Setup/Erase Confirm
Commands

Erase is executed one block at a time, initiated by a
two-cycle command sequence. An Erase Setup
command (20H) is first written to the Command User
Interface, followed by the Erase Confirm command
(D0H). These commands require both appropriate
sequencing and an address within the block to be
erased to FFH. Block preconditioning, erase and
verify are all handled internally by the Write State
Machine, invisible to the system. After the two-com­mand erase sequence is written to it, the M28F008
automatically outputs Status Register data when
read (see Figure 6; Block Erase Flowchart). The
CPU can detect the completion of the erase event
by analyzing the output of the RY/BY

pin, or the

WSM Status bit of the Status Register.

When erase is completed, the Erase Status bit
should be checked. If erase error is detected, the
Status Register should be cleared. The Command
User Interface remains in Read Status Register
mode until further commands are issued to it.

This two-step sequence of set-up followed by execu­tion ensures that memory contents are not acciden­tally erased. Also, reliable block erasure can only
occur when V

PP

e

V

PPH

. In the absence of this high
voltage, memory contents are protected against era­sure. If block erase is attempted while V

PP

e

V

PPL

,

the V

PP

Status bit will be set to ‘‘1’’. Erase attempts

while V

PPL

k

V

PP

k

V

PPH

produce spurious results

and should not be attempted.

Erase Suspend/Erase Resume
Commands

The Erase Suspend command allows block erase
interruption in order to read data from another block
of memory. Once the erase process starts, writing
the Erase Suspend command (B0H) to the Com­mand User Interface requests that the WSM sus­pend the erase sequence at a predetermined point
in the erase algorithm. The M28F008 continues to
output Status Register data when read, after the
Erase Suspend command is written to it. Polling the
WSM status and Erase Suspend status bits will de­termine when the erase operation has been sus­pended (both will be set to ‘‘1’’). RY/BY

will also

transition to V

OH

.

At this point, a Read Array command can be written
to the Command User Interface to read data from
blocks other than that which is suspended. The only
other valid commands at this time are Read Status
Register (70H) and Erase Resume (D0H), at which
time the WSM will continue with the erase process.
The Erase Suspend status and WSM status bits of
the Status Register will be automatically cleared and
RY/BY

will return to VOL. After the Erase Resume
command is written to it, the M28F008 automatically
outputs Status Register data when read (see Figure
7; Erase Suspend/Resume Flowchart). V

PP

must re-

main at V

PPH

while the M28F008 is in Erase Sus-

pend.

Byte Write Setup/Write Commands

Byte write is executed by a two-command sequence.
The Byte Write Setup command (40H) is written to
the Command User Interface, followed by a second
write specifying the address and data (latched on
the rising edge of WE) to be written. The WSM then
takes over, controlling the byte write and write verify
algorithms internally. After the two-command byte
write sequence is written to it, the M28F008 auto­matically outputs Status Register data when read
(see Figure 5; Byte Write Flowchart). The CPU can
detect the completion of the byte write event by ana­lyzing the output of the RY/BY

pin, or the WSM
status bit of the Status Register. Only the Read
Status Register command is valid while byte write is
active.

When byte write is complete, the Byte Write status
bit should be checked. If byte write error is detected,
the Status Register should be cleared. The internal
WSM verify only detects errors for ‘‘1’’s that do not
successfully write to ‘‘0’’s. The Command User In­terface remains in Read Status Register mode until
further commands are issued to it. If byte write is
attempted while V

PP

e

V

PPL

, the VPPStatus bit will

be set to ‘‘1’’. Byte write attempts while

V

PPL

k

V

PP

k

V

PPH

produce spurious results and should not be attempt­ed.

10

M28F008

EXTENDED BLOCK ERASE/BYTE
WRITE CYCLING

Intel has designed extended cycling capability into
its ETOX flash memory technologies. The M28F008
is designed for 10,000 byte write/block erase cycles
on each of the sixteen 64 Kbyte blocks. Low electric
fields, advanced oxides and minimal oxide area per
cell subjected to the tunneling electric field combine
to greatly reduce oxide stress and the probability of
failure. A 20 Mbyte solid-state drive using an array of
M28F008s has a MTBF (Mean Time Between Fail­ure) of 3.33 million hours

(1)

, over 600 times more

reliable than equivalent rotating disk technology.

AUTOMATED BYTE WRITE

The M28F008 integrates the Quick-Pulse program­ming algorithm of prior Intel Flash devices on-chip,
using the Command User Interface, Status Register
and Write State Machine (WSM). On-chip integration
dramatically simplifies system software and provides
processor interface timings to the Command User
Interface and Status Register. WSM operation, inter­nal verify and V

PP

high voltage presence are moni-

tored and reported via the RY/BY

output and appro­priate Status Register bits. Figure 5 shows a system
software flowchart for device byte write. The entire
sequence is performed with V

PP

at V

PPH

. Byte write

abort occurs when RP

transitions to VIL,orV

PP

drops to V

PPL

. Although the WSM is halted, byte
data is partially written at the location where byte
write was aborted. Block erasure, or a repeat of byte
write, is required to initialize this data to a known
value.

AUTOMATED BLOCK ERASE

As above, the Quick-Erase algorithm of prior Intel
Flash devices is now implemented internally, includ­ing all preconditioning of block data. WSM opera­tion, erase success and V

PP

high voltage presence

are monitored and reported through RY/BY

and the
Status Register. Additionally, if a command other
than Erase Confirm is written to the device following
Erase Setup, both the Erase Status and Byte Write
Status bits will be set to ‘‘1’’s. When issuing the
Erase Setup and Erase Confirm commands, they
should be written to an address within the address
range of the block to be erased. Figure 6 shows a
system software flowchart for block erase.

Erase typically takes 1.6 seconds per block. The
Erase Suspend/Erase Resume command sequence
allows suspension of this erase operation to read
data from a block other than that in which erase is
being performed. A system software flowchart is
shown in Figure 7.

The entire sequence is performed with V

PP

at V

PPH

.

Abort occurs when RP

transitions to VILor VPPfalls

to V

PPL

, while erase is in progress. Block data is
partially erased by this operation, and a repeat of
erase is required to obtain a fully erased block.

DESIGN CONSIDERATIONS

Three-Line Output Control

The M28F008 will often be used in large memory
arrays. Intel provides three control inputs to accom­modate multiple memory connections. Three-line
control provides for:

a) lowest possible memory power dissipation

b) complete assurance that data bus contention will

not occur

To efficiently use these control inputs, an address
decoder should enable CE

, while OE should be con­nected to all memory devices and the system’s
READ

control line. This assures that only selected
memory devices have active outputs while deselect­ed memory devices are in Standby Mode. Finally,
RP

should either be tied to the system RESET,or

connected to V

CC

if unused.

RY/BY and Byte Write/Block Erase
Polling

RY/BY is a full CMOS output that provides a hard­ware method of detecting byte write and block erase
completion. It transitions low time t

WHRL

after a
write or erase command sequence is written to the
M28F008, and returns to V

OH

when the WSM has

finished executing the internal algorithm.

RY/BY

can be connected to the interrupt input of
the system CPU or controller. It is active at all times,
not tri-stated if the M28F008 CE

or OE inputs are

brought to V

IH

. RY/BY is also VOHwhen the device

is in Erase Suspend or deep powerdown modes.

(1)

Assumptions: 10 Kbyte file written every 10 minutes. (20 Mbyte array)/(10 Kbyte file)e2,000 file writes before erase required.

(2000 files writes/erase)

c

(10,000 cycles per M28F008 block)e20 million file writes.

(20

c

106file writes)c(10 min/write)c(1 hr/60 min)e3.33c106MTBF.

11

M28F008

271232– 4

Bus

Command Comments

Operation

Write Byte Write Datae40H (10H)

Setup Address

e

Byte to be written

Write Byte Write Data to be written

AddresseByte to be written

Standby/Read Check RY/BY

V

OH

e

Ready, V

OL

e

Busy

or
Read Status Register
Check SR.7
1eReady, 0eBusy
Toggle OE

or CE to update

Status Register

Repeat for subsequent bytes

Full status check can be done after each byte or after a
sequence of bytes

Write FFH after the last byte write operation to reset the
device to Ready Array Mode

FULL STATUS CHECK PROCEDURE

271232– 5

Bus

Command Comments

Operation

Optional CPU may already have read

Status Register data in WSM

Read

Ready polling above

Standby Check SR.3

1eVPPLow Detect

Standby Check SR.4

1

e

Byte Write Error

SR.3 MUST be cleared, if set during a byte write attempt,
before further attempts are allowed by the Write State
Machine.

SR.4 is only cleared by the Clear Status Register Command,
in cases where multiple bytes are written before full status is
checked.

If error is detected, clear the Status Register before
attempting retry or other error recovery.

Figure 5. Automated Byte Write Flowchart

12

M28F008

271232– 6

Bus

Command Comments

Operation

Write Erase Datae20H

Setup Address

e

Within block to be

erased

Write Erase Data

e

D0H
AddresseWithin block to be
erased

Standby/Read Check RY/BY

V

OH

e

Ready, V

OL

e

Busy

or
Read Status Register
Check SR.7
1eReady, 0eBusy
Toggle OE

or CE to update

Status Register

Repeat for subsequent bytes

Full status check can be done after each block or after a
sequence of blocks

Write FFH after the last block erase operation to reset the
device to Ready Array Mode

FULL STATUS CHECK PROCEDURE

271232– 7

Bus

Command Comments

Operation

Optional CPU may already have read

Status Register data in WSM

Read

Ready polling above

Standby Check SR.3

1eVPPLow Detect

Standby Check SR.4,5

Both 1

e

Command Sequence

Error

Standby Check SR.5

1eBlock Erase Error

SR.3 MUST be cleared, if set during a block erase attempt,
before further attempts are allowed by the Write State
Machine

SR.5 is only cleared by the Clear Status Register Command,
in cases where multiple blocks are erased before full status is
checked.

If error is detected, clear the Status Register before
attempting retry or other error recovery.

Figure 6. Automated Block Erase Flowchart

13

M28F008

271232– 8

Bus

Command Comments

Operation

Write Erase DataeB0H

Suspend

Write Read Data

e

70H

Status Register

Standby/ Check RY/BY

Read V

OH

e

Ready, V

OL

e

Busy or Read Status
Register

Check SR.7
1eReady, 0eBusy
Toggle OE

or CE to Update

Status Register

Standby Check SR.6

1

e

Suspended

Write Read Array DataeFFH

Read Read array data from block

other than that being
erased.

Write Erase Resume DataeD0H

Figure 7. Erase Suspend/Resume Flowchart

14

M28F008

Power Supply Decoupling

Flash memory power switching characteristics re­quire careful device decoupling. System designers
are interested in 3 supply current issues; standby
current levels (I

SB

), active current levels (ICC) and
transient peaks produced by falling and rising edges
of CE

. Transient current magnitudes depend on the
device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 mF ceramic capacitor
connected between each V

CC

and GND, and be-

tween its V

PP

and GND. These high frequency, low
inherent-inductance capacitors should be placed as
close as possible to package leads. Additionally, for
every 8 devices, a 4.7 mF electrolytic capacitor
should be placed at the array’s power supply con­nection between V

CC

and GND. The bulk capacitor
will overcome voltage slumps caused by PC board
trace inductances.

VPPTrace on Printed Circuit Boards

Writing flash memories, while they reside in the tar­get system, requires that the printed circuit board
designer pay attention to the V

PP

power supply

trace. The V

PP

pin supplies the memory cell current
for writing and erasing. Use similar trace widths and
layout considerations given to the V

CC

power bus.

Adequate V

PP

supply traces and decoupling will de-

crease V

PP

voltage spikes and overshoots.

VCC,VPP,RPTransitions and the
Command/Status Registers

Byte write and block erase completion are not guar­anteed if V

PP

drops below V

PPH

. If the VPPStatus bit
of the Status Register (SR.3) is set to ‘‘1’’, a Clear
Status Register command MUST be issued before
further byte write/block erase attempts are allowed
by the WSM. Otherwise, the Byte Write (SR.4) or
Erase (SR.5) Status bits of the Status Register will
be set to ‘‘1’’s if error is detected. RP

transitions to

V

IL

during byte write and block erase also abort the
operations. Data is partially altered in either case,
and the command sequence must be repeated after
normal operation is restored. Device poweroff, or RP
transitions to VIL, clear the Status Register to initial
value 10000 for the upper 5 bits.

The Command User Interface latches commands as
issued by system software and is not altered by V

PP

or CE transitions or WSM actions. Its state upon
powerup, after exit from deep powerdown or after
V

CC

transitions below V

LKO

, is Read Array Mode.

After byte write or block erase is complete, even
after V

PP

transitions down to V

PPL

, the Command
User Interface must be reset to Read Array mode via
the Read Array command if access to the memory
array is desired.

Power Up/Down Protection

The M28F008 is designed to offer protection against
accidental block erasure or byte writing during power
transitions. Upon power-up, the M28F008 is indiffer­ent as to which power supply, V

PP

or VCC, powers
up first. Power supply sequencing is not required.
Internal circuitry in the M28F008 ensures that the
Command User Interface is reset to the Read Array
mode on power up.

A system designer must guard against spurious
writes for V

CC

voltages above V

LKO

when VPPis

active. Since both WE

and CE must be low for a

command write, driving either to V

IH

will inhibit
writes. The Command User Interface architecture
provides an added level of protection since altera­tion of memory contents only occurs after success­ful completion of the two-step command sequences.

Finally, the device is disabled until RP

is brought to

V

IH

, regardless of the state of its control inputs. This

provides an additional level of memory protection.

Power Dissipation

When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases us­able battery life, because the M28F008 does not
consume any power to retain code or data when the
system is off.

In addition, the M28F008’s deep powerdown mode
ensures low power dissipation even when system
power is applied. For example, portable PCs and
other power sensitive applications, using an array of
M28F008s for solid-state storage, can lower RP

to

V

IL

in standby or sleep modes, reducing power con­sumption. If access to the M28F008 is again need­ed, the part can again be read, following the t

PHQV

and t

PHWL

wakeup cycles required after RP is first

raised back to V

IH

. See AC CharacteristicsÐRead­Only and Write Operations and Figures 8 and 9 for
more information.

15

M28F008

ABSOLUTE MAXIMUM RATINGS*

Operating TemperatureАААААААААb55§Ctoa125§C

Temperature Under BiasААААААААb55§Ctoa125§C

Storage Temperature АААААААААА

b

65§Ctoa125§C

Voltage on Any Pin

(except V

CC

and VPP)

with Respect to GND АААААААА

b

2.0V toa7.0V

(1)

VPPProgram Voltage with

Respect to GND during
Block Erase/Byte Write ÀÀÀ

b

2.0V toa14.0V

(1, 2)

VCCSupply Voltage

with Respect to GND АААААААА

b

2.0V toa7.0V

(1)

Output Short Circuit CurrentААААААААААААА100 mA

(3)

NOTICE: This data sheet contains preliminary infor­mation on new products in production. The specifica­tions are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.

*

WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex­tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.

NOTES:

1. Minimum DC voltage is

b

0.5V on input/output pins. During transitions, this level may undershoot tob2.0V for periods

k

20 ns. Maximum DC voltage on input/output pins is V

CC

a

0.5V which, during transitions, may overshoot to V

CC

a

2.0V

for periods

k

20 ns.

2. Maximum DC voltage on V

PP

may overshoot toa14.0V for periodsk20 ns.

3. Output shorted for no more than one second. No more than one output shorted at a time.

OPERATING CONDITIONS

Symbol Parameter Min Max Unit

T

C

Operating Temperature

b

55

a

125

§

C

V

CC

VCCSupply Voltage (10%) 4.50 5.50 V

DC CHARACTERISTICS

Symbol Parameter Notes

MC28F008 and

Unit Test Conditions

MF28F008

Min Max

I

LI

Input Load Current 1

g

1.0 mAV

CC

e

VCCMax

V

IN

e

VCCor GND

I

LO

Output Load Current 1

g

10 mAV

CC

e

VCCMax

V

OUT

e

VCCor GND

I

CCS

VCCStandby Current 1, 3 2.0 mA V

CC

e

VCCMax

CE

eRPe

V

IH

150 mAV

CC

e

VCCMax

CE

eRPe

V

CC

g

0.2V

I

CCD

VCCDeep Powerdown Current 1 100 mARPeGNDg0.2V

I

OUT

(RY/BY)e0mA

I

CCR

VCCRead Current 1 35 mA V

CC

e

VCCMax, CEeGND,

F

e

8 MHz, I

OUT

e

0 mA,

CMOS Inputs

50 mA V

CC

e

VCCMax, CEeVIL,

F

e

8 MHz, I

OUT

e

0 mA,

TTL Inputs

16

M28F008

DC CHARACTERISTICS (Continued)

Symbol Parameter Notes

MC28F008 and

Unit Test Conditions

MF28F008

Min Max

I

CCW

VCCByte Write Current 1 30 mA Byte Write In Progress

I

CCE

VCCBlock Erase Current 1 30 mA Block Erase In Progress

I

CCES

VCCErase Suspend Current 1, 2 10 mA Block Erase Suspended

CE

e

V

IH

I

PPS

VPPStandby Current 1

g

15 mAV

PP

s

V

CC

200 mAV

PP

l

V

CC

I

PPD

VPPDeep PowerDown Current 1 20 mARPeGNDg0.2V

I

PPW

VPPWrite Current 1 30 mA V

PP

e

V

PPH

Byte Write in Progress

I

PPE

VPPBlock Erase Current 1 30 mA V

PP

e

V

PPH

Block Erase in Progress

I

PPES

VPPErase Suspend Current 1 200 mAV

PP

e

V

PPH

Block Erase Suspended

V

IL

Input Low Voltage

b

0.5 0.8 V

V

IH

Input High Voltage 2.0 V

CC

a

0.5 V

V

OL

Output Low Voltage 3 0.45 V V

CC

e

VCCMin

I

OL

e

5.8 mA

V

OH

Output High Voltage 3 2.4 V V

CC

e

VCCMin

I

OH

eb

2.5 mA

V

PPL

VPPduring Normal Operations 4 0.0 6.5 V

V

PPH

VPPduring Erase/Write Operations 11.4 12.6 V

V

LKO

VCCErase/Write Lock Voltage 1.8 V

CAPACITANCE

(5)

T

A

e

25§C, fe1 MHz

Symbol Parameter Typ Max Unit Condition

C

IN

Input Capacitance 6 8 pF V

IN

e

0V

C

OUT

Output Capacitance 8 12 pF V

OUT

e

0V

NOTES:

1. All currents are in RMS unless otherwise noted.

2. I

CCES

is specified with the device deselected. If the M28F008 is read while in Erase Suspend Mode, current draw is the

sum of I

CCES

and I

CCR

.

3. Includes RY/BY

.

4. Block Erases/Byte Writes are inhibited when V

PP

e

V

PPL

and not guaranteed in the range between V

PPH

and V

PPL

.

17

M28F008

AC INPUT/OUTPUT REFERENCE WAVEFORM

271232– 9

AC test inputs are driven at V

OH

(2.4 V

TTL

) for a Logic ‘‘1’’ and VOL(0.45 V

TTL

) for a Logic

‘‘0’’. Input timing begins at V

IH

(2.0 V

TTL

) and VIL(0.8 V

TTL

). Output timing ends at VIHand

V

IL

. Input rise and fall times (10% to 90%)k10 ns.

AC TESTING LOAD CIRCUIT

C

L

e

100 pF

C

L

Includes Jig 271232 – 10

Capacitance

R

L

e

3.3 kX

AC CHARACTERISTICSÐRead-Only Operations

(1, 4)

Symbol Parameter Notes

M28F008-10

(4)

M28F008-12

(4)

Unit

Min Max Min Max

t

AVAVtRC

Read Cycle Time 100 120 ns

t

AVQVtACC

Address to Output Display 100 120 ns

t

ELQVtCE

CE to Output Delay 2 100 120 ns

t

PHQVtPWH

RP High to Output Delay 400 400 ns

t

GLQVtOE

OE to Output Delay 2 60 60 ns

t

ELQXtLZ

CE to Output Low Z 3 0 0 ns

t

EHQZtHZ

CE High to Output High Z 3 55 55 ns

t

GLQXtOLZ

OE to Output Low Z 3 0 0 ns

t

GHQZtDF

OE High to Output High Z 3 30 30 ns

t

OH

Output Hold from 3 0 0 ns
Addresses, CE or OE
Change, Whichever is First

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. OE

may be delayed up to tCE–tOEafter the falling edge of CE without impact on tCE.

3. Sampled, not 100% tested.

4. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.

18

M28F008

Figure 8. AC Waveform for Read Operations

123211– 11

19

M28F008

AC CHARACTERISTICSÐWrite Operations

(1, 7)

Symbol Parameter Notes

M28F008-10

(7)

M28F008-12

(7)

Unit

Min Max Min Max

t

AVAV

t

WC

Write Cycle Time 100 120 ns

t

PHWL

t

PS

RP High Recovery to WE 21 1 ms
Going Low

t

ELWL

t

CS

CE Setup to WE Going Low 10 10 ns

t

WLWHtWP

WE Pulse Width 40 40 ns

t

VPWH

t

VPSVPP

Setup to WE Going 2 100 100 ns

High

t

AVWHtAS

Address Setup to WE Going 3 40 40 ns
High

t

DVWHtDS

Data Setup to WE Going 4 40 40 ns
High

t

WHDXtDH

Data Hold from WE High 5 5 ns

t

WHAXtAH

Address Hold from WE High 5 5 ns

t

WHEHtCH

CE Hold from WE High 10 10 ns

t

WHWLtWPH

WE Pulse Width High 30 30 ns

t

WHRL

WE High to RY/BY Going 100 100 ns
Low

t

WHQV1

Duration of Byte Write 5, 6 6 6 ms
Operation

t

WHQV2

Duration of Block Erase 5, 6 0.3 0.3 sec
Operation

t

WHGL

Write Recovery before 0 0 ms
Read

t

QVVL

t

VPHVPP

Hold from Valid SRD, 2, 6 0 0 ns

RY/BY

High

NOTES:

1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only Operations.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A

IN

for byte write or block erasure.

4. Refer to Table 3 for valid D

IN

for byte write or block erasure.

5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard
Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and
erase verify (block erase).

6. Byte write and block erase durations are measured to completion (SR.7

e

1, RY/BYeVOH). VPPshould be held at

V

PPH

until determination of byte write/block erase success (SR.3/4/5e0)

7. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.

20

M28F008

BLOCK ERASE AND BYTE WRITE PERFORMANCE

Parameter Notes

M28F008-10 M28F008-12

Unit

Min Typ Max Min Typ Max

Block Erase Time 1, 2 1.6 10 1.6 10 sec

Block Write Time 1, 2 0.6 2.1 0.6 2.1 sec

NOTES:

1. 25

§

C, 12.0 VPP.

2. Excludes System-Level Overhead.

21

M28F008

Figure 9. AC Waveform for Write Operations

271232– 12

22

M28F008

ALTERNATIVE CE-CONTROLLED WRITES

(1)

Symbol Parameter Notes

M28F008-10

(6)

M28F008-12

(6)

Unit

Min Max Min Max

t

AVAV

t

WC

Write Cycle Time 100 120 ns

t

PHEL

t

PS

RP High Recovery to CE 21 1 ms
Going Low

t

WLELtWS

WE Setup to CE Going Low 0 0 ns

t

ELEH

t

CP

CE Pulse Width 50 50 ns

t

VPEHtVPSVPP

Setup to CE Going High 2 100 100 ns

t

AVEHtAS

Address Setup to CE Going 3 40 40 ns
High

t

DVEHtDS

Data Setup to CE Going High 4 40 40 ns

t

EHDXtDH

Data Hold from CE High 5 5 ns

t

EHAXtAH

Address Hold from CE

High 5 5 ns

t

EHWHtWH

WE Hold from CE High 0 0 ns

t

EHEL

t

EPH

CE Pulse Width High 25 25 ns

t

EHRL

CE High to RY/BY Going 100 100 ns
Low

t

EHQV1

Duration of Byte Write 5 6 6 ms
Operation

t

EHQV2

Duration of Block Erase 5 0.3 0.3 sec
Operation

t

EHGL

Write Recovery before Read 0 0 m s

t

QVVL

t

VPHVPP

Hold from Valid SRD, 2, 5 0 0 ns

RY/BY High

NOTES:

1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE

and WE. In systems where CE
defines the write pulsewidth (within a longer WE timing waveform), all setup, hold and inactive WE times should be mea­sured relative to the CE

waveform.

2. Sampled, not 100% tested.

3. Refer to Table 3 for valid A

IN

for byte write or block erasure.

4. Refer to Table 3 for valid D

IN

for byte write or block erasure.

5. Byte write and block erase durations are measured to completion (SR.7

e

1, RY/BYeVOH). VPPshould be held at

V

PPH

until determination of byte write/block erase success (SR.3/4/5e0)

6. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.

23

M28F008

Figure 10. Alternate AC Waveform for Write Operations

271232– 13

24

M28F008

ORDERING INFORMATION

MC28F008 - 10

Package Access Time
C

e

40-Pin Sidebrazed DIP 10e100 ns

F

e

42-Lead Flatpack 12e120 ns

X ä Y

ADDITIONAL INFORMATION

Order

Number

28F008SA-L Data Sheet 290435

AP-359 ‘‘28F008SA Hardware Interfacing’’ 292094

AP-360 ‘‘28F008SA Software Drivers’’ 292095

AP-364 ‘‘28F008SA Automation and Algorithms’’ 292099

ER-27 ‘‘The Intel 28F008SA Flash Memory’’ 294011

ER-28 ‘‘ETOX III Flash Memory Technology’’ 290412

25

M28F008

MC28F008 PACKAGE DIMENSIONS

271232– 15

Symbol

Millimeters Inches

Min Max Notes Min Max Notes

a 0

§

10

§

0

§

10

§

A 3.30 5.51 Solid Lid 0.130 0.217 Solid Lid

A

1

1.02 1.52 0.040 0.060

A

2

2.29 3.99 Solid Lid 0.090 0.157 Solid Lid

A

3

2.03 3.66 0.080 0.144

B 0.38 0.56 0.015 0.022

B

1

1.27 Typical 0.050 Typical

C 0.23 0.30 Typical 0.009 0.012 Typical

D 50.29 51.31 1.980 2.020

D

2

48.26 Reference 1.900 Reference

E 15.24 15.75 0.600 0.620

E

1

14.86 15.37 0.585 0.605

e

1

2.29 2.79 0.090 0.110

e

A

14.99 Reference 0.590 Reference

e

B

15.24 17.15 0.600 0.675

L 3.18 4.06 0.125 0.160

N40 40

S 0.76 1.78 0.030 0.070

S

1

0.13 0.005

S

2

0.13 0.005

ISSUE IWS

26

M28F008

MF28F008 PACKAGE DIMENSIONS

271232– 16

Symbol

Millimeters Inches

Min Max Notes Min Max Notes

A 2.08 2.17 Solid Lid 0.082 0.103 Solid Lid

B 0.43 0.58 Typical 0.017 0.023 Typical

C 0.13 0.25 Typical 0.005 0.010 Typical

D 26.67 27.18 1.050 1.070

D

2

25.40 Reference 1.000 Reference

E 16.00 16.51 0.630 0.650

E

2

13.46 13.97 0.530 0.550

E

3

0.89 1.65 0.035 0.065

e

1

1.14 1.40 Typical 0.045 0.055 Typical

H 32.77 Reference 1.29 Reference

L 7.87 8.64 0.310 0.340

N42 42

Q 1.27 1.55 0.050 0.061

S 0.23 1.02 0.009 0.040

S

1

0.00 1.27 0.000 0.050

ISSUE IWS 8/90

27

M28F008

REVISION HISTORY

Number Description

-002 Ð Revised Extended Cycling Capability to
10K Block Erase Cycles
160K Block Erase Cycles per Chip

Ð Changed I

PPS

Standby current spec

from

g

10 mAtog15 mA

Ð Removed typical Block Erase times

Number Description

-003 Ð PWD

renamed RP for JEDEC stan-

dardization compatibility

Ð Added MF, 42-Lead Flatpack

Ð Added 100 ns access time specs

Ð Combined V

PP

Standby current and

V

PP

Read current into one VPPStand­by condition with two test conditions
(DC Characteristics table)

INTEL CORPORATION, 2200 Mission College Blvd., Santa Clara, CA 95052; Tel. [phone]

INTEL CORPORATION (U.K.) Ltd., Swindon, United Kingdom; Tel. [phone]

INTEL JAPAN k.k., Ibaraki-ken; Tel. [phone]

Printed in U.S.A./xxxx/1295/B10M/xx xx