Page 1
MOTOROLA CMOS LOGIC DATAMC14099B MC14599B
246
The MC14099B and MC14599B are 8–bit addressable latches. Data is
entered in serial form when the appropriate latch is addressed (via address
pins A0, A1, A2) and write disable is in the low state. Chip enable must be
high for w riting into MC14599B. F or the MC14599B the data pin is a
bidirectional data port and for the MC14099B the input is a unidirectional
write only port. The Write/Read
line controls this port in the MC14599B.
The d ata is p resented in p arallel a t the output of t he eight latches
independently of the state of Write Disable, Write/Read
or Chip Enable.
A Master Reset capability is available on both parts.
• Serial Data Input
• Parallel Output
• Master Reset
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–Power
Schottky TTL Load over the Rated Temperature Range
• MC14099B pin for pin compatible with CD4099B
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage
– 0.5 to + 18.0
V
Vin, V
out
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, I
out
Input or Output Current (DC or Transient),
per Pin
± 10
mA
P
D
Power Dissipation, per Package†
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
MC14099B MC14599B
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q3
Q4
Q5
Q6
V
DD
Q0
Q1
Q2
WRITE
DISABLE
DATA
RESET
Q7
V
SS
A2
A1
A0
A0
DATA
RESET
Q7
V
SS
CE
A2
A1
WRITE
DISABLE
Q4
Q5
Q6
V
DD
WRITE/
READ
Q0
Q1
Q2
Q3
14
15
16
17
18
10
11
12
13
5
4
3
2
1
9
8
7
6
PIN ASSIGNMENT
PIN ASSIGNMENT
CHIP ENABLE
WRITE/READ
WRITE DISABLE
DATA
A0
A1
A2
RESET
8
10
4
3
2
5
6
7
DECODER
11
12
13
14
15
16
17
1
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
8
LATCHES
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
8
LATCHES
DECODER
5
6
7
WRITE DISABLE
DATA
A0
A1
A2
RESET
8
4
3
2
8
VDD = 18
VSS = 9
VDD = 16
VSS = 8
9
10
11
12
13
14
15
1
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 0
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14099BCP Plastic
MC14099BCL Ceramic
MC14099BDW SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
L SUFFIX
CERAMIC
CASE 726
ORDERING INFORMATION
MC14599BCP Plastic
MC14599BCL Ceramic
P SUFFIX
PLASTIC
CASE 707
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and V
out
should be constrained
to the range VSS v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or VDD). Unused outputs must be left open.
TA = – 55° to 125°C for all packages.
Page 2
MOTOROLA CMOS LOGIC DATA
247
MC14099B MC14599B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C
25_C
125_C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ #
Max
Min
ÎÎÎ
ÎÎÎ
ÎÎÎ
Max
Unit
Output Voltage
“0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
mAdc
Input Current
I
in
15
—
± 0.1
—
±0.00001
± 0.1
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
± 1.0
µAdc
Input Capacitance
(Vin = 0)
C
in
—
—
—
—
5.0
7.5
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
pF
Input Capacitance
MC14599B — Data (pin 3)
(Vin = 0)
C
in
—
—
—
—
15
22.5
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (1.5 µA/kHz) f + I
DD
IT = (3.0 µA/kHz) f + I
DD
IT = (4.5 µA/kHz) f + I
DD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
Page 3
MOTOROLA CMOS LOGIC DATAMC14099B MC14599B
248
SWITCHING CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C)
Characteristic
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Symbol
V
DD
Vdc
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Min
Typ #
Max
Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.35 ns/pF) CL + 32 ns
t
TLH
, t
THL
= (0.6 ns/pF) CL + 20 ns
t
TLH
, t
THL
= (0.4 ns/pF) CL + 20 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
TLH
,
t
THL
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Data to Output Q
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
PHL
,
t
PLH
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
200
75
50
400
150
100
ns
Write Disable to Output Q
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
200
80
60
400
160
120
ns
Reset to Output Q
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
175
80
65
350
160
130
ns
CE to Output Q (MC14599B only)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
225
100
75
450
200
150
ns
Propagation Delay Time, MC14599B only
Chip Enable, Write/Read
to Data
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
PHL
,
t
PLH
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
200
80
65
400
160
130
ns
Address to Data
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
200
90
75
400
180
150
ns
Pulse Widths
Reset
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
w(H)
t
w(L)
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
150
75
50
75
40
25
—
—
—
ns
Write Disable
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
320
160
120
160
80
60
—
—
—
ns
Set Up Time
Data to Write Disable
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
su
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
100
50
35
50
25
20
—
—
—
ns
Hold Time
Write Disable to Data
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
h
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
150
75
50
75
40
25
—
—
—
ns
Set Up Time
Address to Write Disable
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
su
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
100
80
40
45
30
10
—
—
—
ns
Removal Time
Write Disable to Address
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
rem
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
0
0
0
– 80
– 40
– 40
—
—
—
ns
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Page 4
MOTOROLA CMOS LOGIC DATA
249
MC14099B MC14599B
RESET
DATA
WRITE
DISABLE
A0
A1
A2
(M.S.B.)
7
6
5
4
3
2
ADDRESS
DECODER
TO
OTHER
LATCHES
ZERO
SELECT
OTHER LATCHES
EACH LATCH
14 Q5
1 Q7
15 Q6
13 Q4
12 Q3
11 Q2
10 Q1
9 Q0
MC14099B
FUNCTION DIAGRAM
TRUTH TABLE
Write
Disable
Reset
Addressed
Latch
Unaddressed
Latches
0 0 Data Qn*
0 1 Data Reset
†
1 0 Qn* Qn*
1 1 Reset Reset
*Qn is previous state of latch.
†Reset to zero state.
SWITCHING WAVEFORMS
DATA OR
WRITE DISABLE
OUTPUT Q
RESET
OUTPUT Q
V
DD
V
SS
V
DD
V
SS
t
PHL
50%
t
TLH
t
THL
90%
50%
10%
50%
t
PLH
t
PHL
ADDRESS
WRITE
DISABLE
DATA
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
50%
50%
50%
t
su
t
w(L)trem
t
su
t
h
t
w(H)
CAUTION: To avoid unintentional data changes in the latches, W rite
Disable must be active (high) during transitions on the
address inputs A0, A1, and A2.
Page 5
MOTOROLA CMOS LOGIC DATAMC14099B MC14599B
250
RESET
DATA
WRITE
DISABLE
A0
A1
A2
(M.S.B.)
7
6
5
4
3
2
CHIP
ENABLE
8
WRITE/READ
10
V
SS
V
DD
ADDRESS
DECODER
TO
OTHER
LATCHES
ZERO
SELECT
OTHER LATCHES
EACH LATCH
16 Q5
1 Q7
17 Q6
15 Q4
14 Q3
13 Q2
12 Q1
11 Q0
MC14599B
FUNCTION DIAGRAM
TRUTH TABLE
Chip
Enable
Write/Read
Write
Disable
Reset
Addressed
Latch
Other
Latches
Data
Pin
0 X X 0 * * Z
1 1 0 0 Data * Input
1 1 1 0 * * Z
1 0 X 0 * * Q
n
X X X 1 0 0 Z/0
X = Don’t care.
* = No change in state of latch.
Z = High impedance.
Qn = State of addressed latch.
CAUTION: To avoid unintentional data changes in the latches, Write Disable must be active (high) during transitions on
the address inputs A0, A1, and A2.
Page 6
MOTOROLA CMOS LOGIC DATA
251
MC14099B MC14599B
MC14599B
SWITCHING WAVEFORMS
DATA READ
DATA WRITE
WRITE DISABLE
DATA
A2, A1, A0
CE
RESET
Q7
Q0
t
PHL
t
TLH
t
PHL
50%
90%
10%
90%
10%
t
THL
t
PLH
t
PLH
t
w(H)
50%
50%
50% 50%
10% 10%
90%
20 ns20 ns
t
su
t
w(L)
t
rem
t
h
t
su
A2, A1, A0
DATA
CE
W/R
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
50%
t
PLH
,
t
PHL
t
PLH
,
t
PHL
50%
1
NOTE: 1. Invalid Data Output
2. Reset in LOW State
Page 7
MOTOROLA CMOS LOGIC DATAMC14099B MC14599B
252
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
F
E
G
N
K
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
Page 8
MOTOROLA CMOS LOGIC DATA
253
MC14099B MC14599B
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
_ _ _ _
L SUFFIX
CERAMIC DIP PACKAGE
CASE 726–04
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F FOR FULL LEADS. HALF
LEADS OPTIONAL AT LEAD POSITIONS 1, 9,
10, AND 18.
1
SEATING
PLANE
10
9
18
M
K
C
N
F
G
D
L
–A–
–B–
18 PL
J 18 PL
–T–
S
A
M
0.25 (0.010) T
S
B
M
0.25 (0.010) T
OPTIONAL LEAD
CONFIGURATION (1, 9, 10, 18)
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 22.35 23.110.880 0.910
B 6.10 7.490.240 0.295
C ––– 5.08––– 0.200
D 0.38 0.530.015 0.021
G 2.54 BSC0.100 BSC
J 0.20 0.300.008 0.012
K 3.18 4.320.125 0.170
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.020.020 0.040
_ __ _
F 1.40 1.780.055 0.070
Page 9
MOTOROLA CMOS LOGIC DATAMC14099B MC14599B
254
P SUFFIX
PLASTIC DIP PACKAGE
CASE 707–02
ISSUE C
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
1
SEATING
PLANE
10
9
18
M
A
B
K
C
N
F
G
D
H
J
L
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 22.22 23.24 0.875 0.915
B 6.10 6.60 0.240 0.260
C 3.56 4.57 0.140 0.180
D 0.36 0.56 0.014 0.022
F 1.27 1.78 0.050 0.070
G 2.54 BSC 0.100 BSC
H 1.02 1.52 0.040 0.060
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
L 7.62 BSC 0.300 BSC
M 0 15 0 15
N 0.51 1.02 0.020 0.040
_ _ _ _
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MC14099B/D
*MC14099B/D*
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