Page 1
MC14584B
Hex Schmitt Trigger
The MC14584B Hex Schmitt Trigger is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14584B
may be used in place of the MC14069UB hex inverter for enhanced
noise immunity to “square up” slowly changing waveforms.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load over the Rated Temperature Range
• Double Diode Protection on All Inputs
• Can Be Used to Replace MC14069UB
• For Greater Hysteresis, Use MC14106B which is Pin−for−Pin
Replacement for CD40106B and MM74Cl4
• Pb−Free Packages are Available
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14
PDIP−14
P SUFFIX
CASE 646
1
14
SOIC−14
D SUFFIX
CASE 751A
1
MARKING
DIAGRAMS
MC14584BCP
AWLYYWWG
14584BG
AWLYWW
MAXIMUM RATINGS (Voltages Referenced to V
Symbol Parameter Value Unit
V
Vin, V
Iin, I
P
T
T
T
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and V
to the range VSS v (Vin or V
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
DC Supply Voltage Range −0.5 to +18.0 V
DD
Input or Output Voltage Range
out
(DC or Transient)
Input or Output Current
out
D
A
stg
L
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range −55 to +125 °C
Storage Temperature Range −65 to +150 °C
Lead Temperature
(8−Second Soldering)
) v VDD.
out
)
SS
−0.5 to VDD + 0.5 V
± 10 mA
500 mW
260 °C
should be constrained
out
14
TSSOP−14
DT SUFFIX
CASE 948G
14
SOEIAJ−14
F SUFFIX
CASE 965
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
14
584B
ALYWG
G
1
MC14584B
ALYWG
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 7
1 Publication Order Number:
MC14584B/D
Page 2
MC14584B
PIN ASSIGNMENT
1
IN 1
IN 2
IN 3
V
2
3
4
6
7
SS
OUT 1
OUT 2
OUT 3
14
V
DD
13
IN 6
12
OUT 6
11
IN 5
105
OUT 5
9
IN 4
8
OUT 4
EQIVALENT CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
LOGIC DIAGRAM
1
3
5
9
11
13
VDD = PIN 14
VSS = PIN 7
2
4
6
8
10
12
ORDERING INFORMATION
Device Package Shipping
MC14584BCP PDIP−14
MC14584BCPG PDIP−14
(Pb−Free)
MC14584BD SOIC−14
MC14584BDG SOIC−14
(Pb−Free)
MC14584BDR2 SOIC−14
MC14584BDR2G SOIC−14
(Pb−Free)
MC14584BDTR2 TSSOP−14*
MC14584BDTR2G TSSOP−14*
MC14584BF SOEIAJ−14
MC14584BFG SOEIAJ−14
(Pb−Free)
MC14584BFEL SOEIAJ−14
MC14584BFELG SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
25 Units / Rail
55 Units / Rail
2500 / Tape & Reel
50 Units / Rail
2000 / Tape & Reel
†
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2
Page 3
MC14584B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
V
DD
Characteristic Symbol
Output Voltage “0” Level
= V
V
in
DD
Vin = 0 “1” Level V
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Input Current I
Input Capacitance
Vdc
V
OL
5.0
10
15
OH
5.0
10
15
I
OH
5.0
5.0
10
15
I
OL
5.0
10
15
in
C
in
15 − ± 0.1 − ±0.00001 ±0.1 − ± 1.0
Min Max Min Typ
4.95
9.95
14.95
– 3.0
– 0.64
– 1.6
– 4.2
0.64
1.6
4.2
− − − − 5.0 7.5 − − pF
)
SS
− 55_C 25_C 125_C
(2)
Max Min Max
−
0.05
−
0.05
−
0.05
−
−
−
−
−
−
−
−
−
−
−
−
−
4.95
9.95
14.95
– 2.4
– 0.51
– 1.3
– 3.4
0.51
1.3
3.4
0
0
0
5.0
10
15
– 4.2
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
0.05
0.05
0.05
−
−
−
−
−
−
−
−
−
−
−
−
−
4.95
9.95
14.95
– 1.7
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
0.05
0.05
0.05
−
−
−
−
−
−
−
−
−
−
(Vin = 0)
Quiescent Current
(Per Package)
Total Supply Current
(3) (4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
I
DD
I
T
5.0
10
15
5.0
10
15
−
0.25
−
−
0.5
1.0
−
0.0005
−
0.0010
−
0.0015
IT = (1.8 mA/kHz) f + I
IT = (3.6 mA/kHz) f + I
IT = (5.4 mA/kHz) f + I
0.25
0.5
1.0
DD
DD
DD
−
−
−
7.5
15
30
buffers switching)
Hysteresis Voltage VH
Threshold Voltage
Positive−Going
Negative−Going V
(5)
5.0
10
15
V
T+
5.0
10
15
T–
5.0
10
15
0.27
0.36
0.77
1.9
3.4
5.2
1.6
3.0
4.5
1.0
1.3
1.7
3.5
7.0
10.6
3.3
6.7
9.7
0.25
0.3
0.6
1.8
3.3
5.2
1.6
3.0
4.6
0.6
0.7
1.1
2.7
5.3
8.0
2.1
4.6
6.9
1.0
1.2
1.5
3.4
6.9
10.5
3.2
6.7
9.8
0.21
0.25
0.50
1.7
3.2
5.2
1.5
3.0
4.7
1.0
1.2
1.4
3.4
6.9
10.5
3.2
6.7
9.9
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
5. VH = VT+ – VT– (But maximum variation of VH is specified as less than V
T + max
– V
T – min
).
Unit
Vdc
Vdc
mAdc
mAdc
mAdc
mAdc
mAdc
Vdc
Vdc
Vdc
SWITCHING CHARACTERISTICS (C
= 50 pF, T
L
Characteristic Symbol
Output Rise Time t
Output Fall Time t
Propagation Delay Time t
= 25_C)
A
PLH
TLH
THL
, t
PHL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
Min Typ
−
−
−
−
−
−
−
−
−
100
50
40
100
50
40
125
50
40
(6)
Max Unit
200
100
80
200
100
80
250
100
80
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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3
ns
ns
ns
Page 4
MC14584B
V
DD
14
VSS7
OUTPUT
C
L
PULSE
GENERATOR
INPUT
Figure 1. Switching Time Test Circuit and Waveforms
V
in
V
H
V
in
V
out
V
DD
V
T+
V
T−
V
SS
V
DD
V
SS
(a) Schmitt Triggers will square up inputs with slow
rise and fall times.
Figure 2. Typical Schmitt Trigger Applications
20 ns 20 ns
V
t
PLH
DD
V
SS
V
OH
V
OL
V
DD
V
T+
V
T−
V
SS
V
DD
V
SS
INPUT
t
PHL
OUTPUT
V
out
V
H
V
in
V
out
90%
50%
10%
t
f
90%
50%
10%
t
r
(b) A Schmitt trigger offers maximum noise immunity
in gate applications.
V
DD
, OUTPUT VOLTAGE (Vdc)
out
V
0
0
V
V
T+
T−
V
H
Vin, INPUT VOLTAGE (Vdc)
Figure 3. Typical Transfer Characteristics
V
DD
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4
Page 5
−T−
SEATING
PLANE
14 8
17
N
HG
MC14584B
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B
A
F
L
C
D
14 PL
0.13 (0.005)
K
J
M
M
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L
0.290 0.310 7.37 7.87
M −−− 10 −−− 10
N 0.015 0.039 0.38 1.01
MILLIMETERSINCHES
__
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5
Page 6
−T−
SEATING
PLANE
MC14584B
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−A−
14
1
8
−B−
7
P 7 PL
0.25 (0.010) B
M
M
G
F
J
D 14 PL
0.25 (0.010) A
M
T
R X 45
C
K
S
B
S
_
M
SOLDERING FOOTPRINT*
7X
7.04
1
14X
0.58
14X
1.52
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
__ __
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
INCHESMILLIMETERS
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
Page 7
MC14584B
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
0.10 (0.004)
−T−
SEATING
PLANE
14X REFK
S
U
T
S
N
0.25 (0.010)
U0.15 (0.006) T
S
2X L/2
0.10 (0.004) V
14
M
8
M
L
PIN 1
IDENT.
1
S
U0.15 (0.006) T
A
−V−
B
N
−U−
F
7
DETAIL E
K
K1
J
J1
SECTION N−N
C
D
G
H
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
−W−
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
M 0 8 0 8
____
INCHESMILLIMETERS
SOLDERING FOOTPRINT*
7.06
1
14X
0.36
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
14X
1.26
DIMENSIONS: MILLIMETERS
0.65
PITCH
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7
Page 8
14 8
1
Z
D
e
b
0.13 (0.005)
M
E
7
A
0.10 (0.004)
H
A
1
MC14584B
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE A
L
E
E
VIEW P
_
M
L
DETAIL P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q
1
c
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
DIM MIN MAX MIN MAX
−−− 2.05 −−− 0.081
A
A
0.05 0.20 0.002 0.008
1
0.35 0.50 0.014 0.020
b
0.10 0.20 0.004 0.008
c
9.90 10.50 0.390 0.413
D
5.10 5.45 0.201 0.215
E
1.27 BSC 0.050 BSC
e
H
7.40 8.20 0.291 0.323
E
0.50 0.85 0.020 0.033
0.50
L
1.10 1.50 0.043 0.059
E
0
M
_
Q
0.70 0.90 0.028 0.035
1
−−− 1.42 −−− 0.056
Z
INCHES
10
_
10
0
_
_
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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MC14584B/D
8
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