Datasheet MC14584BCL, MC14584BCP, MC14584BD Datasheet (Motorola)

Page 1
MOTOROLA CMOS LOGIC DATA
1
MC14584B
  
The MC14584B Hex Schmitt Trigger is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. These devices find primary use where low power dissipation and/or high noise immunity is desired. The MC14584B may be used in place of the MC14069UB hex inverter for enhanced noise immunity to “square up” slowly changing waveforms.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range
Double Diode Protection on All Inputs
Can Be Used to Replace MC14069UB
For Greater Hysteresis, Use MC14106B which is Pin–for–Pin
Replacement for CD40106B and MM74Cl4
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 18.0 V
Vin, V
out
Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current (DC or Transient), per Pin
± 10 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
EQIVALENT CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and V
out
should be constrained to the range VSS (Vin or V
out
) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3 1/94

L SUFFIX
CERAMIC
CASE 632
ORDERING INFORMATION
MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
LOGIC DIAGRAM
13
11
9
5
3
1
12
10
8
6
4
2
VDD = PIN 14
VSS = PIN 7
Page 2
MOTOROLA CMOS LOGIC DATAMC14584B
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C 25_C 125_C
Characteristic
Symbol
V
DD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage “0” Level
Vin = V
DD
V
OL
5.0 10 15
— — —
0.05
0.05
0.05
— — —
0 0 0
0.05
0.05
0.05
— — —
0.05
0.05
0.05
Vdc
Vin = 0 “1” Level V
OH
5.0 10 15
4.95
9.95
14.95
— — —
4.95
9.95
14.95
5.0 10 15
— — —
4.95
9.95
14.95
— — —
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
I
OH
5.0
5.0 10 15
– 3.0
– 0.64
– 1.6 – 4.2
— — — —
– 2.4
– 0.51
– 1.3 – 3.4
– 4.2 – 0.88 – 2.25
– 8.8
— — — —
– 1.7
– 0.36
– 0.9 – 2.4
— — — —
mAdc
(VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)
I
OL
5.0 10 15
0.64
1.6
4.2
— — —
0.51
1.3
3.4
0.88
2.25
8.8
— — —
0.36
0.9
2.4
— — —
mAdc
Input Current I
in
15 ±0.1 ±0.00001 ±0.1 ±1.0 µAdc
Input Capacitance
(Vin = 0)
C
in
5.0 7.5 pF
Quiescent Current
(Per Package)
I
DD
5.0 10 15
— — —
0.25
0.5
1.0
— — —
0.0005
0.0010
0.0015
0.25
0.5
1.0
— — —
7.5 15 30
µAdc
Total Supply Current**†
(Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)
I
T
5.0 10 15
IT = (1.8 µA/kHz) f + I
DD
IT = (3.6 µA/kHz) f + I
DD
IT = (5.4 µA/kHz) f + I
DD
µAdc
Hysteresis Voltage VH‡ 5.0
10 15
0.27
0.36
0.77
1.0
1.3
1.7
0.25
0.3
0.6
0.6
0.7
1.1
1.0
1.2
1.5
0.21
0.25
0.50
1.0
1.2
1.4
Vdc
Threshold Voltage
Positive–Going
V
T+
5.0 10 15
1.9
3.4
5.2
3.5
7.0
10.6
1.8
3.3
5.2
2.7
5.3
8.0
3.4
6.9
10.5
1.7
3.2
5.2
3.4
6.9
10.5
Vdc
Negative–Going V
T–
5.0 10 15
1.6
3.0
4.5
3.3
6.7
9.7
1.6
3.0
4.6
2.1
4.6
6.9
3.2
6.7
9.8
1.5
3.0
4.7
3.2
6.7
9.9
Vdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. **āThe formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001. ‡VH = VT+ – VT– (But maximum variation of VH is specified as less than VT +
max
– VT –
min
).
Page 3
MOTOROLA CMOS LOGIC DATA
3
MC14584B
SWITCHING CHARACTERISTICS (C
L
= 50 pF, TA = 25_C)
Characteristic
Symbol
V
DD
Vdc
Min Typ # Max Unit
Output Rise Time t
TLH
5.0 10 15
— — —
100
50 40
200 100
80
ns
Output Fall Time t
THL
5.0 10 15
— — —
100
50 40
200 100
80
ns
Propagation Delay Time t
PLH
, t
PHL
5.0 10 15
— — —
125
50 40
250 100
80
ns
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Switching Time Test Circuit and Waveforms
PULSE
GENERATOR
V
DD
INPUT
C
L
VSS7
OUTPUT
20 ns 20 ns
V
DD
V
SS
V
OH
V
OL
90% 50% 10%
90% 50% 10%
t
PLH
t
PHL
OUTPUT
INPUT
t
f
t
r
V
DD
V
T+
V
T–
V
SS
V
DD
V
SS
V
out
V
in
V
H
V
H
V
DD
V
T+
V
T–
V
SS
V
DD
V
SS
V
out
V
in
V
DD
0
V
DD
V
T+
V
T–
0
V
H
Vin, INPUT VOLTAGE (Vdc)
V
out
, OUTPUT VOLTAGE (Vdc)
Figure 2. Typical Schmitt Trigger Applications
(b) A Schmitt trigger offers maximum noise immunity
in gate applications.
(a) Schmitt Triggers will square up inputs with slow
rise and fall times.
Figure 3. Typical Transfer Characteristics
PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
OUT 5
IN 5
OUT 6
IN 6
V
DD
OUT 4
IN 4
OUT 2
IN 2
OUT 1
IN 1
V
SS
OUT 3
IN 3
V
in
V
out
14
Page 4
MOTOROLA CMOS LOGIC DATAMC14584B
4
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.94 B 0.245 0.280 6.23 7.11 C 0.155 0.200 3.94 5.08 D 0.015 0.020 0.39 0.50 F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31 L 0.300 BSC 7.62 BSC M 0 15 0 15 N 0.020 0.040 0.51 1.01
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.
–A–
–B–
C
14 PLD
GF N
K
14 PLJ
M
L
S
B
M
0.25 (0.010) T
S
A
M
0.25 (0.010) T
–T–
SEATING PLANE
1 7
14 9
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
4. ROUNDED CORNERS OPTIONAL.
1 7
14 8
B
A
F
H G D
K
C
N
L
J
M
SEATING PLANE
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.715 0.770 18.16 19.56 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L 0.300 BSC 7.62 BSC M 0 10 0 10 N 0.015 0.039 0.39 1.01
_ _ _ _
Page 5
MOTOROLA CMOS LOGIC DATA
5
MC14584B
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P
7 PL
14 8
71
M
0.25 (0.010) B
M
S
B
M
0.25 (0.010) A
S
T
–T–
F
R
X 45
SEATING PLANE
D 14 PL
K
C
J
M
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019
_ _ _ _
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MC14584B/D
*MC14584B/D*
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