Page 1
MOTOROLA CMOS LOGIC DATA
1
MC14583B
The MC14583B is a dual Schmitt trigger constructed with complementary
P–channel and N–channel MOS devices on a monolithic silicon substrate.
Each Schmitt trigger is functionally independent except for a common
3–state input and an internally–connected Exclusive OR output for use in
line receiver applications. Trigger levels are adjustable through the positive,
negative, and common t erminals with the u se of external resistors.
Applications include the speed–up of a slow waveform edge in interface
receivers, level detectors, etc.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Single Supply Operation
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Resistor Adjustable Trigger Levels
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 18.0 V
Vin, V
out
Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current (DC or Transient),
per Pin
± 10 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
LOGIC DIAGRAM
POSITIVE A
6 5
NEGATIVE A
7 COMMON A
B
out
9A
in
12
B
out
10
EXCLUSIVE OR14
A
out
11
A
out
4
13
15B
in
POSITIVE B
2
2 3
NEGATIVE B
1 COMMON B
3–STATE
OUTPUT DISABLE
VDD = PIN 16
VSS = PIN 8
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
BLOCK DIAGRAM
TRUTH TABLE
Inputs Outputs
A B Dis
A
out
A
outBoutBout
ę
0 0 0 0 Z 0 Z 0
0 0 1 0 1 0 1 0
0 1 0 0 Z 1 Z 1
0 1 1 0 1 1 0 1
1 0 0 1 Z 0 Z 1
1 0 1 1 0 0 1 1
1 1 0 1 Z 1 Z 0
1 1 1 1 0 1 0 0
Z = High impedance at output
VDD = PIN 16
VSS = PIN 8
9
13
15
12
10
14
11
4
A
PosANegACom
B
PosBNegBCom
A
in
B
in
D
is
B
out
B
out
A
out
A
out
6 5 7
2 3 1
Page 2
MOTOROLA CMOS LOGIC DATAMC14583B
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C 25_C 125_C
Characteristic
Symbol
V
DD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage “0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 1.2
– 0.25
– 1.62
– 1.8
—
—
—
—
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current I
in
15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
Input Capacitance
(Vin = 0)
C
in
— — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (1.33 µA/kHz) f + I
DD
IT = (2.65 µA/kHz) f + I
DD
IT = (3.98 µA/kHz) f + I
DD
µAdc
Three–State Leakage Current I
TL
15 — ±0.1 — ±0.0001 ±0.1 — ±3.0 µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
V
out
should be constrained to the range VSS ≤ (Vin or V
out
) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
B
out
DIS
B
in
V
DD
A
in
B
out
A
out
A
out
B
Neg
B
Pos
B
Com
V
SS
A
Com
A
Pos
A
Neg
Page 3
MOTOROLA CMOS LOGIC DATA
3
MC14583B
SWITCHING CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C)
Characteristic
Symbol V
DD
Min Typ # Max Unit
Output Rise Time
t
TLH
= (3.0 ns/pF) CL + 30 ns
t
TLH
= (1.5 ns/pF) CL + 15 ns
t
TLH
= (1.1 ns/pF) CL + 10 ns
t
TLH
5.0
10
15
—
—
—
180
90
65
360
180
130
ns
Output Fall Time
t
THL
= (1.5 ns/pF) CL + 25 ns
t
THL
= (0.75 ns/pF) CL + 12.5 ns
t
THL
= (0.55 ns/pF) CL + 9.5 ns
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Ain, Bin to A
out
, B
out
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 565 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 197 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 125 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
650
230
150
1300
460
300
ns
Ain, Bin to A
out
, B
out
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 1015 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 347 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 235 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
1100
380
260
2200
760
520
ns
Ain, Bin to Exclusive OR
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 665 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 257 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 145 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
750
280
170
1500
560
340
ns
3–State Enable, Disable Delay Time (see figure 5)
ton, t
off
= (1.7 ns/pF) CL + 140 ns
ton, t
off
= (0.66 ns/pF) CL + 57 ns
ton, t
off
= (0.5 ns/pF) CL + 30 ns
ton,
t
off
5.0
10
15
—
—
—
225
90
55
450
180
110
ns
Positive Threshold Voltage
(R1, R2 = 5.0 kΩ)
V
T+
5.0
10
15
—
—
—
3.30
5.70
8.20
—
—
—
Vdc
Negative Threshold Voltage
(R1, R2 = 5.0 kΩ)
V
T–
5.0
10
15
—
—
—
1.70
4.30
6.80
—
—
—
Vdc
Hysteresis Voltage
(R1, R2 = 5.0 kΩ)
V
H
5.0
10
15
0.85
0.70
0.70
1.70
1.40
1.40
3.40
2.80
2.80
Vdc
Threshold Voltage Variation, A to B
(R1, R2 = 5.0 kΩ)
∆V
T
5.0
10
15
—
—
—
0.1
0.15
0.20
—
—
—
Vdc
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Page 4
MOTOROLA CMOS LOGIC DATAMC14583B
4
Figure 1. Typical Output Source and Sink Characteristics Test Circuit
NJ
V
DD
V
out
V
DD
V
SS
SW1
SW2
V
SS
I
O
EXTERNAL
POWER
SUPPLY
A
in
DIS
B
in
A
out
A
out
B
out
B
out
Output Source
Characteristics
Output Sink
Characteristics
Test
Value
VGS = – V
DD
VDS = V
out
– V
DD
NJ
Test
Value
VGS = V
DD
VDS = V
out
Output
Under Test
Switch Position Switch Position
SW1 SW2 SW1 SW2
1A
out
, B
out
1 2 2
2A
out
, B
out
2 1 1
1Exclusive OR 2 1 1
1
2
2
1
Figure 2. Power Dissipation Test Circuit and Waveforms
PULSE
GENERATOR 1
AinA
out
PULSE
GENERATOR 2
DIS
B
in
A
out
B
out
B
out
V
DD
V
SS
0.01
µ
F
CERAMIC
500 µF
C
L
C
L
C
L
C
L
C
L
f
out
, A
in
f
out
, B
in
I
D
Figure 3. Typical Threshold Points
POSITIVE
COMMON
NEGATIVE
R1
R2
POSITIVE
COMMON
NEGATIVE
R1
A — Feedback scheme for independent threshold adjustment:
B — Feedback scheme for hysteresis adjustment:
80
70
60
50
40
30
20
10
1.0 M100 k10 k1.0 k10010 20 40
6 8
R1, R2, RESISTANCE (OHMS)
TYPICAL THRESHOLD POINT (%V
DD
)
VDD = 5.0 V
VDD = 10 V
VDD = 15 V
VSS = 0
Page 5
MOTOROLA CMOS LOGIC DATA
5
MC14583B
Figure 4. Switching Time Test Circuit and Waveforms
PULSE
GENERATOR 1
PULSE
GENERATOR 3
PULSE
GENERATOR 2
AinA
out
DIS
B
in
A
out
B
out
B
out
V
DD
C
L
V
SS
CLCLCLC
L
50%
t
PLH
50%
50%
50%
90%
10%
90%
10%
50%
90%
10%
50%
50%
90%
10%
t
f
t
r
t
PHL
t
PHL
t
PLH
t
PHL
t
PLH
t
f
t
off
t
on
t
PLH
t
PHL
t
r
t
on
t
off
t
f
t
r
t
PHL
t
PLH
t
PHL
t
PLH
t
f
t
r
A
in
B
in
3–STATE
DISABLE
A
out
B
out
A
out
B
out
EXCLUSIVE
OR
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
NOTE: Dashed lines indicate high output resistance
INPUT = tr = tf = 20 ns
t
r
t
f
Page 6
MOTOROLA CMOS LOGIC DATAMC14583B
6
Figure 5. 3–State Switching Time Test Circuit and Waveforms
VOL′ and VOH′ refer to the levels present as a result of the 1 k ohm load resistors.
*Metal film, ± 1%, 1/4 W or greater
CL = 15 pF, which includes test circuit capacitance.
Test Switch Position
ton HL 1
ton LH 2
t
off
HL 2
t
off
LH 1
PULSE
GENERATOR 1
PULSE
GENERATOR 2
V
DD
V
DD
V
SS
A
in
DIS
B
in
A
out
A
out
B
out
B
out
C
L
1 k*
1 k*
1
2
SW
A
in
B
in
3–STATE
DISABLE
A
out
B
out
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
V
OH
V
OL
50%
ton LH
t
off
LH
t
off
LH
10%
t
off
HL
V
OL
ton LH
10%
90%
VOH′
VOH′
90% V
OH
t
off
LH
VOL′
10% (VOH – VOL′
)
VOL′
10% (VOH – VOL′
)
90%
90%
V
OH
ton HL
V
OH
′
SWITCH POSITION 2 SWITCH POSITION 1
Page 7
MOTOROLA CMOS LOGIC DATA
7
MC14583B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
F
E
G
N
K
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
Page 8
MOTOROLA CMOS LOGIC DATAMC14583B
8
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
_ _ _ _
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MC14583B/D
*MC14583B/D*
◊
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