Page 1
MOTOROLA CMOS LOGIC DATA
1
MC14582B
The M C14582B is a C MOS look–ahead carry g enerator c apable of
anticipating a carry across four binary adders or groups of adders. The
device is cascadable to perform full look–ahead across n–bit adders. Carry,
generate–carry, and propagate–carry functions are provided as enumerated
in the pin designation table shown below.
• Expandable to any Number of Bits
• All Buffered Outputs
• Low Power Dissipation
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–Power
Schottky TTL Load over the Rated Temperature Range
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 18.0 V
Vin, V
out
Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current (DC or Transient),
per Pin
± 10 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
LOGIC EQUATIONS
C
n+x
= G0 + (P0 Cn)
C
n+y
= G1
+ (P1 G0) + (P1 P0 Cn)
C
n+z
= G2
+ (P2 G1) + (P2 P1 G0) + (P2 P1 P0 Cn)
G
= G3 + (P3 G2) + (P3 P2 G1) + (P1 P2 P3 G0)
P
= P3 P2 P1 P0
PIN DESIGNATIONS
Designation Pin No’s Function
G0, G1, G2, G3 3, 1, 14, 5 Active–Low
Carry–Generate Inputs
P0, P1, P2, P3 4, 2, 15, 6 Active–Low
Carry–Propagate Inputs
C
n
13 Carry Input
C
n+x
, C
n+y
C
n+z
12, 11, 9 Carry Outputs
G 10 Active–Low Group
Carry–Generate Output
P 7 Active–Low Group
Carry–Propagate Output
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
C
n+x
C
in
G
2
P
2
V
DD
C
n+z
G
C
n+y
P
0
G
0
P
1
G
1
V
SS
P
P3
G
3
Page 2
MOTOROLA CMOS LOGIC DATAMC14582B
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS)
V
DD
– 55_C 25_C 125_C
Characteristic
Symbol
DD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage “0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current I
in
15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
Input Capacitance
(Vin = 0)
C
in
— — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (1.4 µA/kHz) f + I
DD
IT = (2.8 µA/kHz) f + I
DD
IT = (4.3 µA/kHz) f + I
DD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**āThe formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and V
out
should be constrained to the range VSS ≤ (Vin or V
out
) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
Page 3
MOTOROLA CMOS LOGIC DATA
3
MC14582B
SWITCHING CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C)
Characteristic
Symbol V
DD
Min Typ # Max Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) CL + 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) CL + 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) CL + 9.5 ns
t
TLH
,
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 260 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 107 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 85 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
345
140
110
690
280
220
ns
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Dynamic Power Dissipation
Test Circuit and Waveform
20 ns
V
in
V
DD
V
SS
10%
90%
50%
20 ns
VARIABLE
WIDTH
V
in
C
in
C
L
V
DD
G0
G1
G2
G3
P0
P1
P2
P3
C
L
C
L
C
L
C
L
C
n+x
C
n+y
C
n+z
P
G
PULSE
GENERATOR
Figure 2. Source Current Test Circuit Figure 3. Sink Current Test Circuit
C
in
V
DD
G0
G1
G2
G3
P0
P1
P2
P3
C
n+x
C
n+y
C
n+z
P
G
C
in
V
DD
G0
G1
G2
G3
P0
P1
P2
P3
Cn +
x
Cn +
y
Cn +
z
P
G
V
SS
8
EXTERNAL
POWER
SUPPLY
V
SS
8
EXTERNAL
POWER
SUPPLY
16 16
I
OH
I
OL
V
out
= V
OH
V
out
= V
OL
Page 4
MOTOROLA CMOS LOGIC DATAMC14582B
4
Figure 4. Switching Time Test Circuit and Waveforms
AC Paths DC Data
Input Output To V
SS
To V
DD
P
0 P Remaining G’s
P
’s, C
n
G
0 G P’s, CnRemaining
G
’s
CnC
n+x
, C
n+y
, P’s G’s
C
n+z
TEST TABLE
V
out
C
in
C
L
V
DD
G0
G1
G2
G3
P0
P1
P2
P3
C
n+x
C
n+y
C
n+z
P
G
PULSE
GENERATOR
V
SS
SEE
TEST
TABLE
20 ns
V
in
V
DD
V
SS
10%
90%
50%
20 ns
V
OH
V
OL
V
out
t
PLH
t
PHL
t
TLH
t
THL
TYPICAL APPLICATIONS
CnC
n+4
CnC
n+4
CnC
n+4
CnC
n+4
C
n
C
n
C
n
C
n
C
n+4
G P G P G P G P
G0 P0 C
n+x
G1 P1 C
n+y
G2 P2 C
n+z
G3 P3
G P
C
n
MC14582B
MC14581B
MC14581B
16–BIT ALU, TWO LEVEL LOOK–AHEAD
16–BIT ALU, RIPPLE CARRY
C
n
C
n
C
n
C
n
C
n+4
G P G P G P G P
G0 P0 C
n+x
G1 P1 C
n+y
G2 P2 C
n+z
G3 P3
G P
C
n
MC14582B
C
n
C
n
C
n
C
n
C
n+4
G P G P G P G P
G0 P0 C
n+x
G1 P1 C
n+y
G2 P2 C
n+z
G3 P3
G P
C
n
MC14582B
32–BIT ALU, TWO LEVEL LOOK–AHEAD OVER 16–BIT GROUPS
MC14581B
C
n
C
n
C
n
C
n
C
n+4
G P G P G P G P
G0 P0 C
n+x
G1 P1 C
n+y
G2 P2 C
n+z
G3 P3
G P
C
n
MC14582B
C
n
C
n
C
n
G P G P
G0 P0 C
n+x
G1 P1 C
n+y
C
n
MC14582B
COMBINED TWO–LEVEL LOOK–AHEAD AND RIPPLE CARRY ALU
MC14581B
C
n+4
C
n
C
n
C
n
C
n
G P G P G P G P
G0 P0 C
n+x
G1 P1 C
n+y
G2 P2 C
n+z
G3 P3
G P
C
n
MC14582B
C
n
C
n
C
n
C
n
C
n+4
G P G P G P G P
G0 P0 C
n+x
G1 P1 C
n+y
G2 P2 C
n+z
G3 P3
G P
C
n
MC14582B
64–BIT ALU, FULL–CARRY LOOK–AHEAD IN THREE LEVELS.
MC14581B
CnC
n+4
C
n+4
G0 P0 C
n+x
C
n
MC14582B
G0 P0 C
n+x
G1 P1 C
n+y
C
n
MC14582B
A AND B INPUTS AND F OUTPUTS ARE NOT SHOWN (MC14581B).
C
n
G P
Page 5
MOTOROLA CMOS LOGIC DATA
5
MC14582B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
F
E
G
N
K
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
Page 6
MOTOROLA CMOS LOGIC DATAMC14582B
6
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
_ _ _ _
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
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MC14582B/D
*MC14582B/D*
◊
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