Page 1
MOTOROLA CMOS LOGIC DATA
1
MC14580B
The MC14580B is a 4 by 4 multiport register useful in small scratch pad
memories, arithmetic operations when coupled with an adder, and other data
storage applications. It allows independent reading of any two words (or the
same word at both outputs) while writing into any one of four words.
Address changing and data entry occur on the rising edge of the clock.
When t he write enable input is low, the contents of any word may b e
accessed but not altered.
• No Restrictions on Clock Input Rise or Fall Times
• 3–State Outputs
• Single Phase Clocking
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or one Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin Compatible with CD40108
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 18.0 V
Vin, V
out
Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current (DC or Transient),
per Pin
± 10 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
BLOCK DIAGRAM
CLOCK
16
15
20
191719
18
DATA
INPUT
WE
R1
B
R0
B
R1
AR0A
W1W0
1011141398
DECODER
3–STATE A
3
4
5
6
7
22
23
2
1
21
3–STATE B
4 X 4
MEMORY
VDD = PIN 24
VSS = PIN 12
D0
D1
D2
D3
Q0
A
Q1
A
Q2
A
Q3
A
Q0
B
Q1
B
Q2
B
Q3
B
WORD A
OUTPUT
WORD B
OUTPUT
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 623
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBDW SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
PIN ASSIGNMENT
Q2
A
Q0
A
3–STATE A
Q2
B
Q3
B
WRITE 0
Q3
A
Q1
A
D0
3–STATE B
Q0
B
Q1
B
V
DD
WE
CLOCK
D3
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
13
11
12
21
22
23
24
READ 0
A
READ 1
A
D2
D1
READ 0
B
V
SS
READ 1
B
WRITE 1
Page 2
MOTOROLA CMOS LOGIC DATAMC14580B
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C 25_C 125_C
Characteristic
Symbol
V
DD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage “0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current I
in
15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
Input Capacitance
(Vin = 0)
C
in
— — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.010
0.020
0.030
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (1.18 µA/kHz) f + I
DD
IT = (1.91 µA/kHz) f + I
DD
IT = (2.67 µA/kHz) f + I
DD
µAdc
Three–State Leakage Current I
TL
15 — ±0.1 — ±0.0001 ±0.1 — ±3.0 µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and V
out
should be constrained to the range VSS ≤ (Vin or V
out
) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
Page 3
MOTOROLA CMOS LOGIC DATA
3
MC14580B
SWITCHING CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C)
Characteristic
Symbol V
DD
Min Typ # Max Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) CL + 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) CL + 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) CL + 9.5 ns
t
TLH
, t
THL
(Figures 3 and 6)
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Output
t
PLH
, t
PHL
(Figures 3 and 6)
5.0
10
15
—
—
—
650
250
170
1300
500
340
ns
Write Enable Setup Time
(Enabling a Write or Read)
t
su
(Figure 5)
5.0
10
15
800
300
200
400
150
100
—
—
—
ns
Write Enable Removal Time
(Disabling a Write or Read)
t
rem
(Figure 5)
5.0
10
15
0
0
0
– 100
– 50
– 35
—
—
—
ns
Setup Time**
Address, Data to Clock
t
su
(Figure 3)
5.0
10
15
50
30
25
20
0
0
—
—
—
ns
Hold Time**
Clock to Address, Data
t
h
(Figure 3)
5.0
10
15
480
195
150
160
65
50
—
—
—
ns
3–State Enable/Disable Delay Time t
PHZ
, t
PLZ
t
PZH
, t
PZL
(Figures 4 and 7)
5.0
10
15
—
—
—
130
60
45
260
120
90
ns
Clock Pulse Width t
w
(Figure 3)
5.0
10
15
820
330
220
410
165
110
—
—
—
ns
**When loading repetitive highs, the output may glitch low momentarily after the rising edge of Clock. However, data integrity remains unaffected
and data is valid after the propagation delays listed in the Switching Characteristics Table.
Figure 1. Output Drive Current Test Circuit
Sink Current Source Current
Position of S1 2 1
VGS = V
DD
– V
DD
VDS = V
out
V
out
– V
DD
EXTERNAL
POWER
SUPPLY
V
out
I
DS
V
DD
V
SS
PULSE
GENERATOR
V
DD
V
SS
S1
1
2
WE
W0
W1
R0
A
R1
A
R0
B
R1
B
C
D0
D1
D2
D3
Q0
A
Q1
A
Q2
A
Q3
A
Q0
B
Q1
B
Q2
B
Q3
B
Page 4
MOTOROLA CMOS LOGIC DATAMC14580B
4
Figure 2. Power Dissipation Test Circuit and Waveforms (3–State Inputs are High)
PULSE
GENERATOR
1
PULSE
GENERATOR
2
PULSE
GENERATOR
3
V
DD
I
DD
WE
W0
W1
R0
A
R1
A
R0
B
R1
B
C
D0
D1
D2
D3
Q0
A
Q1
A
Q2
A
Q3
A
Q0
B
Q1
B
Q2
B
Q3
B
V
SS
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
REPETITIVE WAVEFORMS
P.G. 1
P.G. 2
P.G. 3
OUTPUT
Qn A, B
Figure 3. Figure 4.
CLOCK
ADDRESS DATA
Q
tw(H)
tw(L)
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
50%
t
su
t
h
50%
t
PLH
, t
PHL
t
TLH
, t
THL
50%
90%
10%
3–STATE
A OR B
V
DD
V
SS
V
OH
V
OL
V
OH
V
OL
Q
A
Q
B
t
PHZ
90%
50% 50%
10%
90%
10%
t
PZL
t
PZH
t
PZL
CLOCK
WE
t
su
t
rem
50%
50%
50% 50%
V
DD
V
SS
V
DD
V
SS
DEVICE
UNDER
TEST
Q
C
L
DEVICE
UNDER
TEST
Q
C
L
1 k
Ω
CONNECT TO VCC WHEN TESTING t
PLZ
AND t
PZL
CONNECT TO GND WHEN TESTING t
PHZ
AND t
PZH
Figure 5. Figure 6. Test Circuit
Figure 7. Test Circuit
Page 5
MOTOROLA CMOS LOGIC DATA
5
MC14580B
LOGIC DIAGRAM
16
15
17
18
19
20
9
8
W0
W1
D0
D1
D2
D3
WE
CLOCK
R0
A
13
C
D Q
C
D
Q
C
D
Q
C
D
Q
C
D Q
Q
C
D
Q
Q
R0
B
11
3–STATE A
3
R1
A
14
R1
B
10
C
D
Q
Q C
D Q
Q C
D
Q
Q C
D
Q
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
C
D
3–STATE
Q
21
3–STATE B
7
6
5
4
1
2
23
22
Q3
A
Q2
A
Q1
A
Q0
A
Q3
B
Q2
B
Q1
B
Q0
B
TRUTH TABLE
Clock WE Write 1 Write 0 Read 1ARead 0ARead 1BRead 0B3–State A 3–State B D
n
QnA QnB
1 0 1 0 1 0 1 1 1 1 1 1
1 0 1 0 1 0 1 1 1 0 0 0
X X X X X X X 1 1 X No
ChangeNoChange
X X X X X X X X 0 0 X Z Z
0 X X X X X X X 1 1 X No
ChangeNoChange
1 X X X X X X X 1 1 X No
ChangeNoChange
1 0 0 0 1 1 0 1 1 Dn to
word 0
Contents
of word 1
displayed
Contents
of word 2
displayed
0 0 0 0 1 1 0 1 1 Word 0
not
altered
Contents
of word 1
displayed
Contents
of word 2
displayed
Z = High Impedance
X = Don’t Care
Page 6
MOTOROLA CMOS LOGIC DATAMC14580B
6
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 709–02
ISSUE C
L SUFFIX
CERAMIC DIP PACKAGE
CASE 623–05
ISSUE M
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 31.37 32.13 1.235 1.265
B 13.72 14.22 0.540 0.560
C 3.94 5.08 0.155 0.200
D 0.36 0.56 0.014 0.022
F 1.02 1.52 0.040 0.060
G 2.54 BSC 0.100 BSC
H 1.65 2.03 0.065 0.080
J 0.20 0.38 0.008 0.015
K 2.92 3.43 0.115 0.135
L 15.24 BSC 0.600 BSC
M 0 15 0 15
N 0.51 1.02 0.020 0.040
_ _ _ _
1 12
1324
B
H
A
F
D
G
K
SEATING
PLANE
N
C
M
J
L
NOTES:
1. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (WHEN FORMED
PARALLEL).
1 12
24 13
B
A
SEATING
PLANE
F
D
G
K
N
C
M
J
L
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 31.24 32.77 1.230 1.290
B 12.70 15.49 0.500 0.610
C 4.06 5.59 0.160 0.220
D 0.41 0.51 0.016 0.020
F 1.27 1.52 0.050 0.060
G 2.54 BSC 0.100 BSC
J 0.20 0.30 0.008 0.012
K 3.18 4.06 0.125 0.160
L 15.24 BSC 0.600 BSC
M 0 15 0 15
N 0.51 1.27 0.020 0.050
_ _ _ _
Page 7
MOTOROLA CMOS LOGIC DATA
7
MC14580B
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
–A–
–B– P12X
D24X
12
1324
1
M
0.010 (0.25) B
M
S
A
M
0.010 (0.25) B
S
T
–T–
G
22X
SEATING
PLANE
K
C
R
X 45
_
M
F
J
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 15.25 15.54 0.601 0.612
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.41 0.90 0.016 0.035
G 1.27 BSC 0.050 BSC
J 0.23 0.32 0.009 0.013
K 0.13 0.29 0.005 0.011
M 0 8 0 8
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
____
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
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MC14580B/D
*MC14580B/D*
◊
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