Datasheet MC14572UBCP, MC14572UBD, MC14572UBDR2, MC14572UBF, MC14572UBFEL Datasheet (MOTOROLA)
Page 1
MC14572UB
Hex Gate
The MC14572UB hex functional gate is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. These complementary MOS logic gates find
primary use where low power dissipation and/or high noise immunity
is desired. The chip contains four inverters, one NOR gate and one
NAND gate.
• Diode Protection on All Inputs
• Single Supply Operation
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• NOR Input Pin Adjacent to V
• NAND Input Pin Adjacent to V
Inverter
• NOR Output Pin Adjacent to Inverter Input Pin For OR Application
• NAND Output Pin Adjacent to Inverter Input Pin For AND
Application
• Capable of Driving T wo Low–power TTL Loads or One Low–Power
Schottky TTL Load over the Rated T emperature Range
MAXIMUM RATINGS (Voltages Referenced to V
Symbol
V
DD
Vin, V
Iin, I
P
T
T
stg
T
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and V
to the range V
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
DC Supply Voltage Range –0.5 to +18.0 V
Input or Output Voltage Range
out
Input or Output Current
out
Power Dissipation,
D
Ambient Temperature Range –55 to +125 °C
A
Storage Temperature Range –65 to +150 °C
Lead Temperature
L
SS
or VDD). Unused outputs must be left open.
SS
Parameter Value Unit
(DC or Transient)
(DC or Transient) per Pin
per Package (Note 3.)
(8–Second Soldering)
v (Vin or V
out
Pin to Simplify Use As An Inverter
SS
Pin to Simplify Use As An
DD
) (Note 2.)
SS
–0.5 to VDD + 0.5 V
±10 mA
500 mW
260 °C
should be constrained
) v VDD.
out
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
SOIC–16
D SUFFIX
CASE 751B
SOEIAJ–16
F SUFFIX
CASE 966
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
MC14572UBCP
AWLYYWW
1
16
14572U
AWLYWW
1
16
MC14572UB
AWLYWW
1
ORDERING INFORMATION
Device Package Shipping
MC14572UBCP PDIP–16 2000/Box
MC14572UBD SOIC–16 48/Rail
MC14572UBDR2 SOIC–16 2500/Tape & Reel
MC14572UBF SOEIAJ–16 See Note 1.
MC14572UBFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev . 3
1 Publication Order Number:
MC14572UB/D
Page 2
MC14572UB
PIN ASSIGNMENT
OUT
1
A
IN
2
A
OUT
3
B
IN
4
B
OUT
C
IN 1
6
C
IN 2
7
C
V
8
SS
LOGIC DIAGRAM
V
16
DD
15
IN 2
F
IN 1
14
F
13
OUT
F
125
IN
E
OUT
11
10
E
IN
D
OUT
9
D
2
4
6
7
10
12
14
15
V
= PIN 16
DD
V
= PIN 8
SS
CIRCUIT SCHEMATIC
1
3
5
9
11
13
V
V
DD
7
2
1
6
V
SS
DD
14
5
V
DD
13
15
V
SS
V
SS
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2
Page 3
MC14572UB
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
V
DD
Characteristic Symbol
Output Voltage “0” Level
V
= VDD or 0
in
Vin = 0 or V
DD
“1” Level V
Input Voltage “0” Level
(V
= 4.5 or 0.5 Vdc)
O
(V
= 9.0 or 1.0 Vdc)
O
(V
= 13.5 or 1.5 Vdc)
O
“1” Level
(V
= 0.5 or 4.5 Vdc)
O
= 1.0 or 9.0 Vdc)
(V
O
(V
= 1.5 or 13.5 Vdc)
O
Output Drive Current
(V
= 2.5 Vdc) Source
OH
(V
= 4.6 Vdc)
OH
(V
= 9.5 Vdc)
OH
(V
= 13.5 Vdc)
OH
(VOL = 0.4 Vdc) Sink
(V
= 0.5 Vdc)
OL
= 1.5 Vdc)
(V
OL
Input Current I
Input Capacitance
(V
= 0)
in
Quiescent Current
(Per Package)
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
Per Package)
= 50 pF on all outputs, all
(C
L
V
OL
OH
V
V
I
OH
I
OL
in
C
I
DD
I
Vdc
5.0
10
15
5.0
10
15
IL
5.0
10
15
IH
5.0
10
15
5.0
5.0
10
15
5.0
10
15
Min Max Min Typ
—
—
—
4.95
9.95
14.95
—
—
—
4.0
8.0
12.5
– 1.2
– 0.25
– 0.62
– 1.8
0.64
1.6
4.2
15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
in
T
— — — — 5.0 7.5 — — pF
5.0
10
15
—
—
—
5.0
10
15
)
SS
– 55_C 25_C 125_C
(4.)
Max Min Max
0.05
0.05
0.05
—
—
—
1.0
2.0
2.5
—
—
—
—
—
—
—
—
—
—
0.25
0.5
1.0
—
—
—
4.95
9.95
14.95
—
—
—
4.0
8.0
12.5
– 1.0
– 0.2
– 0.5
– 1.5
0.51
1.3
3.4
—
—
—
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
– 1.7
– 0.36
– 0.9
– 3.5
0.88
2.25
8.8
0.0005
0.0010
0.0015
IT = (1.89 µA/kHz) f + I
IT = (3.80 µA/kHz) f + I
IT = (5.68 µA/kHz) f + I
0.05
0.05
0.05
—
—
—
1.0
2.0
2.5
—
—
—
—
—
—
—
—
—
—
0.25
0.5
1.0
DD
DD
DD
—
—
—
4.95
9.95
14.95
—
—
—
4.0
8.0
12.5
– 0.7
– 0.14
– 0.35
– 1.1
0.36
0.9
2.4
—
—
—
0.05
0.05
0.05
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
I
) = IT(50 pF) + (CL – 50) Vfk
T(CL
where: I
is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.006.
T
—
—
—
1.0
2.0
2.5
—
—
—
—
—
—
—
—
—
—
7.5
15
30
Unit
Vdc
Vdc
Vdc
Vdc
mAdc
mAdc
µAdc
µAdc
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Page 4
MC14572UB
SWITCHING CHARACTERISTICS
Characteristic
Output Rise Time
t
= (3.0 ns/pF) CL + 30 ns
TLH
= (1.5 ns/pF) CL + 15 ns
t
TLH
t
= (1.1 ns/pF) CL + 10 ns
TLH
Output Fall Time
t
= (1.5 ns/pF) CL + 25 ns
THL
= (0.75 ns/pF) CL + 12.5 ns
t
THL
= (0.55 ns/pF) CL + 9.5 ns
t
THL
Propagation Delay Time
t
, t
PLH
t
PLH
t
PLH
= (1.7 ns/pF) CL + 5 ns
PHL
, t
= (0.66 ns/pF) CL + 17 ns
PHL
, t
= (0.5 ns/pF) CL + 15 ns
PHL
(7.)
(C
L
= 50 pF, T
= 25_C)
A
Symbol V
t
TLH
t
THL
t
,
PLH
t
PHL
DD
5.0
10
15
5.0
10
15
5.0
10
15
Min Typ
—
180
—
—
—
100
—
—
—
—
—
90
65
50
40
90
50
40
(8.)
Max Unit
360
180
130
200
100
80
180
100
80
7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
PULSE
GENERATOR
INPUT
2
V
DD
16
8V
SS
C
1
L
OUTPUT
PULSE
GENERATOR
INPUT
7
V
6
8V
DD
16
5
C
SS
L
ns
ns
ns
OUTPUT
PULSE
GENERATOR
INPUT
15
V
DD
16
14
INPUT
20 ns 20 ns
90%
50%
10%
OUTPUT
13
V
8
SS
C
L
OUTPUT
90%
50%
Figure 1. Switching Time Test Circuits and Waveforms
t
PHL
10%
V
90%
50%
10%
t
PLH
90%
50%
10%
t
t
r
f
DD
V
SS
V
OH
V
OL
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Page 5
P ACKAGE DIMENSIONS
PLASTIC DIP PACKAGE
–A–
916
B
18
F
H
G
D
16 PL
0.25 (0.010) T
C
S
SEATING
–T–
PLANE
K
M
A
MC14572UB
PDIP–16
P SUFFIX
CASE 648–08
ISSUE R
J
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM MIN MAX MIN MAX
L
M
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
MILLIMETERSINCHES
____
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Page 6
–T–
–A–
16 9
–B–
18
G
K
C
SEATING
PLANE
D
16 PL
0.25 (0.010) A
M
S
B
T
S
MC14572UB
P ACKAGE DIMENSIONS
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
8 PLP
M
0.25 (0.010) B
M
S
X 45
R
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
DIM MIN MAX MIN MAX
F
J
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
____
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
INCHESMILLIMETERS
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Page 7
16 9
1
Z
D
e
b
0.13 (0.005)
M
8
H
E
E
A
A
1
0.10 (0.004)
MC14572UB
P ACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
L
E
M
_
L
DETAIL P
VIEW P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
Q
1
c
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
DIM MIN MAX MIN MAX
––– 2.05 ––– 0.081
A
A
0.05 0.20 0.002 0.008
1
0.35 0.50 0.014 0.020
b
0.18 0.27 0.007 0.011
c
9.90 10.50 0.390 0.413
D
5.10 5.45 0.201 0.215
E
1.27 BSC 0.050 BSC
e
H
7.40 8.20 0.291 0.323
E
0.50 0.85 0.020 0.033
L
L
1.10 1.50 0.043 0.059
E
0
M
_
Q
0.70 0.90 0.028 0.035
1
––– 0.78 ––– 0.031
Z
INCHES
10
_
10
0
_
_
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MC14572UB
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without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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MC14572UB/D
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