Page 1
MOTOROLA CMOS LOGIC DATA
1
MC14562B
The MC14562B is a 128–bit static shift register constructed with MOS
P–channel and N–channel enhancement mode d evices in a single
monolithic structure. Data is clocked in and out of the shift register on the
positive edge of the clock input. Data outputs are available every 16 bits,
from 16 through bit 128. This complementary MOS shift register is primarily
used where low power dissipation and/or high noise immunity is desired.
• Diode Protection on All Inputs
• Fully Static Operation
• Cascadable to Provide Longer Shift Register Lengths
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 18.0 V
Vin, V
out
Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current (DC or Transient),
per Pin
± 10 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
LOGIC DIAGRAM
DCQ1DCQ2DCQ3DCQ16DCQ17DCQ32DCQ33DCQ48DCQ49DCQ
64
CLOCK 5
DATA IN 12
DCQ65DCQ80DCQ81DCQ96DCQ97DCQ
112
DCQ
113
DCQ
128
10 Q16
13 Q32
9 Q48
1 Q64
8 Q80
2 Q96
6 Q112
3 Q128
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
BLOCK DIAGRAM
L SUFFIX
CERAMIC
CASE 632
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
10
13
9
1
8
2
6
3Q128
Q112
Q96
Q80
Q64
Q48
Q32
Q16
12
5
DATA
CLOCK
VDD = PIN 14
VSS = PIN 7
Pins 4 and 11
not used.
Page 2
MOTOROLA CMOS LOGIC DATAMC14562B
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C 25_C 125_C
Characteristic
Symbol
V
DD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage “0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(VO = 4.5 or 05 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current I
in
15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
Input Capacitance
(Vin = 0)
C
in
— — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.010
0.020
0.030
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (1.94 µA/kHz) f + I
DD
IT = (3.81 µA/kHz) f + I
DD
IT = (5.52 µA/kHz) f + I
DD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
V
out
should be constrained to the range VSS ≤ (Vin or V
out
) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
Q16
NC
DATA
Q32
V
DD
Q80
Q48
NC
Q128
Q96
Q64
V
SS
Q112
CLOCK
NC = NO CONNECTION
Page 3
MOTOROLA CMOS LOGIC DATA
3
MC14562B
SWITCHING CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C)
Characteristic
Symbol V
DD
Min Typ # Max Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) CL + 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) CL + 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) CL + 9.5 ns
t
TLH
,
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 515 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 217 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 145 ns
t
PLH
,
t
PHL
5.0
10
15
—
—
—
600
250
170
1200
500
340
ns
Clock Pulse Width
(50% Duty Cycle)
t
WH
5.0
10
15
600
220
150
300
110
75
—
—
—
ns
Clock Pulse Frequency f
cl
5.0
10
15
—
—
—
1.9
5.6
8.0
1.1
3.0
4.0
MHz
t
su(1)
5.0
10
15
– 20
– 10
0
– 170
– 64
– 60
—
—
—
ns
t
su(0)
5.0
10
15
– 20
– 10
0
– 91
– 58
– 48
—
—
—
ns
t
h(1)
5.0
10
15
350
165
155
263
109
100
—
—
—
ns
t
h(0)
5.0
10
15
350
200
140
267
140
93
—
—
—
ns
Clock Input Rise and Fall Times tr, t
f
5.0
10
15
—
—
—
—
—
—
15
5
4
µs
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Power Dissipation Test Circuit and Waveforms
V
DD
DATA
CLOCK
Q128
Q112
Q96
Q80
Q64
Q48
Q32
Q16
VSS7
I
D
500
µ
F
CLCLCLCLCLCLCLC
L
f
o
CLOCK
DATA
(f = 1/2 fo)
V
DD
V
SS
V
DD
V
SS
Data to Clock Setup Time
Data to Clock Hold Time
Page 4
MOTOROLA CMOS LOGIC DATAMC14562B
4
TIMING DIAGRAM
PULSE 1
PIN
NO.’S
CLOCK 5
DATA IN 12
Q16 10
Q32 13
Q28 3
PULSE 16 PULSE 32 PULSE 128
AC TEST WAVEFORMS
NOTE: The remaining Data–Bit Outputs (Q32, Q48, Q64, Q80, Q96, Q112 and Q128) will occur at Clock Pulse 32, 48, 64, 80,
96, 112, 128 in the same relationship as Q16.
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
CLOCK
DATA IN
Q16
CLOCK
DATA IN
Q16
PULSE 1 PULSE 2 PULSE 16 PULSE 17
50% 50% 50%
90%
10%
50%
t
WH
t
WL
t
r
t
f
50%
50%
t
su(0)
t
h(0)
50%
90%
10%
t
PHL
t
THL
PULSE 1 PULSE 2 PULSE 16 PULSE 17
50% 50% 50%
t
WH
t
WL
50%
50% 50%
t
su(1)
t
h(1)
50%
90%
10%
t
THL
t
PLH
Page 5
MOTOROLA CMOS LOGIC DATA
5
MC14562B
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
C 0.155 0.200 3.94 5.08
D 0.015 0.020 0.39 0.50
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
____
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
C
14 PLD
GF N
K
14 PLJ
M
L
S
B
M
0.25 (0.010) T
S
A
M
0.25 (0.010) T
–T–
SEATING
PLANE
1 7
14 9
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
1 7
14 8
B
A
F
H G D
K
C
N
L
J
M
SEATING
PLANE
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
M 0 10 0 10
N 0.015 0.039 0.39 1.01
_ _ _ _
Page 6
MOTOROLA CMOS LOGIC DATAMC14562B
6
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P
7 PL
14 8
71
M
0.25 (0.010) B
M
S
B
M
0.25 (0.010) A
S
T
–T–
F
R
X 45
SEATING
PLANE
D 14 PL
K
C
J
M
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
_ _ _ _
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MC14562B/D
*MC14562B/D*
◊
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