Datasheet MC14562BCP Datasheet (MOTOROLA)

MC14562B

128-Bit Static Shift
Register

The MC14562B is a 128–bit static shift register constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. Data is clocked in and out of the shift
register on the positive edge of the clock input. Data outputs are
available every 16 bits, from 16 through bit 128. This complementary
MOS shift register is primarily used where low power dissipation
and/or high noise immunity is desired.

• Diode Protection on All Inputs

• Fully Static Operation

• Cascadable to Provide Longer Shift Register Lengths

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving T wo Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated T emperature Range

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

DD

Vin, V

Iin, I

P

T

T

stg

T

1. Maximum Ratings are those values beyond which damage to the device

may occur.

2. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

DC Supply Voltage Range –0.5 to +18.0 V
Input or Output Voltage Range

out

Input or Output Current

out

Power Dissipation,

D

Ambient Temperature Range –55 to +125 °C

A

Storage Temperature Range –65 to +150 °C
Lead Temperature

L

Parameter Value Unit

(DC or Transient)

(DC or Transient) per Pin

per Package (Note 2.)

(8–Second Soldering)

) (Note 1.)

SS

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

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MARKING

DIAGRAMS

14

PDIP–14

P SUFFIX

CASE 646

A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

MC14562BCP

AWLYYWW

1

ORDERING INFORMATION

Device Package Shipping

MC14562BCP PDIP–14 25/Rail

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev . 3

v (Vin or V

SS

or VDD). Unused outputs must be left open.

) v VDD.

out

and V

in

should be constrained

out

1 Publication Order Number:

MC14562B/D

MC14562B

PIN ASSIGNMENT

Q64
Q96

Q128

NC

CLOCK

Q112

V

SS

NC = NO CONNECTION

BLOCK DIAGRAM

12

5

Pins 4 and 11
not used.

DATA

CLOCK

1
2
3
4

6
7

14
13
12
11
105

9
8

Q16
Q32
Q48
Q64
Q80
Q96

Q112

V

DD

V

V
Q32
DATA
NC
Q16
Q48

Q80

= PIN 14

= PIN 7

SS

DD

10
13
9
1
8
2
6
3Q128

CLOCK 5

DATA IN 12

LOGIC DIAGRAM

DCQDCQDCQDCQDCQDCQDCQDCQD

1 2 3 16173233484964

DCQDCQDCQDCQ

65 80 81 96

DCQ

97

DCQ

112

DCQ

113

DCQ

128

QDCQ

C

10 Q16

13 Q32

9 Q48

1 Q64

8 Q80

2 Q96

6Q112

3 Q128

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2

MC14562B

V

DD

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

V

Characteristic Symbol

Output Voltage “0” Level

V

= VDD or 0

in

“1” Level

V

= 0 or V

in

DD

Input Voltage “0” Level

(V

= 4.5 or 05 Vdc)

O

(V

= 9.0 or 1.0 Vdc)

O

(V

= 13.5 or 1.5 Vdc)

O

“1” Level

(V

= 0.5 or 4.5 Vdc)

O

= 1.0 or 9.0 Vdc)

(V

O

(V

= 1.5 or 13.5 Vdc)

O

Output Drive Current

(V

= 2.5 Vdc) Source

OH

(V

= 4.6 Vdc)

OH

(V

= 9.5 Vdc)

OH

(V

= 13.5 Vdc)

OH

(VOL = 0.4 Vdc) Sink
(V

= 0.5 Vdc)

OL

= 1.5 Vdc)

(V

OL

Input Current I
Input Capacitance

(V

= 0)

in

Quiescent Current

(Per Package)

Total Supply Current

(4.) (5.)

(Dynamic plus Quiescent,
Per Package)

= 50 pF on all outputs, all

(C

L

V

OL

V

OH

V

V

I

OH

I

OL

in

C

I

DD

I

Vdc

5.0
10
15

5.0
10
15

IL

5.0
10
15

IH

5.0
10
15

5.0

5.0
10
15

5.0
10
15

Min Max Min Typ

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

– 3.0

– 0.64

– 1.6
– 4.2

0.64

1.6

4.2

15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc

in

T

— — — — 5.0 7.5 — — pF

5.0
10
15

—
—
—

5.0
10
15

)

SS

– 55_C 25_C 125_C

(3.)

Max Min Max

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0

—
—
—

—
—
—
—

—
—
—

5.0
10
20

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

– 2.4

– 0.51

– 1.3
– 3.4

0.51

1.3

3.4

—
—
—

0
0
0

5.0
10
15

2.25

4.50

6.75

2.75

5.50

8.25

– 4.2

– 0.88

– 2.25

– 8.8

0.88

2.25

8.8

0.010

0.020

0.030

IT = (1.94 µA/kHz) f + I
IT = (3.81 µA/kHz) f + I
IT = (5.52 µA/kHz) f + I

0.05

0.05

0.05
—

—
—

1.5

3.0

4.0

—
—
—

—
—
—
—

—
—
—

5.0
10
20

DD
DD
DD

—
—
—

4.95

9.95

14.95

—
—
—

3.5

7.0
11

– 1.7

– 0.36

– 0.9
– 2.4

0.36

0.9

2.4

—
—
—

0.05

0.05

0.05

buffers switching)

3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

4. The formulas given are for the typical characteristics only at 25_C.

5. To calculate total supply current at loads other than 50 pF:
I

) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

T

—
—
—

1.5

3.0

4.0

—
—
—

—
—
—
—

—
—
—

150
300
600

Unit

Vdc

Vdc

Vdc

Vdc

mAdc

mAdc

µAdc

µAdc

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3

MC14562B

SWITCHING CHARACTERISTICS

(6.)

(C

L

= 50 pF, T

Characteristic

Output Rise and Fall Time

t

, t

TLH

t

TLH

t

TLH

= (1.5 ns/pF) CL + 25 ns

THL

, t

= (0.75 ns/pF) CL + 12.5 ns

THL

, t

= (0.55 ns/pF) CL + 9.5 ns

THL

Propagation Delay Time

Clock to Q

, t

t
t
t

PLH
PLH
PLH

= (1.7 ns/pF) CL + 515 ns

PHL

, t

= (0.66 ns/pF) CL + 217 ns

PHL

, t

= (0.5 ns/pF) CL + 145 ns

PHL

Clock Pulse Width

(50% Duty Cycle)

Clock Pulse Frequency f

Data to Clock Setup Time

Data to Clock Hold Time

Clock Input Rise and Fall Times tr, t

= 25_C)

A

Symbol V

t

,

TLH

t

THL

t

,

PLH

t

PHL

t

WH

cl

t

su(1)

t

su(0)

t

h(1)

t

h(0)

f

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

5.0
10
15

DD

Min Typ

—
—
—

—
—
—

600
220
150

—
—
—

– 20
– 10

0

– 20
– 10

0

– 170

– 64
– 60

– 91
– 58
– 48

350
165
155

350
200
140

—
—
—

100

50
40

600
250
170

300
110

75

1.9

5.6

8.0

263
109
100

267
140

93
—

—
—

(7.)

Max Unit

200
100

80

1200

500
340

—
—
—

1.1

3.0

4.0
—

—
—

—
—
—

—
—
—

—
—
—

15

5
4

6. The formulas given are for the typical characteristics only at 25_C.

7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance .

ns

ns

ns

MHz

ns

ns

ns

ns

µs

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4

DATA

CLOCK

MC14562B

V

DD

Q16

Q32

Q48

Q64

Q80

Q96

Q112

Q128

C

CLCLCLCLCLCLC

V

7

SS

L

L

I

500 µF

D

f

o

CLOCK

DATA

)

(f = 1/2 f

o

Figure 1. Power Dissipation Test Circuit and Waveforms

V

DD

V

SS

V

DD

V

SS

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5

MC14562B

TIMING DIAGRAM

PIN

NO.’S

CLOCK 5

DATA IN 12

Q16 10

Q32 13

Q28 3

CLOCK

DATA IN

Q16

CLOCK

DATA IN

Q16

PULSE 1

PULSE 1 PULSE 2 PULSE 16 PULSE 17

50% 50% 50%

50%

t

su(0)

PULSE 1 PULSE 2 PULSE 16 PULSE 17

50% 50% 50%

50% 50%

t

su(1)

PULSE 16 PULSE 32 PULSE 128

AC TEST WAVEFORMS

90%

10%

t

WH

t

t

WH

t

WL

WL

50%

t

r

t

h(0)

t

h(1)

t

f

t

PHL

t

PLH

50%

50%

50%

t

THL

50%

t

THL

10%

90%

90%

10%

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

NOTE: The remaining Data–Bit Outputs (Q32, Q48, Q64, Q80, Q96, Q112 and Q128) will occur at Clock Pulse 32, 48, 64, 80,

96, 112, 128 in the same relationship as Q16.

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MC14562B

P ACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE M

14 8

B

17

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–T–

SEATING
PLANE

N

HG

A

F

L

C

D

14 PL

0.13 (0.005)

K

J

M

M

DIM MIN MAX MIN MAX

A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L

0.290 0.310 7.37 7.87

M ––– 10 ––– 10
N 0.015 0.039 0.38 1.01

MILLIMETERSINCHES

__

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MC14562B

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MC14562B/D