Datasheet MC14557BCP, MC14557BDW, MC14557BDWR2, MC14557BF, MC14557BFEL Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14557B/D

MC14557B

1-to-64 Bit V ariable Length
Shift Register

The MC14557B is a static clocked serial shift register whose length
may be programmed to be any number of bits between 1 and 64. The
number of bits selected is equal to the sum of the subscripts of the
enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus
one. Serial data may be selected from the A or B data inputs with the
A/B select input. This feature is useful for recirculation purposes. A
Clock Enable (CE) input is provided to allow gating of the clock or
negative edge clocking capability .

The device can be effectively used for variable digital delay lines or
simply to implement odd length shift registers.

• 1–64 Bit Programmable Length

• Q and Q Serial Buffered Outputs

• Asynchronous Master Reset

• All Inputs Buffered

• No Limit On Clock Rise and Fall T imes

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or one Low–power

Schottky TTL Load Over the Rated Temperature Range

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol

Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. T emperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

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A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14557BCP PDIP–16 2000/Box
MC14557BDW SOIC–16 47/Rail

MARKING

DIAGRAMS

1

16

PDIP–16

P SUFFIX

CASE 648

MC14557BCP

AWLYYWW

SOIC–16
DW SUFFIX
CASE 751G

1

16

14557B

AWLYYWW

MC14557BDWR2 SOIC–16 1000/Tape & Reel
MC14557BF SOEIAJ–16 See Note 1.
MC14557BFEL SOEIAJ–16 See Note 1.

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

SOEIAJ–16

F SUFFIX

CASE 966

1

16

MC14557B

AWLYWW

MC14557B

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2

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

L32

L16

L8

L4

V

DD

A/B SEL

Q

Q

CLOCK

RESET

L1

L2

V

SS

A

B

CE

BLOCK DIAGRAM

TRUTH TABLE

Inputs Output

Rst A/B Clock CE

Q

00 0 B
01 0 A
00 1 B
01 1 A
1X X X 0

Q is the output of the first selected shift

register stage.

X = Don’t Care

12

13

14

1

15

2

9

7

6

5

4

3

11

10

RESET
CLOCK
CE
B
A
A/B SELECT
L1
L2
L4
L8
L16
L32

Q

Q

VDD = PIN 16

V

SS

= PIN 8

LENGTH SELECT TRUTH TABLE

L32 L16 L8 L4 L2 L1 Register Length

0

0

0

0

0

0

1 Bit

0

0

0

0

0

1

2 Bits

0000103 Bit

s

0000114 Bits

0000001100015 Bits

6 Bits

0001016 Bits
























1

0

0

0

0

0

33 Bits

10000134 Bit

s













111100



61 Bits
1 1 1 1 1 1 62 Bits
1

1

1

1

1

0

63 Bits

11110164 Bi

ts

NOTE: Length equals the sum of the binary length control

subscripts plus one.

MC14557B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C 25_C 125_C

Characteristic Symbol

V

DD

Vdc

Min Max Min Typ

(4.)

Max Min Max

Unit

Output Voltage “0” Level

V

in

= VDD or 0

V

OL

5.0
10
15

—
—
—

0.05

0.05

0.05

—
—
—

0
0
0

0.05

0.05

0.05

—
—
—

0.05

0.05

0.05

Vdc

“1” Level

V

in

= 0 or V

DD

V

OH

5.0
10
15

4.95

9.95

14.95

—
—
—

4.95

9.95

14.95

5.0
10
15

—
—
—

4.95

9.95

14.95

—
—
—

Vdc

Input Voltage “0” Level

(V

O

= 4.5 or 0.5 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

V

IL

5.0
10
15

—
—
—

1.5

3.0

4.0

—
—
—

2.25

4.50

6.75

1.5

3.0

4.0

—
—
—

1.5

3.0

4.0

Vdc

“1” Level

(V

O

= 0.5 or 4.5 Vdc)

(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

V

IH

5.0
10
15

3.5

7.0
11

—
—
—

3.5

7.0
11

2.75

5.50

8.25

—
—
—

3.5

7.0
11

—
—
—

Vdc

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

I

OH

5.0

5.0
10
15

– 3.0

– 0.64

– 1.6
– 4.2

—
—
—
—

– 2.4

– 0.51

– 1.3
– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—
—
—
—

– 1.7

– 0.36

– 0.9
– 2.4

—
—
—
—

mAdc

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

I

OL

5.0
10
15

0.64

1.6

4.2

—
—
—

0.51

1.3

3.4

0.88

2.25

8.8

—
—
—

0.36

0.9

2.4

—
—
—

Input Current I

in

15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc

Input Capacitance

(V

in

= 0)

C

in

— — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package)

I

DD

5.0
10
15

—
—
—

5.0
10
20

—
—
—

0.010

0.020

0.030

5.0
10
20

—
—
—

150
300
600

µAdc

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

L

= 50 pF on all outputs, all

buffers switching)

I

T

5.0
10
15

IT = (1.75 µA/kHz) f + I

DD

IT = (3.50 µA/kHz) f + I

DD

IT = (5.25 µA/kHz) f + I

DD

µAdc

4. Data labelled “T yp” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MC14557B

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4

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

A

= 25_C)

Characteristic

Symbol V

DD

Min Typ

(8.)

Max Unit

Rise and Fall Time, Q or Q Output

t

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

t

TLH

,

t

THL

5
10
15

—
—
—

100

50
40

200
100

80

ns

Propagation Delay, Clock or CE to Q or Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 215 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 65 ns

t

PLH

,

t

PHL

5
10
15

—
—
—

300
130

90

600
260
180

ns

Propagation Delay, Reset to Q or Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 215 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 70 ns

t

PLH

,

t

PHL

5
10
15

—
—
—

300
130

95

600
260
190

ns

Pulse Width, Clock t

WH(cl)

5
10
15

200
100

75

95
45
35

—
—
—

ns

Pulse Width, Reset t

WH(rst)

5
10
15

300
140
100

150

70
50

—
—
—

ns

Clock Frequency (50% Duty Cycle) f

cl

5
10
15

—
—
—

3.0

7.5

13.0

1.7

5.0

6.7

MHz

Setup Time, A or B to Clock or CE

Worst case condition: L1 = L2 = L4 = L8 =
L16 = L32 = V

SS

(Register Length = 1)

t

su

5
10
15

700
290
145

350
130

85

—
—
—

ns

Best case condition: L32 = VDD, L1 through L16 =
Don’t Care (Any register length from 33 to 64)

5
10
15

400
165

60

45

5
0

—
—
—

Hold Time, Clock or CE to A or B

Best case condition: L1 = L2 = L4 = L8 = L16 =
L32 = V

SS

(Register Length = 1)

t

h

5
10
15

200
100

10

– 150

– 60
– 50

—
—
—

ns

Worst case condition: L32 = VDD, L1 through L16 =
Don’t Care (Any register length from 33 to 64)

5
10
15

400
185

85

50
25
22

—
—
—

Rise and Fall Time, Clock tr,

t

f

5
10
15

No Limit

—

Rise and Fall Time, Reset or CE tr,

t

f

5
10
15

—
—
—

—
—
—

15

5
4

µs

Removal Time, Reset to Clock or CE t

rem

5
10
15

160

80
70

80
40
35

—
—
—

ns

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “T yp” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14557B

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5

TIMING DIAGRAM

1–bit length:

CE

= 0
A/B = 1
L1 = L2 = L4 = L8 = L16 = L32 = 0

PW

R

50%

t

WH(cl)

t

h

50%

t

su

t

rem

50%

t

TLH

t

THL

t

PHL

t

PHL

t

PLH

90%

50%

10%

A INPUT

CLOCK

RESET

Q

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

1/f

cl

MC14557B

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6

LOGIC DIAGRAM

A/B

SELECT

B

A

RESET

CLOCK

CE

9

6

7

3

4

5

CR

32 BIT

12

L32

CR

2 BIT

1

L2

2

L1

CR

1 BIT

CR

16 BIT

13

L16

14

L8

CR

1 BIT

CR

8 BIT

10

11

Q

Q

15

L4

CR

4 BIT

V

DD

= PIN 16

V

SS

= PIN 8

MC14557B

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7

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

SOIC–16

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751G–03

ISSUE B

D

14X

B16X

SEATING
PLANE

S

A

M

0.25 B

S

T

16 9

81

h X 45

_

M

B

M

0.25

H8X

E

B

A

e

T

A1

A

L

C

q

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.

DIM MIN MAX

MILLIMETERS

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49
C 0.23 0.32
D 10.15 10.45
E 7.40 7.60

e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90

q

0 7

__

MC14557B

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8

P ACKAGE DIMENSIONS

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035

––– 0.78 ––– 0.031

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005)

0.10 (0.004)

1

16 9

8

D

Z

E

A

b

c
D
E

e

L

M

Z

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

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