Page 1
MOTOROLA CMOS LOGIC DATA
1
MC14554B
The MC14554B 2 x 2–bit parallel binary multiplier is constructed with
complementary MOS (CMOS) enhancement mode devices. The multiplier
can perform the multiplication of two binary numbers and simultaneously add
two o ther b inary n umbers to t he p roduct. T he M C14554B h as t wo
multiplicand inputs (X0 and X1), two multiplier inputs (Y0 and Y1), f ive
cascading or adding inputs (K0, K1, M0, M1, and M2), and five sum and
carry outputs (S0, S1, S2, C1 [S3], and C0). The basic multiplier can be
expanded into a straightforward m–bit by n–bit parallel multiplier without
additional logic elements.
Application areas include arithmetic processing (multiplying/adding,
obtaining square roots, polynomial evaluation, obtaining reciprocals, and
dividing), Fast Fourier Transform processing, digital filtering, communications (convolution and correlation), and process and machine controls.
• Diode Protection on All Inputs
• All Outputs Buffered
• Straight–forward m–Bit By n–Bit Expansion
• No Additional Logic Elements Needed for Expansion
• Multiplies and Adds Simultaneously
• Positive Logic Design
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 18.0 V
Vin, V
out
Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current (DC or Transient),
per Pin
± 10 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
K0
X1
X0
Y0
V
DD
S1
K1
S0
C0
M1
M0
Y1
V
SS
S2
C1 (S3)
M2
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and V
out
should be constrained
to the range VSS v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or VDD). Unused outputs must be left open.
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
S = (X x Y) + K + M
Where:
x Means Arithmetic Times.
+ Means Arithmetic Plus.
S = S3 S2 S1 S0, X = X1X0, Y = Y1Y0,
K = K1 K0, M = M1 M0 (Binary Numbers).
Example:
Given: X = 2(1), Y = 3(11)
K = 1(01), M = 2(10)
Then: S = (2 x 3) + 1 + 2 = 9
S = (10 x 11) + 01 + 10 = 1001
EQUATIONS
NOTE: C0 connected to M2 for this size
multiplier. See general expansion
diagram for other size multipliers.
Page 2
MOTOROLA CMOS LOGIC DATAMC14554B
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C 25_C 125_C
Characteristic
Symbol
V
DD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage “0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current I
in
15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
Input Capacitance
(Vin = 0)
C
in
— — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (1.0 µA/kHz) f + I
DD
IT = (2.0 µA/kHz) f + I
DD
IT = (3.0 µA/kHz) f + I
DD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.0035.
Page 3
MOTOROLA CMOS LOGIC DATA
3
MC14554B
SWITCHING CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C)
Characteristic
Symbol V
DD
Min Typ # Max Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) CL + 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) CL + 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) CL + 9.5 ns
t
TLH
,
t
THL
5.0
10
15
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
K0 to C0
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 185 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 82 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 60 ns
M0 to S2
t
PLH
, t
PHL
= (1.7 ns/pF) CL + 595 ns
t
PLH
, t
PHL
= (0.66 ns/pF) CL + 247 ns
t
PLH
, t
PHL
= (0.5 ns/pF) CL + 185 ns
t
PLH
,
t
PHL
5.0
10
15
5.0
10
15
—
—
—
—
—
—
270
115
85
680
280
210
675
290
215
1700
750
570
ns
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Dynamic Power Dissipation
Waveforms
Figure 2. Dynamic Signal Waveforms
All outputs connected to respective
CL loads. f = system clock frequency
LOGIC DIAGRAM
MULTIPLIER CELL
Inputs X0, X1, Y0, Y1, K1, and M2 low, and inputs
M0 and M1 high.
MULTIPLIER
CELL
20 ns 20 ns
V
DD
V
SS
V
OH
V
OL
90%
50%
10%
2f
1
ALL INPUTS
(50% DUTY CYCLE)
ANY OUTPUT
(50% DUTY CYCLE)
V
DD
V
SS
V
OH
V
OL
20 ns 20 ns
90%
50%
10%
t
PLH
t
PHL
50%
90%
10%
t
TLH
t
THL
OUTPUT
C0 OR S2
INPUT
K0 OR M0
M1 Y1 M0 Y0
4
5
M2
C0
X0
K0
14
12
3 21 15
M Y M Y
X
X
K K
S
C
S
C
MULTIPLIER
CELL
M
X
K
S
C
Y M
X
K
S
C
Y
MULTIPLIER
CELL
MULTIPLIER
CELL
6 7 9 11
S2 S1 S0C1(S3)
X1
K1
M
Y
X
K
L
S
C
For K0 to C0:
Inputs X1, Y1, and K0 low, and inputs X0, Y0,
K1, M1, and M2 high.
For M0 to S2:
13
10
Page 4
MOTOROLA CMOS LOGIC DATAMC14554B
4
EXPANSION DIAGRAM
m–Bit by n–Bit Parallel Binary Multiplier (Top View)
S = (X x Y) + K + M Where: x means Arithmetic Times.
S = (X x Y) + K + M Where: + means Arithmetic Plus.
S = S(m + n–1) S(m + n–2) … S2 S1 S0
X = X(m–1) X (m–2) … X2 X1 X0, Y = Y(n–1) Y(n–2) … Y2 Y1 Y0
K = K(m–1) K(m–2) … K2 K1 K0 and M = M(n–1) M(n–2) … M2 M1 M0
(Binary Numbers).
Number of output binary digits = m + n
Number of packages = mxn/4 (For m or n of both odd select next highest even number.)
Y(n–1)
M(n–2)
M(n–1)
Y(n–2)
X0
X1
Y3
M2
M3
Y2
X0
X1
Y1
M0
M1
Y0
X0
X1
K0
K1
Y(n–1)
Y(n–2)
X2
X3
Y(n–2)
X(m–2)
X(m–1)
Y(n–1)
S(m + n–1) S(m + n–2) S(m + n–3) S(m+2) S(m+1) S(m)
Y3
Y2
X2
X3
Y3
Y2
X(m–2)
X(m–1)
Y1
Y0
X2
X3
K2
K3
Y1
Y0
X(m–2)
X(m–1)
K(m–2)
K(m–1)
S(m–1) S3 S1
S2 S0S(m–2)
X AND K
Y AND M
Y1
M0
M1
C0
M2
C1
S2
V
SS
V
DD
Y0
X0
X1
K0
S0
K1
S1
Page 5
MOTOROLA CMOS LOGIC DATA
5
MC14554B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
F
E
G
N
K
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
Page 6
MOTOROLA CMOS LOGIC DATAMC14554B
6
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
_ _ _ _
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
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MC14554B/D
*MC14554B/D*
◊
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