Datasheet MC145443BP, MC145442BDW, MC145443BDW Datasheet (Motorola)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MC145442B/D

MC145442B

Single-Chip 300-Baud Modem

The MC145442B and MC145443B silicon–gate CMOS single–chip low–
speed modems contain a complete frequency shift keying (FSK) modulator,
demodulator, and filter. These devices are compatible with CCITT V.21
(MC145442B) and Bell 103 (MC145443B) specifications. Both devices provide
full–duplex or half–duplex 300–baud data communication over a pair of
telephone lines. They also include a carrier detect circuit for the demodulator
section and a duplexer circuit for direct operation on a telephone line through a
simple transformer.

• MC145442B Compatible with CCITT V.21

• MC145443B Compatible with Bell 103

• Low–Band and High–Band Band–Pass Filters On–Chip

• Simplex, Half–Duplex, and Full–Duplex Operation

• Originate and Answer Mode

• Analog Loopback Configuration for Self Test

• Hybrid Network Function On–Chip

• Carrier Detect Circuit On–Chip

• Adjustable Transmit Level and CD

• On–Chip Crystal Oscillator (3.579 MHz)

• Single +5 V Power Supply Operation

• Internal Mid–Supply Generator

• Power–Down Mode

• Pin Compatible with MM74HC943

• Capable of Driving –9 dBm into a 600 Ω Load

Delay Timing

MC145443B

P SUFFIX

20

1

20

1

ORDERING INFORMATION

MC145442BP Plastic DIP
MC145443BP Plastic DIP

MC145442BDW SOG Package
MC145443BDW SOG Package

PIN ASSIGNMENT

DSI

1

LB

2

CD

3

CDT

4

RxD 5

V

6

DD

CDA

7

X

8

out
X

9

in

FB

10

PLASTIC DIP

CASE 738

DW SUFFIX

SOG PACKAGE

CASE 751D

20

TLA

19

V

18

Exl

17

TxA

16

RxA1

15

RxA2

14

SQT

13

MODE

12

V

11

TxD

AG

SS

REV 1
9/00

 Motorola, Inc. 2000

MC145442B•MC145443BMOTOROLA

1

15

RxA2

16

RxA1

2

LB

13

MODE

14

SQT

11

TxD

20

TLA

8

X

out
X

in

*Refer to the FB pin description.

9

OSCILLATOR

–
+

MODULATOR

MODE

CONTROL

AAF S/H

CLOCK

DIVIDER

BLOCK DIAGRAM

LOW–BAND

BPF

HIGH–BAND

BPF

SAMPLING CLOCK: 77.82 kHz
SAMPLING CLOCK: 19.46 kHz

SMOOTHING

FILTER

INTERNAL

V

AG

AC AMP

ANALOG

GROUND

GENERATOR

4

CDT

7

CDA

CARRIER

DETECT

*

DEMOD

–
+

3

CD

5

RxD

10

FB

1

DSI

17

TxA

18

ExI

19

V

AG

6

V

DD

12

V

SS

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

Rating Symbol Value Unit

Supply Voltage V
DC Input Voltage V
DC Output Voltage V
Clamp Diode Current, per Pin IIK, I
DC Output Current, per Pin I
Power Dissipation P
Operating Temperature Range T
Storage Temperature Range T

DD

out

out

stg

in

D
A

–0.5 to VDD + 0.5 V
–0.5 to VDD + 0.5 V

OK

)

SS

–0.5 to 7.0 V

±20 mA
±28 mA

500 mW

–40 to 85 °C

–65 to 150 °C

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Max Unit

Supply Voltage V
DC Input or Output Voltage Vin, V
Input Rise or Fall Time tr, t
Crystal Frequency* f

*Changing the crystal frequency from 3.579 MHz will change the output frequencies. The

change in output frequency will be proportional to the change in crystal frequency .

DD

out
f

crystal

4.5 5.5 V
0 V

— 500 ns

3.2 5.0 MHz

DD

V

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised that
normal precautions be taken to avoid application
of any voltage higher than maximum rated
voltages to this high impedance circuit. For
proper operation it is recommended that Vin and

V

be constrained to the range VSS ≤ (Vin or

out

V

) ≤ VDD).

out

Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
or VDD).

SS

MC145442B•MC145443B MOTOROLA
2

DC ELECTRICAL CHARACTERISTICS (V

Characteristic Symbol Min Typ Max Unit

High–Level Input Voltage LB

Low–Level Input Voltage LB

High–Level Output Voltage

IOH = 20 µACD
IOH = 2 mA CD
IOH = 20 µAX

Low–Level Output Voltage

IOL = 20 µACD
IOL = 2 mA CD
IOL = 20 µAX

Input Current LB, TxD, Mode, SQT

Quiesent Supply Current (Xin or f
Power–Down Supply Current — 200 300 µA
Input Capacitance X

VAG Output Voltage (IO = ±10 µA) V
CDA Output Voltage (IO = ±10 µA) V
Line Driver Feedback Resistor R

RxA1, RxA2 (0° x TA x 85°C)

RxA1, RxA2 (–40° x TA < 0°C)

= 3.579 MHz) I

crystal

= 5.0 V ±10%, TA = –40° to 85°C)

DD

Xin, TxD, Mode, SQT

Xin, TxD, Mode, SQT

, RxD
, RxD

out

, RxD
, RxD

out

X

in

All Other Inputs

in

V

V

V

OH

V

OL

I

DD

C

AG

CDA

IH

IL

in

in

VDD – 0.8

3.15
—

—

VDD – 0.1

3.7
—

—
—
—

—
—
—
—

— 7 10 mA

—
—

2.4 2.5 2.6 V

1.1 1.2 1.3 V

f

10 20 30 kΩ

—
—

—
—

—
—

VDD – 0.05

—
—

0.05
—

10
—
—

10
—

—
—

0.8

1.1

—
—
—

0.1

0.4
—

±1.0

±12
±20
±10

—

10

V

V

V

V

µA

pF

AC ELECTRICAL CHARACTERISTICS

(VDD = 5.0 V ±10%, TA = –40° to 85°C, Crystal Frequency = 3.579 MHz ±0.1%; See Figure 1)

Characteristic

TRANSMITTER

Power Output on TxA

RL = 1.2 kΩ, R
RL = 1.2 kΩ, R

Second Harmonic Power

RL = 1.2 kΩ

RECEIVE FILTER AND HYBRID

Hybrid Input Impedance RxA1, RxA2 40 50 — kΩ
FB Output Impedance — 16 — kΩ
Adjacent Channel Rejection –48 — — dBm

DEMODULATOR

Receive Carrier Amplitude –48 — –12 dBm
Dynamic Range — 36 — dB
Bit Jitter (S/N = 30 dB, Input = –38 dBm, Bit Rate = 300 baud) — 100 — µs
Bit Bias — 5 — %
Carrier Detect Threshold On to Off

(CDA = 1.2 V or CDA grounded through a 0.1 µF capacitor) Off to On

TLA
TLA

= ∞
= 5.5 kΩ

Min Typ Max Unit

–13
–10

— –56 — dBm

—
—

–12

–9

–44
–47

–11

–8

—
—

dBm

dBm

MC145442B•MC145443BMOTOROLA

3

3.579 MHz ± 0.1%

CDT

98

X

in

11

TxD

5

RxD

FB

10

0.1 µF

C

FB

TEST

INPUT

R

TLA

V

DD

600 Ω

600 Ω

TEST

OUTPUT

20
17
15

16

0.1 µF

X

out

TLA
TxA
RxA2

MC145442B
MC145443B

RxA1

CDT

4

C

Figure 1. AC Characteristics Evaluation Circuit

T able 1. Bell 103 and CCITT V.21

Frequency Characteristics

Originate Mode Answer Mode

D

in

D

out

Data

Bell 103 (MC145443B)

Space 1070 Hz 2025 Hz 2025 Hz 1070 Hz

Mark 1270 Hz 2225 Hz 2225 Hz 1270 Hz

CCITT V.21 (MC145442B)

Space 1180 Hz 1850 Hz 1850 Hz 1180 Hz

Mark 980 Hz 1650 Hz 1650 Hz 980 Hz

NOTE: Actual frequencies may be ±5 Hz assuming 3.579545 MHz

RELATIVE TO THE TRANSMIT CARRIER LEVEL INT O 600 Ω (kHz)

Transmit Receive Transmit Receive

crystal is used.

MAXIMUM LEVEL OF OUT–OF–BAND ENERGY

25664163.4 420

PIN DESCRIPTIONS

V

DD

Positive Power Supply (Pin 6)

This pin is normally tied to 5.0 V.

V

SS

Negative Power Supply (Pin 12)

This pin is normally tied to 0 V.

V

AG

Analog Ground (Pin 19)

Analog ground is internally biased to (VDD – VSS)/2. This
pin must be decoupled by a capacitor from VAG to VSS and a
capacitor from VAG to VDD. Analog ground is the common
bias line used in the switched capacitor filters, limiter, and
slicer in the demodulation circuitry .

TLA
Transmit Level Adjust (Pin 20)

This pin is used to adjust the transmit level. Transmit level
adjustment range is typically from –12 dBm to –9 dBm. (See

Applications Information.

TxD
Transmit Data (Pin 11)

Binary information is input to the transmit data pin. Data
entered for transmission is modulated using FSK techniques.
A logic high input level represents a mark and a logic low
represents a space (see Table 1).

TxA
Transmit Carrier (Pin 17)

This is the output of the line driver amplifier. The transmit
carrier is the digitally synthesized sine wave output of the
modulator derived from a crystal oscillator reference. When a

3.579 MHz crystal is used the frequency outputs shown in
Table 1 apply. (See

)

Applications Information

.)

0

–20
–25

15 dB/OCTAVE

–55

TRANSMIT CARRIER LEVEL (dBm)

–60

Figure 2. Out–of–Band Energy

ExI
External Input (Pin 18)

The external input is the non–inverting input to the line
driver. It is provided to combine an auxiliary audio signal or
speech signal to the phone line using the line driver. This pin
should be connected to VAG if not used. The average level
must be the same as VAG to maintain proper operation. (See

Applications Information

.)

DSI
Driver Summing Input (Pin 1)

The driver summing input may be used to connect an ex­ternal signal, such as a DTMF dialer, to the phone line. A
series resistor, R
AV (see

Applications Information

, is needed to define the voltage gain

DSI

and Figure 6). When ap­plying a signal to the DSI pin, the modulator should be
squelched by bringing SQT (pin 14) to a logic high level. The
voltage gain, AV, is calculated by the formula AV = –Rf/R
(where Rf ≈ 20 kΩ). For example, a 20 kΩ resistor for R

DSI
DSI

will provide unity gain (AV = –20 kΩ/20 kΩ = –1). This pin
must be left open

if not used.

RxD
Receive Data (Pin 6)

The receive data output pin presents the digital binary data
resulting from the demodulation of the receive carrier. If no
carrier is present, CD

high, the receive data output (RxD) is

clamped high.

MC145442B•MC145443B MOTOROLA
4

RxA2, RxA1
Receive Carrier (Pins 15, 16)

The receive carrier is the FSK input to the demodulator
through the receive band–pass filter. RxA1 is the non–invert­ing input and RxA2 is the inverting input of the receive hybrid
(duplexer) operational amplifier.

LB
Analog Loopback (Pin 2)

When a high level is applied to this pin (SQT must be low),
the analog loopback test is enabled. The analog loopback
test connects the TxA pin to the RxA2 pin and the RxA1 to
analog ground. In loopback, the demodulator frequencies
are switched to the modulation frequencies for the selected
mode. (See Tables 1 and 2 and Figures 4c and 4d.)

When LB

is connected to analog ground (VAG), the modu­lator generates an echo cancellation tone of 2100 Hz for
MC145442B CCITT V.21 and 2225 Hz for MC145443B Bell
103 systems. For normal operation, this pin should be at a
logic low level (VSS).

The power–down mode is enabled when both LB

and SQT

are connected to a logic high level (see Table 2).

T able 2. Functional Table

MODE
Pin 13

SQT

Pin 14

1 0 0 Originate Mode
0 0 0 Answer Mode
X 0 VAG (VDD/2) Echo Tone
X 0 1 Analog Loopback
X 1 0 Squelch Mode
X 1 VAG (VDD/2) Squelch Mode
X 1 1 Power Down

LB

Pin 2

Operating Mode

MODE
Mode (Pin 13)

This input selects the pair of transmit and frequencies
used during modulation and demodulation. When a logic
high level is placed on this input, originate (Bell) or channel 1
(CCITT) is selected. When a low level is placed on this input,
answer (Bell) or channel 2 (CCITT) is selected. (See
Tables 1 and 2 and Figure 4.)

CDT
Carrier Detect Timing (Pin 4)

A capacitor on this pin to VSS sets the amount of time the
carrier must be present before CD

tions Information

for the capacitor values).

goes low (see

Applica-

CD
Carrier Detect Output (Pin 3)

This output is used to indicate when a carrier has been
sensed by the carrier detect circuit. This output goes to a
logic low level when a valid signal above the maximum
threshold level (defined by CDA, pin 7) is maintained on the
input to the hybrid circuit longer then the response (defined

by CDT, pin 4). This pin is held at the logic low level until the
signal falls below the maximum threshold level for longer
than the turn off time. (See

Applications Information

and

Figure 5.)

CDA
Carrier Detect Adjust (Pin 7)

An external voltage may be applied to this pin to adjust the
carrier detect threshold. The threshold hysteresis is internally
fixed at 3 dB (see

X

, X

out

in

Applications Information

).

Crystal Oscillator (Pins 8, 9)

A crystal reference oscillator is formed when a 3.579 MHz
crystal is connected between these two pins. X

(pin 8) is

out

the output of the oscillator circuit, and Xin (pin 9) is the input
to the oscillator circuit. When using an external clock, apply
the clock to the Xin (pin 9) pin and leave X

(pin 8) open. An

out

internal 10 MΩ resistor and internal capacitors, typically
10 pF on Xin and 16 pF on X

, allow the crystal to be con-

out

nected without any other external components. Printed cir­cuit board layout should keep external stray capacitance to a
minimum.

FB
Filter Bias (Pin 10)

This is the negative input to the ac amplifier. In normal op­eration, this pin is connected to analog ground through a

0.1 µF bypass capacitor in order to cancel the input offset
voltage of the limiter. It has a nominal input impedance of
16 kΩ (see Figure 3).

SQT
Transmit Squelch (Pin 14)

When this input pin is at a logic high level, the modulator is
disabled. The line driver remains active if LB

is at a logic low

level (see Table 2).

When both LB

and SQT are connected to a logic high level
(see Table 2), the entire chip is in a power down state and all
circuitry except the crystal oscillator is disabled. Total power
supply current decreases from 10 mA (max) to 300 µA
(max).

FROM

BAND–PASS

FILTER

+
–

490 kΩ

16 kΩ

FB

10

0.1 µF

CARRIER DETECT CIRCUIT

TO

AND DEMODULATOR

Figure 3. AC Amplifier Circuit

MC145442B•MC145443BMOTOROLA

5

GENERAL DESCRIPTION

The MC145442B and MC145443B are full–duplex low–
speed modems. They provide a 300–baud FSK signal for bi­directional data transmission over the telephone network.
They can be operated in one of four basic configurations as
determined by the state of MODE (pin 13) and LB
The normal (non–loopback) and self test (loopback) modes
in both answer and originate modes will be discussed.

For an originate or channel 1 mode, a logic high level is
placed on MODE (pin 13) and a logic low level is placed on
LB

(pin 2). In this mode, transmit data is input on TxD, where
it is converted to a FSK signal and routed through a low–
band band–pass filter. The filtered output signal is then buff­ered by the Tx op–amp line driver, which is capable of driving
–9 dBm onto a 600 Ω line. The receive signal is connected
through a hybrid duplexer circuit on pins 15 and 16, RxA2
and RxA1. The signal then passes through the anti–aliasing
filter, the sample–and–hold circuit, is switched into the high–
band band–pass filter, and then switched into the ac amplifier
circuit. The output of the ac amplifier circuit is routed to the
demodulator circuit and demodulated. The resulting digital
data is then output through RxD (pin 5). The carrier detect
circuit receives its signal from the output of the ac amplifier
circuit and goes low when the incoming signal is detected
(see Figure 4a).

(pin 2).

In the answer or channel 2 mode, a logic low level is
placed on MODE (pin 13) and on LB
data follows the same path except the FSK signal is routed to
the high–band band–pass filter and the sample–and–hold
signal is routed through the low–band band–pass filter (see
Figure 4b).

In the analog loopback originate or channel 1 mode, a logic
high level is placed on MODE (pin 13) and on LB
mode is used for a self check of the modulator, demodulator,
and low–band pass–band filter circuit. The modulator side is
configured exactly like the originate mode above except the
line driver output (TxA, pin 17) is switched to the negative in­put of the hybrid op–amp. The RxA2 input pin is open in this
mode and the non–inverting input of the hybrid circuit is con­nected to VAG. The sample–and–hold output bypasses the
filter so that the demodulator receives the modulated Tx data
(see Figure 4c). This test checks all internal device compo­nents except the high–band band–pass filter, which can be
checked in the answer or channel 2 mode test.

In the analog loopback or channel 2 mode, a logic low level
is placed on MODE (pin 13) and a logic high level on LB
(pin 2). This mode is used for a self check of the modulator,
demodulator, and high–band pass–band filter circuit. This
configuration is exactly like the originate loopback mode
above, except the signal is routed through the high–band
pass–band filter (see Figure 4d).

(pin 2). In this mode, the

(pin 2). This

MC145442B•MC145443B MOTOROLA
6

15

RxA2

16

RxA1

–
+

AAF S/H

LOW–BAND

BPF

AC

AMP

CARRIER

DETECT

DEMOD

3

CD

5

RxD

1

DSI

TxD

RxA2

RxA1

TxD

RxA2

RxA1

11

MODULATOR

HIGH–BAND

BPF

SMOOTHING

FILTER

–

+

17

TxA

18

Exl

(a) Originate/Channel 1 Mode (MODE = High, LB = Low)

15

CARRIER

AC

AMP

DETECT

DEMOD

–

+

CARRIER

DETECT

DEMOD

16

11

–
+

AAF S/H

MODULATOR

LOW–BAND

BPF

HIGH–BAND

BPF

(b) Answer/Channel 2 Mode (MODE = Low, LB

15

16

–
+

AAF S/H

LOW–BAND

BPF

AC

AMP

SMOOTHING

FILTER

= Low)

3

CD

5

RxD

1

DSI

17

TxA

18

Exl

3

CD

5

RxD

TxD

RxA2

RxA1

TxD

1

DSI

11

MODULATOR

HIGH–BAND

BPF

SMOOTHING

FILTER

–

+

17

TxA

18

Exl

(c) Originate/Channel 1 Mode and Analog Loopback State (MODE = High, LB = Low)

15

CARRIER

16

11

–
+

AAF S/H

MODULATOR

LOW–BAND

BPF

HIGH–BAND

BPF

AC

AMP

SMOOTHING

FILTER

DETECT

DEMOD

–
+

3

CD

5

RxD

1

DSI

17

TxA

18

Exl

(d) Answer/Channel 2 Mode and Analog Loopback State (MODE = Low, LB = Low)

Figure 4. Basic Operating Modes

MC145442B•MC145443BMOTOROLA

7

APPLICATIONS INFORMATION

CARRIER DETECT TIMING ADJUSTMENT

The value of a capacitor, C
how long a received modem signal must be present above
the minimum threshold level before CD
C

capacitor also determines how long the CD pin stays

CDT

low after the received modem signal goes below the mini­mum threshold. The CD

pin is used to distinguish a strong
modem signal from random noise. The following equations
show the relationship between t
quired for CD
for CD

V alid signal to CD
Invalid signal to CD
Example: t

to go low; t

to go high; and C

response time: t

off time: t

≈ 6.4 × 0.1 µF ≈ 0.64 seconds

CDL

t

≈ 0.54 × 0.1 µF ≈ 0.054 seconds

CDH

CDH

CDT

CARRIER DETECT THRESHOLD ADJUSTMENT

The carrier detect threshold is set by internal resistors to
activate CD
deactivate CD

with a typical –44 dBm (into 600 Ω) signal and

with a typical –47 dBm signal applied to the
input of the hybrid circuit. The carrier detect threshold level
can be adjusted by applying an external voltage on CDA
(pin 7). The following equations may be used to find the CDA
voltage required for a given threshold voltage. (Von and V
are in Vrms.)

V

CDA

V

CDA

Example (Internally Set)

Von = 4.9 mV ≈ –44 dBm: V
V

= 3.5 mV ≈ –47 dBm: V

off

Example (Externally Set)

Von = 7.7 mV ≈ –40 dBm: V
V

= 5.4 mV ≈ –43 dBm: V

off

The CDA pin has an approximate Thevenin equivalent
voltage of 1.2 V and an output impedance of 100 kΩ. When
using the internal 1.2 V reference, a 0.1 µF capacitor should
be connected between this pin and VSS (see Figure 5).

at CDT (pin 4) determines

CDT

(pin 3) goes low. The

, the time in seconds re-

CDL

, the time in seconds required

, the capacitor value in µF.

≈ 6.4 × C

= 244 × V
= 345 × V

= 244 × 4.9 mV = 1.2 V

CDA

= 345 × 3.5 mV = 1.2 V

CDA

= 244 × 7.7 mV = 1.9 V

CDA

= 345 × 5.4 mV = 1.9 V

CDA

CDL
CDH

on
off

≈ 0.54 × C

CDT

CDT

off

(pin 20) to VDD (pin 6). Table 3 shows the R

values and

TLA

the corresponding power output for a 600 Ω load. The volt­age at TxA is twice the value of that at ring and tip because
TxA feeds the signal through a 600 Ω resistor RTx to a 600 Ω
line transformer (see Figure 7). When choosing resistor
R

, keep in mind that –9 dBm is the maximum output level

TLA

allowed from a modem onto the telephone line (in the U.S.).
In addition, keep in mind that maximizing the power output
from the modem optimizes the signal–to–noise ratio, improv­ing accurate data transmission.

T able 3. Transmit Level Adjust

Output Transmit Level

(Typical into 600 Ω)

–12 dBm ∞
–11 dBm 19.8 kΩ
–10 dBm 9.2 kΩ

–9 dBm 5.5 kΩ

R

TLA

THE LINE DRIVER

The line driver is a power amplifier used for driving a tele­phone line. Both the inverting and noninverting input to the
line driver are available for transmitting externally generated
tones.

Exl (pin 18) is the noninverting input to the line driver and
gives a fixed gain of 2 (Ri = 50 kΩ). The average signal level
must be the same as VAG to maintain proper operation. This
pin should be connected to VAG if not used.

The driver summing input (DSI, pin 1) may be used to con­nect an external signal, such as a DTMF dialer, to the phone
line. When applying a signal to the DSI pin, the modulator
should be squelched by bringing SQT (pin 14) to a logic high
level. DSI must be left open if not used.

In addition, the DSI pin is the inverting side of the line driv­er and allows adjustable gain with a series resistor R

DSI

(see
Figure 6). The voltage gain, AV, is determined by the
equation:

R

AV = –

R

f

DSI

where Rf ≈ 20 kΩ.

TRANSMIT LEVEL ADJUSTMENT

The power output at TxA (pin 17) is determined by the

value of resistor R

that is connected between TLA

TLA

Example: A resistor value of 20 kΩ for RDSI will provide

unity gain.

AV = – (20 kΩ/20 kΩ) = –1 .

MC145442B•MC145443B MOTOROLA
8

RxA1

CDA

V

DD

HYBRID

16

7

V

≈ 1.2 V

CDA

ac

AMP

THRESHOLD

CONTROL

V

ref

AUTO–NULLED

COMPARATOR

6 ms

RETRIGGERABLE

ONE–SHOT

SAMPLING

CLOCK

3

CD

C

CDA

0.1 µF

Figure 5. Carrier Detect Circuit

MODULATOR

OUTPUT

R0 = R

f

R

0

R

f

–

+

DSI

DSI

1

ExI

18

R

TxA
17

4 CDT

C

CDT

0.1 µF

R

V

AG

19

i

Figure 6. Line Driver Using the DSI Input

MC145442B•MC145443BMOTOROLA

9

0.1 µF

0.1 µF

+5 V

0.1 µF

R

10 Ω

DSI

20 kΩ

10 µF

DTMF

INPUT

TIP

*

RING

V

DD

0.1 µF

0.1 µF

*Line Protection Circuit.

C

DSI

0.1 µF

6

X

X

out

CD

TxD

RxD

SQT

LB

MODE

712

in

9

8

C

CDA

0.1 µF

10 kΩ

10 kΩ

10 kΩ

3.58
MHz

1

C1+

3

C1–

11

DI2

15

DO1

13

DI1

TxEN

STBY

GND

24

600 Ω

+

R

TLA

R

Tx

C

FB

0.1 µF

20

1

17
15

16

18
10
19

C

CDT

0.1 µF

TLA
DSI

TxA
RxA2

RxA1

MC145442B/3B

Exl
FB

V

AG

CDT

4

V

DD

GND CDA

Figure 7. Typical MC145442B/MC145443B Applications Circuit

17

V

DD

MC145407

19

V

CC

V

SS

C1+
C1–

Tx2

Rx1

Tx1

Rx2

Rx3

20
18

MMBZ15VDLT1X 3

10

6

8

7

9

EIA–232–D

DB–25

CONNECTOR

8

2

3

7

MC145442B•MC145443B MOTOROLA
10

P ACKAGE DIMENSIONS

P SUFFIX

PLASTIC DIP

CASE 738–03

-T-

SEATING
PLANE

-A-

1120

B

110

C

K

E

N

GF

20 PL

D

0.25 (0.010) T A

M M

SOG PACKAGE

CASE 751D–05

D

20

M

A

11

B

H10X

M

E

0.25

1

B20X

M

T

0.25

10

SAS

B

B

A

SEATING

18X

e

A1

PLANE

T

DW SUFFIX

_

h X 45

L

J 20 PL

0.25 (0.010) T B

q

C

M

M M

L

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

INCHES MILLIMETERS

MIN MINMAX MAX

DIM

A
B
C
D

E
F

G

J

K

L
M
N

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90

q

1.070

1.010

0.260

0.240

0.180

0.150

0.022

0.015

0.050 BSC

0.070

0.050

0.100 BSC

0.015

0.008

0.140

0.110

0.300 BSC
15°

0°

0.040

0.020

MILLIMETERS

0 7

__

25.66

6.10

3.81

0.39

1.27 BSC

1.27

2.54 BSC

0.21

2.80

7.62 BSC

0°

0.51

27.17

6.60

4.57

0.55

1.77

0.38

3.55

1.01

15°

MC145442B•MC145443BMOTOROLA

11

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
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Opportunity/Affirmative Action Employer.

How to reach us:
USA/EUROPE /Locations Not Listed: Motorola Literature Distribution; JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center,

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HOME PAGE: http://motorola.com/semiconductors/ 852-26668334

2 Dai King Street, T ai Po Industrial Estate, Tao Po, N.T ., Hong Kong.

MC145442B•MC145443B MOTOROLA

◊

MC145442B/D

12