Datasheet MC14543BCL, MC14543BD, MC14543BCP Datasheet (Motorola)

MOTOROLA CMOS LOGIC DATA

1

MC14543B

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" $ !

The MC14543B BCD–to–seven segment latch/decoder/driver is designed
for use with liquid crystal readouts, and is constructed with complementary
MOS (CMOS) enhancement mode d evices. The circuit provides t he
functions of a 4–bit storage latch and an 8421 BCD–to–seven segment
decoder and driver. The device has the capability to invert the logic levels of
the output combination. The phase (Ph), blanking (BI), and latch disable (LD)
inputs are used to reverse the truth table phase, blank the display , and store
a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is
applied to the Ph input of the circuit and the electrically common backplane
of the d isplay. The o utputs of the circuit are c onnected directly to the
segments of t he LC r eadout. F or o ther t ypes o f readouts, such as
light–emitting diode (LED), incandescent, gas discharge, and fluorescent
readouts, connection diagrams are given on this data sheet.

Applications include instrument (e.g., counter, DVM etc.) display driver,
computer/calculator display driver, cockpit display driver, and various clock,
watch, and timer uses.

• Latch Storage of Code

• Blanking Input

• Readout Blanking on All Illegal Input Combinations

• Direct LED (Common Anode or Cathode) Driving Capability

• Supply Voltage Range = 3.0 V to 18 V

• Capable of Driving Two Low–power TTL Loads, One Low–power

Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range

• Pin–for–Pin Replacement for CD4056A (with Pin 7 Tied to VSS).

• Chip Complexity: 207 FETs or 52 Equivalent Gates

MAXIMUM RATINGS* (Voltages referenced to V

SS

)

Rating

Symbol Value Unit

DC Supply Voltage V

DD

– 0.5 to + 18 V

Input Voltage, All Inputs V

in

– 0.5 to VDD + 0.5 V

DC Input Current per Pin I

in

± 10 mA

Operating Temperature Range T

A

– 55 to + 125

_

C

Power Dissipation, per Package† P

D

500 mW

Storage Temperature Range T

stg

– 65 to + 150

_

C

Maximum Continuous Output Drive
Current (Source or Sink) per Output

I

OHmax

I

OLmax

10 mA

Maximum Continuous Output Power*
(Source or Sink) per Output

P

OHmax

P

OLmax

70 mW

*P

OHmax

= IOH (VOH – VDD) and P

OLmax

= IOL (VOL – VSS)
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

TRUTH TABLE

Inputs Outputs

LD BI Ph* D C B A a b c d e f g Display

X 1 0 X X X X 0 0 0 0 0 0 0 Blank
1 0 0 0 0 0 0 1 1 1 1 1 1 0 0

1 0 0 0 0 0 1 0 1 1 0 0 0 0 1
1 0 0 0 0 1 0 1 1 0 1 1 0 1 2
1 0 0 0 0 1 1 1 1 1 1 0 0 1 3

1 0 0 0 1 0 0 0 1 1 0 0 1 1 4
1 0 0 0 1 0 1 1 0 1 1 0 1 1 5
1 0 0 0 1 1 0 1 0 1 1 1 1 1 6
1 0 0 0 1 1 1 1 1 1 0 0 0 0 7

1 0 0 1 0 0 0 1 1 1 1 1 1 1 8
1 0 0 1 0 0 1 1 1 1 1 0 1 1 9
1 0 0 1 0 1 0 0 0 0 0 0 0 0 Blank
1 0 0 1 0 1 1 0 0 0 0 0 0 0 Blank

1 0 0 1 1 0 0 0 0 0 0 0 0 0 Blank
1 0 0 1 1 0 1 0 0 0 0 0 0 0 Blank
1 0 0 1 1 1 0 0 0 0 0 0 0 0 Blank
1 0 0 1 1 1 1 0 0 0 0 0 0 0 Blank

0 0 0 X X X X ** **
† † † † Inverse of Output Display

Combinations as above
Above

X = Don’t care
† = Above Combinations
* = For liquid crystal readouts, apply a square wave to Ph

For common cathode LED readouts, select Ph = 0
For common anode LED readouts, select Ph = 1

** = Depends upon the BCD code previously applied when

LD = 1



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3
1/94



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

MOTOROLA CMOS LOGIC DATAMC14543B

2

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

DD

– 55_C 25_C 125_C

Characteristic

Symbol

DD

Vdc

Min Max Min Typ # Max Min Max

Unit

Output Voltage “0” Level

Vin = VDD or 0

V

OL

5.0
10
15

—
—
—

0.05

0.05

0.05

—
—
—

0
0
0

0.05

0.05

0.05

—
—
—

0.05

0.05

0.05

Vdc

“1” Level

Vin = 0 or V

DD

V

OH

5.0
10
15

4.95

9.95

14.95

—
—
—

4.95

9.95

14.95

5.0
10
15

—
—
—

4.95

9.95

14.95

—
—
—

Vdc

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)

V

IL

5.0
10
15

—
—
—

1.5

3.0

4.0

—
—
—

2.25

4.50

6.75

1.5

3.0

4.0

—
—
—

1.5

3.0

4.0

Vdc

“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

V

IH

5.0
10
15

3.5

7.0
11

—
—
—

3.5

7.0
11

2.75

5.50

8.25

—
—
—

3.5

7.0
11

—
—
—

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 0.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)

I

OH

5.0

5.0
10
10
15

– 3.0

– 0.64

—
– 1.6
– 4.2

—
—
—
—
—

– 2.4

– 0.51

—
– 1.3
– 3.4

– 4.2
– 0.88
– 10.1
– 2.25

– 8.8

—
—
—
—
—

– 1.7

– 0.36

—
– 0.9
– 2.4

—
—
—
—

mAdc

(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 9.5 Vdc)
(VOL = 1.5 Vdc)

I

OL

5.0
10
10
15

0.64

1.6
—

4.2

—
—
—
—

0.51

1.3
—

3.4

0.88

2.25

10.1

8.8

—
—
—
—

0.36

0.9
—

2.4

—
—
—

mAdc

Input Current I

in

15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc

Input Capacitance C

in

— — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package) Vin = 0 or VDD,
I

out

= 0 µA

I

DD

5.0
10
15

—
—
—

5.0
10
20

—
—
—

0.005

0.010

0.015

5.0
10
20

—
—
—

150
300
600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)

I

T

5.0
10
15

IT = (1.6 µA/kHz) f + I

DD

IT = (3.1 µA/kHz) f + I

DD

IT = (4.7 µA/kHz) f + I

DD

µAdc

#Noise immunity specified for worst–case input combination.

Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V

= 2.0 V min @ VDD = 10 V
= 2.5 V min @ VDD = 15 V

†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency.
**The formulas given are for the typical characteristics only at 25_C.

MOTOROLA CMOS LOGIC DATA

3

MC14543B

SWITCHING CHARACTERISTICS* (C

L

= 50 pF, TA = 25_C)

Characteristic

Symbol V

DD

Min Typ Max Unit

Output Rise Time

t

TLH

= (3.0 ns/pF) CL + 30 ns

t

TLH

= (1.5 ns/pF) CL + 15 ns

t

TLH

= (1.1 ns/pF) CL + 10 ns

t

TLH

5.0
10
15

—
—
—

100

50
40

200
100

80

ns

Output Fall Time

t

THL

= (1.5 ns/pF) CL + 25 ns

t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

THL

= (0.55 ns/pF) CL + 12.5 ns

t

THL

5.0
10
15

—
—
—

100

50
40

200
100

80

ns

Turn–Off Delay Time

t

PLH

= (1.7 ns/pF) CL + 520 ns

t

PLH

= (0.66 ns/pF) CL + 217 ns

t

PLH

= (0.5 ns/pF) CL + 160 ns

t

PLH

5.0
10
15

—
—
—

605
250
185

1210

500
370

ns

Turn–On Delay Time

t

PHL

= (1.7 ns/pF) CL + 420 ns

t

PHL

= (0.66 ns/pF) CL + 172 ns

t

PHL

= (0.5 ns/pF) CL + 130 ns

t

PHL

5.0
10
15

—
—
—

505
205
155

1650

660
495

ns

Setup Time t

su

5.0
10
15

350
450
500

—
—
—

ns

Hold Time t

h

5.0
10
15

40
30
20

—
—
—

ns

Latch Disable Pulse Width (Strobing Data) t

WH

5.0
10
15

250
100

80

125

50
40

—
—
—

ns

*The formulas given are for the typical characteristics only.

LOGIC DIAGRAM

VDD = PIN 16

VSS = PIN 8

B 3

LD 1

D 4

C 2

A 5

PHASE 6

14 g

15 f

13 e

12 d

11 c

10 b

9 a

BI 7

MOTOROLA CMOS LOGIC DATAMC14543B

4

Figure 1. Typical Output Source

Characteristics

Figure 2. Typical Output Sink

Characteristics

–24

–18

–12

–6.0

0

I

OH

, SOURCE CURRENT (mAdc)

(VOH – VDD), SOURCE DEVICE VOLTAGE (Vdc)

–16 –12 –8.0 – 4.0 0

VDD = 5.0 Vdc

P

OHmax

= 70 mWdc

VDD = 10 Vdc

VDD = 15 Vdc

VSS = 0 Vdc

0

6.0

12

18

24

I

OL

, SINK CURRENT (mAdc)

(VOL – VSS), SINK DEVICE VOLTAGE (Vdc)

0 4.0 8.0 12 16

VDD = 15 Vdc

VDD = 10 Vdc

VDD = 5.0 Vdc

VSS = 0 Vdc

P

OLmax

= 70 mWdc

Figure 3. Dynamic Power Dissipation

Signal Waveforms

Inputs BI and Ph low, and Inputs D and LD high.
f in respect to a system clock.

Figure 4. Dynamic Signal Waveforms

(a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high.

(b) Inputs D, Ph, and BI low, and Inputs A and B high.

(c) Data DCBA strobed into latches

20 ns

20 ns

V

DD

V

SS

V

OH

V

OL

10%

50%

90%

1
2f

50% DUTY CYCLE

A, B, AND C

ANY OUTPUT

All outputs connected to respective CL loads.

20 ns 20 ns

90%

10%

50%

t

PHL

t

PLH

90%

50%

10%

V

DD

V

SS

V

OH

V

OL

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

V

DD

V

SS

t

THL

t

TLH

C

g

LD

C

g

LD

20 ns

90%

50%

10%

50% 50%

t

h

t

su

50%

t

WH

MOTOROLA CMOS LOGIC DATA

5

MC14543B

CONNECTIONS TO VARIOUS DISPLAY READOUTS

LIQUID CRYSTAL (LC) READOUT

LIGHT EMITTING DIODE (LED) READOUT

INCANDESCENT READOUT

NOTE: Bipolar transistors may be added for gain (for VDD v 10 V or I

out

≥ 10 mA).

GAS DISCHARGE READOUT

PIN ASSIGNMENT CONNECTIONS TO SEGMENTS

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

d

e

g

f

V

DD

a

b

c

D

B

C

LD

V

SS

BI

PH

A

SQUARE WAVE

(VSS TO VDD)

COMMON
BACKPLANE

ONE OF SEVEN SEGMENTS

MC14543B

OUTPUT

Ph

MC14543B

OUTPUT

Ph

V

SS

APPROPRIATE

VOLTAGE

MC14543B

OUTPUT

Ph

V

SS

COMMON

CATHODE LED

COMMON

ANODE LED

V

DD

MC14543B

OUTPUT

Ph

V

DD

MC14543B

OUTPUT

Ph

APPROPRIATE

VOLTAGE

V

SS

VDD = PIN 16

VSS = PIN 8

0 1 2 3 4 5 6 7 8 9

DISPLAY

a

b

c

d

e

f g

MOTOROLA CMOS LOGIC DATAMC14543B

6

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC

J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

–A–

–B–

–T–

F

E

G

N

K

C

SEATING
PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATA

7

MC14543B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

_ _ _ _

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MC14543B/D

*MC14543B/D*

◊