Datasheet MC14541BCP Specification

MC14541B

Programmable Timer

The MC14541B programmable timer consists of a 16−stage binary counter, an integrated oscillator for use with an external capacitor and two resistors, an automatic power−on reset circuit, and output control logic.

Timing is initialized by turning on power, whereupon the power−on reset is enabled and initializes the counter, within the specified V range. With the power already on, an external reset pulse can be applied. Upon release of the initial reset command, the oscillator will oscillate with a frequency determined by the external RC network. The 16−stage counter divides the oscillator frequency (f stage frequency being f

Features

• Available Outputs 2

/2n.

osc

8

, 210, 213 or 2

16

) with the n

osc

• Increments on Positive Edge Clock Transitions

• Built−in Low Power RC Oscillator (± 2% accuracy over temperature

range and ± 20% supply and ± 3% over processing at < 10 kHz)

• Oscillator May Be Bypassed if External Clock Is Available

(Apply external clock to Pin 3)

• External Master Reset Totally Independent of Automatic Reset

Operation

• Operates as 2

n

Frequency Divider or Single Transition Timer

• Q/Q Select Provides Output Logic Level Flexibility

• Reset (auto or master) Disables Oscillator During Resetting to

Provide No Active Power Dissipation

• Clock Conditioning Circuit Permits Operation with Very Slow Clock

Rise and Fall Times

• Automatic Reset Initializes All Counters On Power Up

• Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset

SS

DD

)

Supply Voltage Range = Disabled (Pin 5 = V Supply Voltage Range = 8.5 Vdc to 18 Vdc with Auto Reset Supply Voltage Range = Enabled (Pin 5 = V

• These Devices are Pb−Free and are RoHS Compliant

PIN ASSIGNMENT

V

14

DD

B

13

A

12

NC

11

MODE

105

9

SEL

Q/Q

8

Q

MR

V

R

C

R

NC

AR

1

tc

2

tc

3

S

4

6

7

SS

DD

th

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MARKING

DIAGRAMS

14

PDIP−14

P SUFFIX

CASE 646

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14 DT SUFFIX

CASE 948G

SOEIAJ−14

F SUFFIX

CASE 965

A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package

(Note: Microdot may be in either location)

MC14541BCP

AWLYYWWG

1

14

14541BG

AWLYWW

1

14

541B

ALYWG

G

1

14

MC14541B

ALYWG

1

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

NC = NO CONNECTION

June, 2011 − Rev. 12

1 Publication Order Number:

MC14541B/D

MC14541B

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

Vin, V

I

out

P

T

DD

out

in

D

A

stg

L

DC Supply Voltage Range −0.5 to +18.0 V

Input or Output Voltage Range, (DC or Transient) −0.5 to VDD + 0.5 V

Input Current (DC or Transient) ± 10 (per Pin) mA

Output Current (DC or Transient) ± 45 (per Pin) mA

Power Dissipation, per Package (Note 1) 500 mW

Ambient Temperature Range −55 to +125 °C

Storage Temperature Range −65 to +150 °C

Lead Temperature, (8−Second Soldering) 260 °C

)

SS

Parameter Value Unit

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

ORDERING INFORMATION

Device Package Shipping

MC14541BCPG PDIP−14

(Pb−Free)

MC14541BDG SOIC−14

(Pb−Free)

500 Units / Rail

55 Units / Rail

MC14541BDR2G SOIC−14

(Pb−Free)

MC14541BDTR2G

TSSOP−14*

MC14541BFG SOEIAJ−14

(Pb−Free)

MC14541BFELG SOEIAJ−14

(Pb−Free)

2500 / Tape & Reel

50 Units / Rail

2000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

†

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2

MC14541B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

V

Characteristic

Symbol

Output Voltage “0” Level

V

= VDD or 0

in

“1” Level

V

= 0 or V

in

DD

Input Voltage “0” Level

(V

= 4.5 or 0.5 Vdc)

O

= 9.0 or 1.0 Vdc)

(V

O

(V

= 13.5 or 1.5 Vdc)

O

“1” Level

(V

= 0.5 or 4.5 Vdc)

O

= 1.0 or 9.0 Vdc)

(V

O

(V

= 1.5 or 13.5 Vdc)

O

Output Drive Current

(V

= 2.5 Vdc) Source

OH

= 9.5 Vdc)

(V

OH

(V

= 13.5 Vdc)

OH

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

OL

= 1.5 Vdc)

(V

OL

Input Current I

Input Capacitance

(V

= 0)

in

Quiescent Current

(Pin 5 is High)

Auto Reset Disabled

Auto Reset Quiescent Current

(Pin 5 is low)

Supply Current (Notes 3 & 4)

(Dynamic plus Quiescent)

V

I

C

I

DDR

OL

OH

OL

in

DD

I

D

IL

IH

in

DD

Vdc

Min Max Min Typ

5.0 10 15

4.95

9.95

14.95

5.0 10 15

3.5

7.0 11

– 4.19 – 7.96 – 16.3

1.93

4.96

19.3

15 − ± 0.1 − ± 0.00001 ± 0.1 − ± 1.0 mAdc

− − − − 5.0 7.5 − − pF

5.0 10 15

10 15

5.0 10 15

)

SS

− 55_C 25_C 125_C

Max Min Max

(Note 2)

−

0.05

−

0.05

−

0.05

−

1.5

3.0

4.0

−

5.0 10 20

250 500

−

4.95

9.95

14.95

−

3.5

7.0 11

– 3.38 – 6.42 – 13.2

1.56

4.0

15.6

−

0 0 0

5.0 10 15

2.25

4.50

6.75

2.75

5.50

8.25

– 6.75 – 12.83 – 26.33

3.12

8.0

31.2

0.005

0.010

0.015

30 82

ID = (0.4 mA/kHz) f + I ID = (0.8 mA/kHz) f + I ID = (1.2 mA/kHz) f + I

0.05

−

1.5

3.0

4.0

−

5.0 10 20

250 500

DD

−

4.95

9.95

14.95

−

3.5

7.0 11

– 2.37 – 4.49

− 9.24

1.09

2.8

10.9

−

0.05

150 300 600

1500 2000

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. When using the on chip oscillator the total supply current (in mAdc) becomes: I in Volts DC, and f in kHz. (see Fig. 3) Dissipation during power−on with automatic reset enabled is typically 50 mA @ VDD = 10 Vdc.

V

DD

= ID + 2 Ctc VDD f x 10–3 where ID is in mA, Ctc is in pF,

T

1.5

3.0

4.0

Unit

Vdc

−

Vdc

−

Vdc

−

mAdc

−

mAdc

−

mAdc

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3

MC14541B

SWITCHING CHARACTERISTICS (Note 5) (C

Characteristic

= 50 pF, T

L

= 25_C)

A

Symbol V

DD

Min Typ

Max Unit

(Note 6)

Output Rise and Fall Time

t

, t t t

TLH

= (1.5 ns/pF) CL + 25 ns

THL

, t

= (0.75 ns/pF) CL + 12.5 ns

THL

, t

= (0.55 ns/pF) CL + 9.5 ns

THL

Propagation Delay, Clock to Q (28 Output)

t

, t t t

PLH

= (1.7 ns/pF) CL + 3415 ns

PHL

, t

= (0.66 ns/pF) CL + 1217 ns

PHL

, t

= (0.5 ns/pF) CL + 875 ns

PHL

Propagation Delay, Clock to Q (216 Output)

t

, t t t

PHL

= (1.7 ns/pF) CL + 5915 ns

PLH

, t

= (0.66 ns/pF) CL + 3467 ns

PLH

, t

= (0.5 ns/pF) CL + 2475 ns

PLH

Clock Pulse Width t

Clock Pulse Frequency (50% Duty Cycle) f

MR Pulse Width t

Master Reset Removal Time t

t

TLH

t

THL

t

PLH

t

PHL

t

PHL

t

PLH

WH(cl)

cl

WH(R)

rem

,

5.0 10 15

−

900 300 225

−

900 300 225

420 200 200

100

50 40

3.5

1.25

0.9

6.0

3.5

2.5

300 100

85

1.5

4.0

6.0

300 100

85

210 100 100

200 100

80

10.5

3.8

2.9

18 10

7.5

−

0.75

2.0

3.0

−

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

ns

ms

ns

MHz

ns

V

DD

PULSE

GENERATOR

R

S

AR

SELECT

Q/Q

MODE

A

Q

C B MR

V

SS

(Rtc AND Ctc OUTPUTS ARE LEFT OPEN)

20 ns 20 ns

90%

50%

10%

50%

DUTY CYCLE

Figure 1. Power Dissipation Test Circuit

and Waveform

V

DD

PULSE

GENERATOR

L

R

S

AR

Q/Q

MODE

A

SELECT

Q

C

L

B MR

V

SS

20 ns

90%

50%

t

PLH

10%

90%

50%

t

TLH

10%

R

S

Q

20 ns

50%

t

PHL

t

THL

Figure 2. Switching Time Test Circuit

and Waveforms

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4

A12 B13

R

tc

C

tc

R

MC14541B

EXPANDED BLOCK DIAGRAM

1 OF 4

MUX

1

OSC

2

3

S

RESET

8-STAGE

C

COUNTER

RESET

8

2

10213216

2

C

8-STAGE

COUNTER

RESET

8Q

AUTO RESET

5

POWER-ON

RESET

MASTER RESET

VDD = PIN 14

V

= PIN 7

SS

FREQUENCY SELECTION TABLE

Number of

Counter Stages

A B

0 0 13 8192

0 1 10 1024

1 0 8 256

1 1 16 65536

n

6

10

MODE

9

Q/Q

SELECT

TRUTH TABLE

Count

n

2

0 1

Auto Reset, 5 Auto Reset

Operating

Master Reset, 6 Timer Operational Master Reset On

Q/Q,9Output Initially Low

After Reset

Mode, 10 Single Cycle Mode Recycle Mode

State

Auto Reset Disabled

Output Initially High After Reset

3

INTERNAL

RESET

21

C

tc

R

S

R

TC

Figure 3. Oscillator Circuit Using RC Configuration

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5

TO CLOCK

CIRCUIT

MC14541B

TYPICAL RC OSCILLATOR CHARACTERISTICS

8.0

4.0

0

-4.0

-8.0

-12

FREQUENCY DEVIATION (%)

-16

= 56 kW,

R

TC

C = 1000 pF

RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C RS = 120 kW, f = 7.8 kHz @ VDD = 10 V, TA = 25°C

T

, AMBIENT TEMPERATURE (°C)

A

VDD = 15 V

10 V

5.0 V

1251007550250-25-55

Figure 4. RC Oscillator Stability

OPERATING CHARACTERISTICS

With Auto Reset pin set to a “0” the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the Master Reset pin is set to a “1”. Both types of reset will result in synchronously resetting all counter stages independent of counter state. Auto Reset pin when set to a “1” provides a low power operation.

The RC oscillator as shown in Figure 3 will oscillate with a frequency determined by the external RC network i.e.,

2.3 R

1

tc

if (1 kHz v f v 100 kHz)

tcCtc

where RS ≥ 10 kW

f =

and RS ≈ 2 R

The time select inputs (A and B) provide a two−bit address to output any one of four counter stages (2

16

2

). The 2n counts as shown in the Frequency Selection Table represents the Q output of the N When A is “1”, 2

16

is selected for both states of B. However,

8

, 210, 213 and

th

stage of the counter.

100

50

20

10

5.0 f AS A FUNCTION

2.0

1.0

0.5

0.2

f, OSCILLATOR FREQUENCY (kHz)

0.1

0.0001 0.001 0.01 0.1

OF C

(R

= 56 kW)

TC

(R

= 120 kW)

S

1.0 k 10 k 100 k 1.0 m RTC, RESISTANCE (OHMS)

C, CAPACITANCE (mF)

VDD = 10 V

f AS A FUNCTION

OF R

TC

(C = 1000 pF)

≈ 2RTC)

(R

S

Figure 5. RC Oscillator Frequency as a

Function of R

and C

tc

when B is “0”, normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 2

The Q/Q

select output control pin provides for a choice of

8

).

output level. When the counter is in a reset condition and Q/Q

select pin is set to a “0” the Q output is a “0”,

correspondingly when Q/Q

select pin is set to a “1” the Q

output is a “1”.

When the mode control pin is set to a “1”, the selected count is continually transmitted to the output. But, with mode pin “0” and after a reset condition the R

flip−flop (see

S

Expanded Block Diagram) resets, counting commences, and after 2 output to change state. Hence, after another 2

n−1

counts the RS flip−flop sets which causes the

n−1

counts the output will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation.

DIGITAL TIMER APPLICATION

R

tc

C

tc

R

S

NC

INPUT

t

MR

1

2

3

4

AR

5

MR

6

78

14

13

12

11

MODE

10

Q/Q

9

V

DD

B

A

N.C.

V

DD

OUTPUT

When Master Reset (MR) receives a positive pulse, the internal counters and latch are reset. The Q output goes high and remains high until the selected (via A and B) number of clock pulses are counted, the Q output then goes low and remains low until another input pulse is received.

This “one shot” is fully retriggerable and as accurate as the input frequency. An external clock can be used (pin 3 is the clock input, pins 1 and 2 are outputs) if additional accuracy is needed.

Notice that a setup time equal to the desired pulse width output is required immediately following initial power up, during which time Q output will be high.

t + t

MR

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6

−T−

SEATING PLANE

14 8

17

N

HG

MC14541B

PACKAGE DIMENSIONS

PDIP−14

CASE 646−06

ISSUE P

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

B

A

F

L

C

D

14 PL

0.13 (0.005)

K

J

M

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.715 0.770 18.16 19.56 B 0.240 0.260 6.10 6.60 C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L

0.290 0.310 7.37 7.87

M −−− 10 −−− 10 N 0.015 0.039 0.38 1.01

MILLIMETERSINCHES

__

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7

−T−

SEATING PLANE

MC14541B

PACKAGE DIMENSIONS

SOIC−14

CASE 751A−03

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER

−A−

14

1

8

−B−

7

P

7 PL

0.25 (0.010) B

M

G

F

J

D 14 PL

0.25 (0.010) A

M

T

R

X 45

C

K

S

B

S

_

M

SOLDERING FOOTPRINT*

7X

7.04

1

14X

0.58

14X

1.52

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 8.55 8.75 0.337 0.344 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7

__ __

P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

1.27 PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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8

MC14541B

PACKAGE DIMENSIONS

TSSOP−14

CASE 948G−01

ISSUE B

−T−

0.10 (0.004)

SEATING PLANE

14X REFK

S

U

T

S

N

0.25 (0.010)

U0.15 (0.006) T

S

2X L/2

0.10 (0.004) V

14

M

8

M

L

PIN 1 IDENT.

1

S

U0.15 (0.006) T

A

−V−

B

N

−U− F

7

DETAIL E

K

K1

J

J1

SECTION N−N

C

D

G

H

DETAIL E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC

−W−

H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

____

INCHESMILLIMETERS

SOLDERING FOOTPRINT*

7.06

1

14X

0.36

14X

1.26

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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9

0.65

PITCH

14 8

1

Z

D

e

b

0.13 (0.005)

M

E

7

A

0.10 (0.004)

H

A

1

E

VIEW P

MC14541B

PACKAGE DIMENSIONS

SOEIAJ−14

CASE 965−01

ISSUE B

L

E

Q

1

_

M

L

DETAIL P

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

--- 2.05 --- 0.081

c

A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.10 0.20 0.004 0.008

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L

1.10 1.50 0.043 0.059

E

0

M

_

Q

0.70 0.90 0.028 0.035

1

--- 1.42 --- 0.056

Z

INCHES

10

_

10

0

_

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MC14541B/D

10

Datasheet MC14541BCP Specification

Specifications and Main Features

Frequently Asked Questions

User Manual