Datasheet MC14541BCP, MC14541BCL, MC14541BD Datasheet (Motorola)

MOTOROLA CMOS LOGIC DATA

1

MC14541B

 

The MC14541B programmable timer consists of a 1 6–stage binary
counter, an integrated oscillator for use with an external capacitor and two
resistors, an automatic power–on reset circuit, and output control logic.

Timing is initialized by turning on power , whereupon the power–on reset is
enabled and initializes the counter, within the specified VDD range. With the
power already on, an external reset pulse can be applied. Upon release of
the initial reset command, the oscillator will o scillate with a frequency
determined by the external RC network. The 16–stage counter divides the
oscillator frequency (f

osc

) with the nth stage frequency being f

osc

/2n.

• Available Outputs 28, 210, 213 or 2

16

• Increments on Positive Edge Clock Transitions

• Built–in Low Power RC Oscillator (± 2% accuracy over temperature

range and ± 20% supply and ± 3% over processing at < 10 kHz)

• Oscillator May Be Bypassed if External Clock Is Available (Apply

external clock to Pin 3)

• External Master Reset Totally Independent of Automatic Reset

Operation

• Operates as 2n Frequency Divider or Single Transition Timer

• Q/Q

Select Provides Output Logic Level Flexibility

• Reset (auto or master) Disables Oscillator During Resetting to Provide

No Active Power Dissipation

• Clock Conditioning Circuit Permits Operation with Very Slow Clock Rise

and Fall Times

• Automatic Reset Initializes All Counters On Power Up

• Supply Voltage Range = 3.0 Vdc to 18 Vdc with Auto Reset

Disabled (Pin 5 = VDD)

= 8.5 Vdc to 18 Vdc with Auto Reset

Enabled (Pin 5 = VSS)

MAXIMUM RATINGS* (Voltages Referenced to V

SS

)

Symbol

Parameter

Value

Unit

V

DD

DC Supply Voltage

– 0.5 to + 18.0

V

Vin, V

out

Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

V

I

in

Input Current (DC or Transient), per Pin

± 10

mA

I

out

Output Current (DC or Transient), per Pin

± 45

mA

P

D

Power Dissipation, per Package†

500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature (8–Second Soldering)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3
1/94



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

PIN ASSIGNMENT

NC = NO CONNECTION

11

12

13

14

8

9

105

4

3

2

1

7

6

MODE

NC

A

B

V

DD

Q

Q/Q

SEL

NC

R

S

C

tc

R

tc

V

SS

MR

AR

MOTOROLA CMOS LOGIC DATAMC14541B

2

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

DD

– 55_C 25_C 125_C

Characteristic

Symbol

DD

Vdc

Min Max Min Typ # Max Min Max

Unit

Output Voltage “0” Level

Vin = VDD or 0

V

OL

5.0
10
15

—
—
—

0.05

0.05

0.05

—
—
—

0
0
0

0.05

0.05

0.05

—
—
—

0.05

0.05

0.05

Vdc

“1” Level

Vin = 0 or V

DD

V

OH

5.0
10
15

4.95

9.95

14.95

—
—
—

4.95

9.95

14.95

5.0
10
15

—
—
—

4.95

9.95

14.95

—
—
—

Vdc

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)

V

IL

5.0
10
15

—
—
—

1.5

3.0

4.0

—
—
—

2.25

4.50

6.75

1.5

3.0

4.0

—
—
—

1.5

3.0

4.0

Vdc

“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

V

IH

5.0
10
15

3.5

7.0
11

—
—
—

3.5

7.0
11

2.75

5.50

8.25

—
—
—

3.5

7.0
11

—
—
—

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)

I

OH

5.0
10
15

– 7.96
– 4.19
– 16.3

—
—
—

– 6.42
– 3.38
– 13.2

– 12.83

– 6.75

– 26.33

—
—
—

– 4.49
– 2.37
– 9.24

—
—
—

mAdc

(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

I

OL

5.0
10
15

1.93

4.96

19.3

—
—
—

1.56

4.0

15.6

3.12

8.0

31.2

—
—
—

1.09

2.8

10.9

—
—
—

mAdc

Input Current I

in

15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance

(Vin = 0)

C

in

— — — — 5.0 7.5 — — pF

Quiescent Current

(Pin 5 is High)

Auto Reset Disabled

I

DD

5.0
10
15

—
—
—

5.0
10
20

—
—
—

0.005

0.010

0.015

5.0
10
20

—
—
—

150
300
600

µAdc

Auto Reset Quiescent Current

(Pin 5 is low)

I

DDR

10
15

—
—

250
500

—
—

30
82

250
500

—
—

1500
2000

µAdc

Supply Current**†

(Dynamic plus Quiescent)

I

D

5.0
10
15

ID = (0.4 µA/kHz) f + I

DD

ID = (0.8 µA/kHz) f + I

DD

ID = (1.2 µA/kHz) f + I

DD

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†When using the on chip oscillator the total supply current (in µAdc) becomes: IT = ID + 2 Ctc VDD f x 10–3 where ID is in µA, Ctc is in pF,

VDD in Volts DC, and f in kHz. (see Fig. 3) Dissipation during power–on with automatic reset enabled is typically 50 µA @ VDD = 10 Vdc.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA

3

MC14541B

SWITCHING CHARACTERISTICS* (C

L

= 50 pF, TA = 25_C)

Characteristic

Symbol V

DD

Min Typ # Max Unit

Output Rise and Fall Time

t

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

t

TLH

,

t

THL

5.0
10
15

—
—
—

100

50
40

200
100

80

ns

Propagation Delay, Clock to Q (28 Output)

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 3415 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 1217 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 875 ns

t

PLH

t

PHL

5.0
10
15

—
—
—

3.5

1.25

0.9

10.5

3.8

2.9

µs

Propagation Delay, Clock to Q (216 Output)

t

PHL

, t

PLH

= (1.7 ns/pF) CL + 5915 ns

t

PHL

, t

PLH

= (0.66 ns/pF) CL + 3467 ns

t

PHL

, t

PLH

= (0.5 ns/pF) CL + 2475 ns

t

PHL

t

PLH

5.0
10
15

—
—
—

6.0

3.5

2.5

18
10

7.5

µs

Clock Pulse Width t

WH(cl)

5.0
10
15

900
300
225

300
100

85

—
—
—

ns

Clock Pulse Frequency (50% Duty Cycle) f

cl

5.0
10
15

—
—
—

1.5

4.0

6.0

0.75

2.0

3.0

MHz

MR Pulse Width t

WH(R)

5.0
10
15

900
300
225

300
100

85

—
—
—

ns

Master Reset Removal Time t

rem

5.0
10
15

420
200
200

210
100
100

—
—
—

ns

*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Power Dissipation Test Circuit

and Waveform

Figure 2. Switching Time Test Circuit

and Waveforms

PULSE

GENERATOR

V

DD

C

L

Q

R

S

AR
Q/Q

SELECT
MODE
A
B
MR

V

SS

20 ns 20 ns

90%

50%

10%

50%

DUTY CYCLE

(Rtc AND Ctc OUTPUTS ARE LEFT OPEN)

PULSE

GENERATOR

V

DD

R

S

AR
Q/Q

SELECT
MODE
A
B
MR

V

SS

C

L

Q

20 ns

90%

50%

20 ns

10%

R

S

Q

t

PLH

50%

90%

50%

10%

50%

t

TLH

t

THL

t

PHL

MOTOROLA CMOS LOGIC DATAMC14541B

4

EXPANDED BLOCK DIAGRAM

A 12
B 13

Rtc1
Ctc2

RS3

5

AUTO RESET

OSC

RESET

C

2

8

8–STAGE

COUNTER

RESET

POWER–ON

RESET

6

MASTER RESET

2102132

16

C

8–STAGE

COUNTER

RESET

1 OF 4

MUX

10

MODE

9

Q/Q

SELECT

8 Q

VDD = PIN 14

VSS = PIN 7

FREQUENCY SELECTION TABLE

A B

Number of

Counter Stages

n

Count

2

n

0 0 13 8192
0 1 10 1024
1 0 8 256
1 1 16 65536

TRUTH TABLE

State

Pin

0 1

Auto Reset, 5 Auto Reset Operating Auto Reset Disabled
Master Reset, 6 Timer Operational Master Reset On
Q/Q, 9 Output Initially Low

After Reset

Output Initially High
After Reset

Mode, 10 Single Cycle Mode Recycle Mode

Figure 3. Oscillator Circuit Using RC Configuration

3

R

S

R

TC

C

tc

2 1

TO CLOCK

CIRCUIT

INTERNAL

RESET

MOTOROLA CMOS LOGIC DATA

5

MC14541B

TYPICAL RC OSCILLATOR CHARACTERISTICS

Figure 4. RC Oscillator Stability

Figure 5. RC Oscillator Frequency as a

Function of Rtc and C

tc

8.0

4.0

0

–4.0

–8.0

–12

–16

1251007550250–25–55

TA, AMBIENT TEMPERATURE (

°

C)

FREQUENCY DEVIATION (%)

VDD = 15 V

10 V

5.0 V

RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C
RS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C

RTC = 56 k

Ω

,

C = 1000 pF

100

0.1

0.2

0.5

1.0

2.0

5.0

10

20

50

1.0 k 10 k 100 k 1.0 m

f, OSCILLATOR FREQUENCY (kHz)

RTC, RESISTANCE (OHMS)

0.0001 0.001 0.01 0.1
C, CAPACITANCE (

µ

F)

VDD = 10 V

f AS A FUNCTION

OF R

TC

(C = 1000 pF)

(RS

≈

2RTC)

f AS A FUNCTION

OF C
(RTC = 56 kΩ)
(RS = 120 k

Ω

)

OPERATING CHARACTERISTICS

With Auto Reset pin set to a “0” the counter circuit is initial­ized by t urning on power. Or with p ower already on, the
counter circuit is reset when the Master Reset pin is set to a
“1”. Both types of reset will result in synchronously resetting
all counter stages independent of counter state. Auto Reset
pin when set to a “1” provides a low power operation.

The RC oscillator as shown in Figure 3 will oscillate with a
frequency determined by the external RC network i.e.,

if (1 kHz v f v 100 kHz)

2.3 RtcC

tc

1

f =

and RS ≈ 2 R

tc

where RS ≥ 10 kΩ

The time select inputs (A and B) provide a two–bit address
to output any one of four counter stages (28, 210, 213 and

216). The 2n counts as shown in the Frequency Selection
Table represents the Q output of the Nth stage of the counter .
When A is “1”, 216 is selected for both states of B. However,

when B is “0”, normal counting is interrupted a nd the 9th
counter stage receives its clock directly from the oscillator
(i.e., effectively outputting 28).

The Q/Q

select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q

select pin is set to a “0” the Q output is a “0”, corre-

spondingly when Q/Q

select pin is set to a “1” the Q output is

a “1”.

When the mode control pin is set to a “1”, the selected
count is continually transmitted to the output. But, with mode
pin “0” and after a reset condition the RS flip–flop (see Ex­panded Block Diagram) resets, counting commences, and
after 2

n–1

counts the RS flip–flop sets which causes the out-

put to change state. Hence, after another 2

n–1

counts the
output will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to reset
the single cycle operation.

DIGITAL TIMER APPLICATION

R

tc

C

tc

NC

R

S

AR
MR

INPUT

t

MR

V

DD
B
A

N.C.

OUTPUT

V

DD

MODE

Q/Q

t + t

MR

1
2
3
4
5
6
7 8

9

10

11

12

13

14

When Master Reset (MR) receives a positive pulse, the in­ternal counters and latch are reset. The Q output goes high
and remains high until the selected (via A and B) number of
clock pulses are counted, the Q output then goes low and re­mains low until another input pulse is received.

This “one shot” is fully retriggerable and as accurate as the
input frequency. An external clock can be used (pin 3 is the
clock input, pins 1 and 2 are outputs) if additional accuracy is
needed.

Notice that a setup time equal to the desired pulse width
output is required immediately following initial power up, dur­ing which time Q output will be high.

MOTOROLA CMOS LOGIC DATAMC14541B

6

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

–A–

–B–

–T–

F

E

G

N

K

C

SEATING
PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATA

7

MC14541B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

_ _ _ _

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
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MC14541B/D

*MC14541B/D*

◊