MC145407MOTOROLA
5
Vin = ± 2
V
6
8
10
15
13
11
4 2
17 19
VDDV
CC
DI1
DI2
DI3
V
SS
GND
Tx3
Tx2
Tx1
R
out
=
V
in
I
Figure 1. Power–Off Source Resistance
Figure 2. Switching Characteristics
Figure 3. Slew Rate Characterization
DRIVERS
DI1 – DI3
3 V
0 V
V
OH
V
OL
Tx1 – Tx3
t
PLH
t
PHL
50%
t
f
t
r
10%
90%
RECEIVERS
Rx1 – Rx3
DO1 – DO3
+ 3 V
0 V
V
OH
V
OL
t
PLH
t
PHL
t
f
t
r
50%
DRIVERS
Tx1 – Tx3
90%
50%
3 V
– 3 V
3 V
– 3 V
t
SHL
t
SLH
SLEW RATE (SR) =
–
3 V – (3 V)OR3 V – ( – 3 V)
t
SLH
t
SHL
10%
PIN DESCRIPTIONS
V
CC
Digital Power Supply (Pin 19)
The digital supply pin, which is connected to the logic power supply. This pin should h ave a 0.33 µF capacitor to
ground.
GND
Ground (Pin 2)
Ground return p in is typically connected to t he signal
ground pin of the EIA–232–E connector (Pin 7) as well as to
the logic power supply ground.
V
DD
Positive Power Supply (Pin 17)
This is the positive output of the on–chip voltage doubler
and the positive power supply input of the driver/receiver
sections of the device. This pin requires an external storage
capacitor to filter the 50% duty cycle voltage generated by
the charge pump.
V
SS
Negative Power Supply (Pin 4)
This is the negative output of the on–chip voltage doubler/
inverter and the negative power supply input of the driver/receiver sections of the device. This pin requires an external
storage capacitor to filter the 50% duty cycle voltage generated by the charge pump.
C2+, C2–, C1–, C1+
Voltage Doubler and Inverter (Pins 1, 3, 18, 20)
These are the connections to the internal voltage doubler
and inverter, which generate the VDD and VSS voltages.
Rx1, Rx2, Rx3
Receive Data Input (Pins 5, 7, 9)
These are the EIA–232–E receive signal inputs. A voltage
between + 3 and + 25 V is decoded as a space and causes
the corresponding DO pin to swing to ground (0 V). A voltage
between – 3 and – 25 V is decoded as a mark, and causes
the DO pin to swing up to VCC.
DO1, DO2, DO3
Data Output (Pins 16, 14, 12)
These are the receiver digital output pins, which swing
from VCC to GND. Each output pin is capable of driving one
LSTTL input load.
DI1, DI2, DI3
Data Input (Pins 15, 13, 11)
These are the high impedance digital input pins to the drivers. Input voltage levels on these pins must be between V
CC
and GND.
Tx1, Tx2, Tx3
Transmit Data Output (Pins 6, 8, 10)
These are the EIA–232–E transmit signal output pins,
which swing toward VDD and V
SS.
A logic 1 at a DI input
causes the corresponding Tx output to swing toward VSS. A
logic 0 causes the output to swing toward VDD. The actual
levels and slew rate achieved will depend on the output loading (RLø
CL).