Datasheet MC14538B Datasheet (ON Semiconductor)

MC14538B

q

Dual Precision Retriggerable/Resettable Monostable Multivibrator

The MC14538B is a dual, retriggerable, resettable monostable multivibrator. It may be triggered from either edge of an input pulse, and produces an accurate output pulse over a wide range of widths, the duration and accuracy of which are determined by the external timing components, C

RX = 

C

= Farads

X

Features

• Unlimited Rise and Fall Time Allowed on the A Trigger Input

• Pulse Width Range = 10 s to 10 s

• Latched Trigger Inputs

• Separate Latched Reset Inputs

• 3.0 Vdc to 18 Vdc Operational Limits

• Triggerable from Positive (A Input) or Negative−Going Edge (B−Input)

• Capable of Driving Two Low−Power TTL Loads or One Low−Power

Schottky TTL Load Over the Rated Temperature Range

• Pin−for−pin Compatible with MC14528B and CD4528B (CD4098)

• Use the MC54/74HC4538A for Pulse Widths Less Than 10 s with

Supplies Up to 6 V

• Pb−Free Packages are Available*

and RX. Output Pulse Width T = RX  CX (secs)

X

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PDIP−16

P SUFFIX

CASE 648

SOIC−16

D SUFFIX

CASE 751B

SOIC−16 DW SUFFIX CASE 751G

16

1

16

1

16

1

MARKING

DIAGRAMS

MC14538BCP

AWLYYWW

14538B

AWLYWW

14538B

AWLYYWW

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

V

Vin, V

Iin, I

T

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.

1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

DC Supply Voltage Range −0.5 to +18.0 V

DD

Input or Output Voltage Range

out

(DC or Transient) Input or Output Current

out

(DC or Transient) per Pin

P

Power Dissipation, per Package

D

(Note 1)

T

Operating Temperature Range −55 to +125 °C

A

Storage Temperature Range −65 to +150 °C

stg

T

Lead Temperature

L

(8−Second Soldering)

SS

Parameter Value Unit

 (Vin or V

or VDD). Unused outputs must be left open.

)  VDD.

out

)

SS

−0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

and V

in

should be constrained

out

16

TSSOP−16

DT SUFFIX

CASE 948F

SOEIAJ−16

F SUFFIX

CASE 966

A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week

14

538B

ALYW

1

16

MC14538B

AWLYWW

1

ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

*For additional information on our Pb−Free strategy

and soldering details, please download the ON Semiconductor Soldering and Mounting

ues Reference Manual, SOLDERRM/D.

Techni

 Semiconductor Components Industries, LLC, 2005

February, 2005 − Rev. 6

1 Publication Order Number:

MC14538B/D

MC14538B

MC14528B MC14536B MC14538B

MC14541B MC4538A*

100 ns

PIN ASSIGNMENT

V

C

X/RX

RESET A

Q

V

1

SS

A

2

3

A

4

A

B

A

6

A

7

A

8

SS

16

15

14

13

125

11

10

9

V

DD

V

SS

C

X/RX

RESET B

A

B

Q

B

Q

B

ONE−SHOT SELECTION GUIDE

1 s 10 s 100 s 1 ms 10 ms 100 ms 1 s 10 s

23 HR

5 MIN.

BLOCK DIAGRAM

C

X

A

4

B

5

3

A

12

B

11

13

RX AND CX ARE EXTERNAL COMPONENTS. V

= PIN 16

DD

V

= PIN 8, PIN 1, PIN 15

SS

12

RESET

C

X

15 14

RESET

Q1

Q2

R

X

V

DD

6

7

R

X

V

DD

10

9

*LIMITED OPERATING VOLTAGE (2 − 6 V)

TOTAL OUTPUT PULSE WIDTH RANGE

RECOMMENDED PULSE WIDTH RANGE

ORDERING INFORMATION

Device Package Shipping

MC14538BCP PDIP−16 500 Units / Rail MC14538BCPG PDIP−16

500 Units / Rail

(Pb−Free) MC14538BD SOIC−16 48 Units / Rail MC14538BDG SOIC−16

48 Units / Rail

(Pb−Free) MC14538BDR2 SOIC−16 2500 Units / Tape & Reel MC14538BDR2G SOIC−16

2500 Units / Tape & Reel

(Pb−Free) MC14538BDW SOIC−16 WB 47 Units / Rail MC14538BDWR2 SOIC−16 WB 1000 Units / Tape & Reel MC14538BDWR2G SOIC−16 WB

1000 Units / Tape & Reel

(Pb−Free) MC14538BDTR2 TSSOP−16* 2500 Units / Tape & Reel MC14538BF SOEIAJ−16 50 Units / Rail MC14538BFG SOEIAJ−16

50 Units / Rail

(Pb−Free) MC14538BFEL SOEIAJ−16 2000 Units / Tape & Reel MC14538BFELG SOEIAJ−16

2000 Units / Tape & Reel

(Pb−Free)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

†

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2

MC14538B

V

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

− 55C 25C 125C

Characteristic Symbol

Output Voltage “0” Level

V

= VDD or 0

in

“1” Level

V

= 0 or V

in

DD

Input Voltage “0” Level

(V

= 4.5 or 0.5 Vdc)

O

= 9.0 or 1.0 Vdc)

(V

O

(V

= 13.5 or 1.5 Vdc)

O

“1” Level

(V

= 0.5 or 4.5 Vdc)

O

(V

= 1.0 or 9.0 Vdc)

O

(V

= 1.5 or 13.5 Vdc)

O

Output Drive Current

(V

= 2.5 Vdc) Source

OH

= 4.6 Vdc)

(V

OH

(V

= 9.5 Vdc)

OH

(V

= 13.5 Vdc)

OH

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

OL

= 1.5 Vdc)

(V

OL

Input Current, Pin 2 or 14 I Input Current, Other Inputs I Input Capacitance, Pin 2 or 14 C Input Capacitance, Other Inputs

(V

= 0)

in

Quiescent Current

(Per Package) Q = Low, Q

= High

Quiescent Current, Active State

(Both) (Per Package) Q = High, Q

= Low

Total Supply Current at an external load capacitance (C external timing network (R

) and at

L

X

, CX)

(Note 3)

V

OL

V

OH

V

IL

V

IH

I

OH

I

OL

in in

in

C

in

I

DD

I

DD

I

T

DD

Vdc

5.0 10 15

5.0

5.0 10 15

Min Max Min Typ

(Note 2)

−

4.95

9.95

14.95

−

3.5

7.0 11

– 3.0

– 0.64

– 1.6 – 4.2

0.64

1.6

4.2

0.05

−

1.5

3.0

4.0

−

4.95

9.95

14.95

−

3.5

7.0 11

– 2.4

– 0.51

– 1.3 – 3.4

0.51

1.3

3.4

– 0.88 – 2.25

0 0 0

5.0 10 15

2.25

4.50

6.75

2.75

5.50

8.25

– 4.2

– 8.8

0.88

2.25

8.8

Max Min Max

0.05

−

1.5

3.0

4.0

−

4.95

9.95

14.95

−

3.5

7.0 11

– 1.7

– 0.36

– 0.9 – 2.4

0.36

0.9

2.4

15 − ±0.05 − ±0.00001 ±0.05 − ±0.5 Adc 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 Adc

− − − − 25 − − − pF

− − − − 5.0 7.5 − − pF

5.0 10 15

5.0 10

−

5.0 10 20

2.0

−

0.005

0.010

0.015

0.04

0.08

0.13

IT = (3.5 x 10–2) RXCXf + 4CXf + 1 x 10–5 CLf I

= (8.0 x 10–2) RXCXf + 9CXf + 2 x 10–5 CLf

T

= (1.25 x 10–1) RXCXf + 12CXf + 3 x 10–5 CLf

I

T

where: I

where: C

in A (one monostable switching only),

T

in F, CL in pF, RX in k ohms, and

X

5.0 10 20

0.20

0.45

0.70

−

where: f in Hz is the input frequency.

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25C.

0.05

−

1.5

3.0

4.0

−

150 300 600

2.0

Unit

Vdc

mAdc

Adc

mAdc

Adc

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3

MC14538B

SWITCHING CHARACTERISTICS (Note 4) (C

= 50 pF, T

L

= 25C)

A

All Types

V

Characteristic Symbol

Output Rise Time

= (1.35 ns/pF) CL + 33 ns

t

TLH

t

= (0.60 ns/pF) CL + 20 ns

TLH

= (0.40 ns/pF) CL + 20 ns

t

TLH

Output Fall Time

= (1.35 ns/pF) CL + 33 ns

t

THL

t

= (0.60 ns/pF) CL + 20 ns

THL

t

= (0.40 ns/pF) CL + 20 ns

THL

Propagation Delay Time

A or B to Q or Q

t

, t t t

PLH PLH PLH

= (0.90 ns/pF) CL + 255 ns

PHL

, t

= (0.36 ns/pF) CL + 132 ns

PHL

, t

= (0.26 ns/pF) CL + 87 ns

PHL

t

PLH

t

TLH

THL

,

PHL

Reset to Q or Q

t

, t

PLH

t

PLH

t

PLH

Input Rise and Fall Times

= (0.90 ns/pF) CL + 205 ns

PHL

, t

= (0.36 ns/pF) CL + 107 ns

PHL

, t

= (0.26 ns/pF) CL + 82 ns

PHL

tr, t

f

Reset

B Input 5

A Input 5

DD

Vdc

5.0 10 15

5 10 15

10 15

10

Min Typ

(Note 5)

−

100

50 40

100

50 40

300 150 100

250 125

95

−

300

1.2

0.4

No Limit

Max

200 100

80

200 100

80

600 300 220

500 250 190

15

5 4

1.0

0.1

0.05

Unit

ns

s

ms

−

15

Input Pulse Width

A, B, or Reset

Retrigger Time t

Output Pulse Width — Q or Q

tWH,

t

WL

rr

T

5.0 10 15

170

90 80

0 0 0

85 45 40

−

ns

−

ns

−

− s

Refer to Figures 8 and 9

= 0.002 F, RX = 100 k

C

X

CX = 0.1 F, RX = 100 k 5.0

CX = 10 F, RX = 100 k 5.0

Pulse Width Match between circuits in

the same package.

= 0.1 F, RX = 100 k

C

X

[(T

1

100

– T2)/T1]

5.0 10 15

10 15

5.0 10 15

198 200 202

9.3

9.4

9.5

0.91

0.92

0.93

−

210 212 214

9.86 10

10.14

0.965

0.98

0.99

± 1.0 ± 1.0 ± 1.0

230 232 234

10.5

10.6

10.7

1.03

1.04

1.06

± 5.0 ± 5.0 ± 5.0

ms

s

%

4. The formulas given are for the typical characteristics only at 25C.

5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

OPERATING CONDITIONS

External Timing Resistance R External Timing Capacitance C

X X

6. The maximum usable resistance RX is a function of the leakage of the capacitor CX, leakage of the MC14538B, and leakage due to board layout and surface resistance. Susceptibility to externally induced noise signals may occur for R

> 15 F, use discharge protection diode per Fig. 11.

7. If C

X

− 5.0 − (Note 6) k

− 0 − No Limit

F

(Note 7)

> 1 M..

X

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4

MC14538B

V

C

DD

R

X

V

RESET

in

21(14)

4 (12)

A

5(11)

B

3 (13)

(15)

500 pF

V

SS

V

DD

P1

N1

V

SS

R

X

C

X

A

B

RESET A′ B′

RESET

CX/R

′

+

C1 C2

ref1

− ENABLE

V

ref2

V

+

−

ENABLE

RSQ OUTPUT

LATCH

6(10)

Q

7(9)

CONTROL

Q

R

S

RESET LATCH

Q

R

RS

NOTE: Pins 1, 8 and 15 must

be externally grounded

Figure 1. Logic Diagram

(1/2 of DevIce Shown)

V

DD

I

D

0.1 F CERAMIC

R

′

X

′

C

X

V

SS

X

Q

C

Q

Q′

C

Q

′

V

SS

L

C

L

C

L

20 ns 20 ns

90%

V

in

10%

V

0 V

DD

PULSE

GENERATOR

PULSE

GENERATOR

PULSE

GENERATOR

Figure 2. Power Dissipation Test Circuit and Waveforms

V

DD

INPUT CONNECTIONS

R

X

C

V

SS

X

A

B

RESET A′

B′

RESET

CX/R

′

R

′

X

C

X

′

*CL = 50 pF

V

SS

Q

C

Q

Q′

C

′

Q

V

SS

L

C

L

C

L

*Includes capacitance of probes,

wiring, and fixture parasitic.

NOTE: Switching test waveforms

for PG1, PG2, PG3 are shown In Figure 4.

Characteristics Reset A B

t

, t

PLH

T, t

WH

t

PLH

T, t

WH

t

PLH(R)

t

WH

PHL

TLH

, t

WL

, t

PHL

TLH

, t

WL

, t

PHL(R)

, t

WL

,

THL

, t

,

THL

,

V

DD

V

DD

PG1 V

V

SS

PG3 PG1 PG2

PG1 =

PG2 =

PG3 =

DD

PG2

Figure 3. Switching Test Circuit

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5

MC14538B

RESET

1.0

0.8

0.6

0.4

A

B

t

Q

PLH

T

= 25°C

A

R

= 100 k

X

C

= 0.1 F

X

50%

t

WH

50%

t

T

PLH

50% 50% 50%

t

PHL

50% 50%

90%

10%

t

TLH

t

THL

t

THL

90%

t

WL

t

THL

t

THL

90%

t

90%

10%

TLH

50%

t

PHL

10%

90%

t

THL

t

PLH

50%

t

TLH

10%

Figure 4. Switching Test Waveforms

0% POINT PULSE WIDTH V

= 5.0 V, T = 9.8 ms

DD

= 10 V, T = 10 ms

V

DD

V

= 15 V, T = 10.2 ms

DD

= 10 V (%)

DD

10%

t

2

1

0

1

2

t

WL

PHL

50% V

t

TLH

t

rr

DD

V

DD

V

DD

50%

RX = 100 k C

= 0.1 F

X

0.2

RELATIVE FREQUENCY OF OCCURRENCE

0

−4 −2 0 2 4

T, OUTPUT PULSE WIDTH (%)

Figure 5. Typical Normalized Distribution

of Units for Output Pulse Width

1000

RX = 100 k, CL = 50 pF ONE MONOSTABLE SWITCHING ONLY

100

VDD = 15 V

10

5.0 V

10 V

1.0

TOTAL SUPPLY CURRENT ( A)µ

0.1

0.001 0.1 1.0 10 100

OUTPUT DUTY CYCLE (%)

Figure 7. Typical Total Supply Current

versus Output Duty Cycle

NORMALIZED PULSE WIDTH CHANGE

WITH RESPECT TO VALUE AT V

, SUPPLY VOLTAGE (VOLTS)

V

DD

Figure 6. Typical Pulse Width Variation as

a Function of Supply Voltage V

FUNCTION TABLE

Inputs Outputs

Reset A B Q Q

H H H L

H L Not Triggered H H Not Triggered

H L, H, H Not Triggered H L L, H, Not Triggered

L X X L H

X X Not Triggered

15141312111098765

DD

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6

= 10 V (%

)

RX = 100 k C

DD

= 0.1 F

X

2

1

0

°C VALUE AT V

−1

−2

TYPICAL NORMALIZED ERROR

VDD = 15 V

VDD = 10 V

VDD = 5 V

MC14538B

= 10 V (%

3.0

DD

2.0

1.0

°C VALUE AT V

−1.0

−2.0

−3.0

TYPICAL NORMALIZED ERROR

0

VDD = 15 V

VDD = 10 V

VDD = 5.0 V

RX = 100 k C

= .002 F

X

WITH RESPECT TO 25

−60 −40 −20 0 20 40 60 80 100 120 140 T

, AMBIENT TEMPERATURE (°C)

A

Figure 8. Typical Error of Pulse Width

Equation versus Temperature

THEORY OF OPERATION

1

A

2

B

RESET

V

C

X/RX

V

ref2

V

ref1

V

ref1

Q

T T

ref2

WITH RESPECT TO 25

−60 −40 −20 0 20 40 60 80 100 120 140 T

, AMBIENT TEMPERATURE (°C)

A

Figure 9. Typical Error of Pulse Width

Equation versus Temperature

3 4

5

V

ref2

V

ref1

T

V

ref2

V

ref1

1

2

Negative edge trigger

3

Positive edge trigger

4

Positive edge re−trigger (pulse lengthening)Positive edge trigger

5

Positive edge re−trigger (pulse lengthening)

Figure 10. Timing Operation

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7

MC14538B

TRIGGER OPERATION

The block diagram of the MC14538B is shown in

Figure 1, with circuit operation following.

As shown in Figure 1 and 10, before an input trigger occurs, the monostable is in the quiescent state with the Q output low, and the timing capacitor C to VDD. When the trigger input A goes from VSS to V

completely charged

X

DD

(while inputs B and Reset are held to VDD) a valid trigger is recognized, which turns on comparator C1 and N−channel transistor N1 ➀. At the same time the output latch is set. With transistor N1 on, the capacitor CX rapidly discharges toward VSS until V

is reached. At this point the output of

ref1

comparator C1 changes state and transistor N1 turns off. Comparator C1 then turns off while at the same time comparator C2 turns on. With transistor N1 off, the capacitor C

begins to charge through the timing resistor, RX, toward

X

VDD. When the voltage across CX equals V

, comparator

ref 2

C2 changes state, causing the output latch to reset (Q goes low) while at the same time disabling comparator C2 ➁. This ends at the timing cycle with the monostable in the quiescent state, waiting for the next trigger.

In the quiescent state, C the current through resistor R

is fully charged to VDD causing

X

to be zero. Both comparators

X

are “off” with total device current due only to reverse junction leakages. An added feature of the MC14538B is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q i s independent of the value of C

, RX, or the duty

X

cycle of the input waveform.

on Reset

sets the reset latch and causes the capacitor to be fast charged to VDD by turning on transistor P1 ➄. When the voltage on the capacitor reaches V

, the reset latch will

ref 2

clear, and will then be ready to accept another pulse. It the Reset input is held low, any trigger inputs that occur will be inhibited and the Q and Q

outputs of the output latch will not change. Since the Q output is reset when an input low level is detected on the Reset input, the output pulse T can be made significantly shorter than the minimum pulse width specification.

POWER−DOWN CONSIDERATIONS

Large capacitance values can cause problems due to the large amount of energy stored. When a system containing the MC14538B is powered down, the capacitor voltage may discharge from VDD through the standard protection diodes at pin 2 or 14. Current through the protection diodes should be limited to 10 mA and therefore the discharge time of the V

supply must not be faster than (VDD). (C) /(10 mA).

DD

For example, if VDD = 10 V and CX = 10 F, the VDD supply should discharge no faster than (10 V) x (10 F) /(10 mA) = 10 ms. This is normally not a problem since power supplies are heavily filtered and cannot discharge at this rate.

When a more rapid decrease of V

to zero volts occurs,

DD

the MC14538B can sustain damage. To avoid this possibility use an external clamping diode, D

, connected as shown in

X

Fig. 11.

D

x

RETRIGGER OPERATION

The MC14538B is retriggered if a valid trigger occurs ➂

followed by another valid trigger ➃ before the Q output has returned to the quiescent (zero) state. Any retrigger, after t h e timing node voltage at pin 2 or 14 has begun to rise from V

, but has not yet reached V

ref 1

, will cause an increase

ref 2

in output pulse width T. When a valid retrigger is initiated ➃, the voltage at CX/RX will again drop to V

ref 1

before progressing along the RC charging curve toward VDD. The Q output will remain high until time T, after the last valid retrigger.

RESET OPERATION

The MC14538B may be reset during the generation of the

output pulse. In the reset mode of operation, an input pulse

C

x

V

SS

RESET

Figure 11. Use of a Diode to Limit

Power Down Current Surge

V

DD

R

x

V

DD

Q

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8

RISING−EDGE

TRIGGER

A

B

B = V

MC14538B

TYPICAL APPLICA TIONS

C

X

R

X

V

DD

Q

DD

RESET = V

DD

C

X

R

X

RISING−EDGE

TRIGGER

A

B

C

RESET

X

R

X

V

DD

Q

= V

DD

C

X

R

X

A = V

SS

B

FALLING−EDGE

TRIGGER

RESET = V

Figure 12. Retriggerable

Monostables Circuitry

V

DD

Q

DD

A B

C

D

V

DD

V

DD

Figure 14. Connection of Unused Sections

NC

Q

FALLING−EDGE

TRIGGER

NC

A

B

RESET = V

DD

Figure 13. Non−Retriggerable

Monostables Circuitry

V

DD

Q

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9

MC14538B

PACKAGE DIMENSIONS

PDIP−16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648−08

ISSUE T

−A−

916

B

18

F

C

S

−T−

H

G

D

16 PL

0.25 (0.010) T

K

M

A

L

SEATING PLANE

J

M

SOIC−16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B−05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

DIM MIN MAX MIN MAX

A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77

M

G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01

MILLIMETERSINCHES



−T−

−A−

16 9

−B−

18

G

K

C

SEATING

PLANE

D

16 PL

0.25 (0.010) A

M

S

B

T

S

8 PLP

0.25 (0.010) B

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

M

S

X 45

R



F

J

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

DIM MIN MAX MIN MAX

A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7



P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019

INCHESMILLIMETERS

http://onsemi.com

10

16 9

ÉÉ

M

B

H8X

M

0.25

0.25 B

14X

MC14538B

PACKAGE DIMENSIONS

SOIC−16 WB

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751G−03

ISSUE C

D

A



E



h X 45

81

B16X

M

S

A

T

B

S

A

SEATING

T

PLANE

C

e

A1

L

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS

DIM MIN MAX

A 2.35 2.65

A1 0.10 0.25

B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60

e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0 7



0.10 (0.004)

−T−

SEATING PLANE

L

U0.15 (0.006) T

PIN 1 IDENT.

U0.15 (0.006) T

D

S

2X L/2

S

TSSOP−16

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F−01

ISSUE A

16X REFK

0.10 (0.004) V

M

S

U

T

S

K

K1

16

9

J1

B

−U−

1

8

J

N

A

SECTION N−N

0.25 (0.010)

M

−V− N

F

DETAIL E

C

DETAIL E

H

G

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011

J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

−W−

L 6.40 BSC 0.252 BSC M 0 8 0 8



INCHESMILLIMETERS

http://onsemi.com

11

16 9

1

Z

D

e

b

0.13 (0.005)

M

8

H

E

A

1

0.10 (0.004)

MC14538B

PACKAGE DIMENSIONS

SOEIAJ−16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966−01

ISSUE O

L

E

M



L

DETAIL P

VIEW P

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

Q

1

c

2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).

MILLIMETERS

DIM MIN MAX MIN MAX

−−− 2.05 −−− 0.081

A A

0.05 0.20 0.002 0.008

1

0.35 0.50 0.014 0.020

b

0.18 0.27 0.007 0.011

c

9.90 10.50 0.390 0.413

D

5.10 5.45 0.201 0.215

E

1.27 BSC 0.050 BSC

e

H

7.40 8.20 0.291 0.323

E

0.50 0.85 0.020 0.033

L L

1.10 1.50 0.043 0.059

E

0

M



Q

0.70 0.90 0.028 0.035

1

−−− 0.78 −−− 0.031

Z

INCHES

10



10

0



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MC14538B/D

12

Datasheet MC14538B Datasheet (ON Semiconductor)

Specifications and Main Features

Frequently Asked Questions

User Manual