Datasheet MC14528BFL2, MC14528BFR1, MC14528BCP, MC14528BD, MC14528BDR2 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14528B/D

MC14528B

Dual Monostable
Multivibrator

The MC14528B is a dual, retriggerable, resettable monostable
multivibrator. It may be triggered from either edge of an input pulse,
and produces an output pulse over a wide range of widths, the duration
of which is determined by the external timing components, C

X

and

RX.

• Separate Reset Available

• Diode Protection on All Inputs

• Triggerable from Leading or Trailing Edge Pulse

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Pin–for–Pin Replacement with the MC14538B

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol

Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

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A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14528BCP PDIP–16 2000/Box
MC14528BD SOIC–16 48/Rail
MC14528BDR2 SOIC–16 2500/Tape & Reel

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

MARKING

DIAGRAMS

1

16

PDIP–16

P SUFFIX

CASE 648

MC14528BCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

1

16

14528B

AWLYWW

SOEIAJ–16

F SUFFIX

CASE 966

1

16

MC14528B

AWLYWW

MC14528BFEL SOEIAJ–16 See Note 1.

MC14528BF SOEIAJ–16 See Note 1.

MC14528B

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2

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

A2

RESET 2

CX2/RX2

V

SS

V

DD

Q2

Q2

B2

A1

RESET 1

CX1/RX1

V

SS

V

SS

Q1

Q1

B1

BLOCK DIAGRAM

RESET 1

RESET 2

V

DD

V

DD

Q1
Q1

Q2
Q2

A1
B1

A2
B2

C

X

1

C

X

2

RX2

R

X

1

12

4
5

3

6
7

1415

12
11

13

10

9

V

DD

= PIN 16

V

SS

= PIN 1, PIN 8, PIN 15

R

X

AND CX ARE EXTERNAL COMPONENTS

ONE–SHOT SELECTION GUIDE

100 ns

1 ms 10 ms 100 ms

1 ms 10 ms 100 ms 1 s 10 s

MC14528B
MC14536B
MC14538B
MC14541B

MC4538A*

23 HR

5 MIN.

TOTAL OUTPUT PULSE WIDTH RANGE

RECOMMENDED PULSE WIDTH RANGE

*LIMITED OPERATING VOLTAGE (2–6 V)

MC14528B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

DD

– 55_C 25_C 125_C

Characteristic Symbol

Vdc

Min Max Min Typ

(4.)

Max Min Max

Unit

Output Voltage “0” Level

V

in

= VDD or 0

V

OL

5.0
10
15

—
—
—

0.05

0.05

0.05

—
—
—

0
0
0

0.05

0.05

0.05

—
—
—

0.05

0.05

0.05

Vdc

“1” Level

V

in

= 0 or V

DD

V

OH

5.0
10
15

4.95

9.95

14.95

—
—
—

4.95

9.95

14.95

5.0
10
15

—
—
—

4.95

9.95

14.95

—
—
—

Vdc

Input Voltage “0” Level

(V

O

= 4.5 or 0.5 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

V

IL

5.0
10
15

—
—
—

1.5

3.0

4.0

—
—
—

2.25

4.50

6.75

1.5

3.0

4.0

—
—
—

1.5

3.0

4.0

Vdc

“1” Level

(V

O

= 0.5 or 4.5 Vdc)

(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

V

IH

5.0
10
15

3.5

7.0
11

—
—
—

3.5

7.0
11

2.75

5.50

8.25

—
—
—

3.5

7.0
11

—
—
—

Vdc

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

I

OH

5.0

5.0
10
15

– 1.2

– 0.64

– 1.6
– 4.2

—
—
—
—

– 1.0

– 0.51

– 1.3
– 3.4

– 1.7
– 0.88
– 2.25

– 8.8

—
—
—
—

– 0.7

– 0.36

– 0.9
– 2.4

—
—
—
—

mAdc

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

I

OL

5.0
10
15

0.64

1.6

4.2

—
—
—

0.51

1.3

3.4

0.88

2.25

8.8

—
—
—

0.36

0.9

2.4

—
—
—

mAdc

Input Current I

in

15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance

(V

in

= 0)

C

in

— — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package)

I

DD

5.0
10
15

—
—
—

5.0
10
20

—
—
—

0.005

0.010

0.015

5.0
10
20

—
—
—

150
300
600

µAdc

Total Supply Current at an

external load Capacitance (C

L

)
and at external timing
capacitance (C

X

), use the

formula —

(5.)

I

T

— IT(CL, CX) = [(CL + 0.36CX)VDDf + 2x10

–8

RXCX(V

DD

–2

)2f] x 10

–3

where: IT in µA (per circuit), CL and CX in pF, RX in megohms,

V

DD

in Vdc, f in kHz is input frequency.

µAdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

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4

SWITCHING CHARACTERISTICS

(8.)

(C

L

= 50 pF, TA = 25_C)

Characteristic

Symbol

C

X

pF

R

X

kΩ

V

DD

Vdc

Min Typ

(9.)

Max Unit

Output Rise and Fall Time

t

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

t

TLH

,

t

THL

— —

5.0
10
15

—
—
—

100

50
40

200
100

80

ns

Turn–Off, Turn–On Delay Time — A or B to Q or Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 240 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 87 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 65 ns

t

PLH

,

t

PHL

15 5.0

5.0
10
15

—
—
—

325
120

90

650
240
180

ns

Turn–Off, Turn–On Delay Time — A or B to Q or Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 620 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 257 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 185 ns

t

PLH

,

t

PHL

1000 10

5.0
10
15

—
—
—

705
290
210

—
—
—

ns

Input Pulse Width — A or B

t

WH

15 5.0 5.0

10
15

150

75
55

70
30
30

—
—
—

ns

t

WL

1000 10 5.0

10
15

—
—
—

70
30
30

—
—
—

ns

Output Pulse Width — Q or Q

(For CX < 0.01 µF use graph for
appropriate V

DD

level.)

t

W

15 5.0 5.0

10
15

—
—
—

550
350
300

—
—
—

ns

Output Pulse Width — Q or Q

(For CX > 0.01 µF use formula:
t

W

= 0.2 RX CX Ln [VDD – VSS])

(6.)

t

W

10,000 10 5.0

10
15

15
10
15

30
50
55

45
90
95

µs

Pulse Width Match between Circuits in the same

package

t1 – t2 10,000 10 5.0

10
15

—
—
—

6.0

8.0

8.0

25
35
35

%

Reset Propagation Delay — Reset to Q or Q t

PLH

,

t

PHL

15 5.0 5.0

10
15

—
—
—

325

90
60

600
225
170

ns

1000 10 5.0

10
15

—
—
—

1000

300
250

—
—
—

ns

Retrigger Time t

rr

15 5.0 5.0

10
15

0
0
0

—
—
—

—
—
—

ns

1000 10 5.0

10
15

0
0
0

—
—
—

—
—
—

ns

External Timing Resistance R

X

— — — 5.0 — 1000 kΩ

External Timing Capacitance C

X

— — — No Limits

(7.)

µF

6. RX is in Ohms, CX is in farads, VDD and VSS in volts, PW

out

in seconds.

7. If C

X

> 15 µF, Use Discharge Protection Diode DX, per Fig. 9.

8. The formulas given are for the typical characteristics only at 25_C.

9. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14528B

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5

FUNCTION TABLE

Inputs Outputs

Reset A B Q Q

H H
H L

H L Not Triggered
H H Not Triggered

H L, H, H Not Triggered
H L L, H, Not Triggered

L X X L H

X X Not Triggered

Figure 1. Output Source Current Test Circuit Figure 2. Output Sink Current Test Circuit

V

DD

V

DD

OPEN

V

SS

V

SS

OPEN

V

OL

RESET

A
B

Q

Q

16

8

16

8

I

OL

RESET

A
B

Q

Q

I

OH

V

OH

Figure 3. Power Dissipation Test Circuit and Waveforms

V

DD

DUTY CYCLE = 50%

C

L

C

L

C

L

C

L

I

D

500 pF

V

SS

V

in

20 ns 20 ns

V

DD

0 VV

in

90%

10%

0.1 mF
CERAMIC

R

X

′

CX′

R

X

C

X

A
B

RESET

A′
B′

RESET

′

Q
Q

Q′
Q

′

MC14528B

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6

INPUT CONNECTIONS

Characteristics Reset A B

t

PLH

, t

PHL

, t

TLH

, t

THL

t

W

V

DD

PG1 V

DD

t

PLH

, t

PHL

, t

TLH

, t

THL

t

W

V

DD

V

SS

PG2

t

PLH(R)

, t

PHL(R)

, t

W

PG3 PG1 PG2

Figure 5. AC Test Waveforms

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

OH

V

OL

V

OH

V

OL

90%

10%

90%

10%

50%50% 50%

50%

50%

t

rr

50%

t

TLH

t

THL

t

TLH

t

THL

90%

10%

t

TLH

t

THL

t

THL

t

TLH

50%

90%

10%

50%

50%

t

WL

t

PLH

50%

50% 50%

90%

10%

A

B

Q

Q

RESET

t

WH

t

TLH

t

THL

t

PHL

t

PHL

t

PHL

t

WL

t

PHL

t

W

Figure 6. Pulse Width versus C

X

100,00010,000100010010

C

X

, EXTERNAL CAPACITANCE (pF)

PULSE WIDTH ( s)t ,

W

m

1000

100

10

1.0

0.1

VDD = 15 V

10 V

5.0 V

15 V

10 V

5.0 V

15 V
10 V

5.0 V

RX = 5.0 k

W

15 V
10 V

5.0 V

RX = 100 k

W

RX = 10 k

W

Figure 4. AC Test Circuit

PULSE

GENERATOR

PULSE

GENERATOR

PULSE

GENERATOR

V

DD

RX′

C

X

′

R

X

C

X

V

SS

A
B

RESET

A′
B′

RESET

′

Q
Q

Q′
Q

′

C

L

C

L

C

L

C

L

PG1 =

PG2 =

PG3 =

*CX = 15 pF
*C

L

= 15 pF

R

X

= 5.0 k

W

*Includes capacitance of probes,

wiring, and fixture parasitic.

NOTE: AC test waveforms for

PG1, PG2, and PG3 on
next page.

MC14528B

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7

TYPICAL APPLICATIONS

Figure 7. Retriggerable

Monostables Circuitry

Figure 8. Non–Retriggerable

Monostables Circuitry

V

DD

R

x

C

x

V

DD

Q

Q

RESET

FALLING EDGE
TRIGGER

RISING EDGE
TRIGGER

V

DD

R

x

C

x

V

DD

Q

Q

RESET

A
B

A
B

V

DD

V

DD

R

x

C

x

V

DD

Q

Q

RESET

FALLING EDGE
TRIGGER

RISING EDGE
TRIGGER

V

DD

R

x

C

x

V

DD

Q

Q

RESET

A
B

A
B

Figure 9. Use of a Diode to Limit

Power Down Current Surge

Figure 10. Connection of Unused Sections

V

DD

V

DD

V

DD

D

X

R

x

C

x

V

DD

Q

Q

RESET

RESET

V

DD

V

DD

NC

NC

NC

A
B

1, 15

2, 14

Q

Q

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8

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77

G 0.100 BSC 2.54 BSC

H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74

M 0 10 0 10

S 0.020 0.040 0.51 1.01

____

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9

P ACKAGE DIMENSIONS

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

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10

P ACKAGE DIMENSIONS

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035
––– 0.78 ––– 0.031

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005)

0.10 (0.004)

1

16 9

8

D

Z

E

A

b
c
D
E
e

L

M

Z

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

MC14528B

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11

Notes

MC14528B

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12

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