Datasheet MC145220DT, MC145220F Datasheet (Motorola)

Page 1

MC145220MOTOROLA

   "   ! !"

BiCMOS

The MC145220 is a low–voltage, single–chip frequency synthesizer with serial interface capable of direct usage up to 1.1 GHz. The device simultaneously supports two loops. The two on–chip dual–modulus prescalers may be independently programmed to divide by either 32/33 or 64/65.

The device consists of two dual–modulus prescalers, two 6–stage A counters, two 12–stage N counters, two fully programmable 13–stage R (reference) counters, and two lock detectors. Four phase/frequency detectors are included: two with current source/sink outputs and two with double–ended outputs.

The counters are programmed via a synchronous serial port which is SPI compatible. The serial port is byte–oriented to facilitate control via an MCU. Due to the innovative BitGrabber Plus registers, the MC145220 may be cascaded with other peripherals featuring BitGrabber Plus without requiring leading dummy bits or multiple address bits in the serial data stream. In addition, BitGrabber Plus peripherals may be cascaded with existing BitGrabber peripherals. Because this device is a dual synthesizer, a single steering bit is used in the serial data stream to direct the data to either side of the chip.

The phase/frequency detectors have linear transfer functions (no dead zones). The current delivered by the current source/sink outputs is controllable via the serial port.

Also featured are low–power standby for either one or both loops and on–board support of an external crystal. In addition, the part may be configured such that the REFin pin accepts an external reference signal. In this configuration, the REF

out

pin may be programmed to output the REF

frequency divided by 1, 2, 4, 8, or 16.

• Operating Frequency: 40 to 1100 MHz

• Operating Supply Voltage Range: 2.7 to 5.5 V

• Supply Current: Both PLLs Operating — 12 mA Nominal

One PLL Operating, One on Standby — 6.5 mA Nominal Both PLLs on Standby — 30 µA Maximum

• Phase Detector Output Current: Up to 2 mA @ 5 V

Up to 1 mA @ 3 V

• Operating Temperature Range: – 40 to 85°C

• Independent R Counters Allow Use of Different Step Sizes for Each Loop

• Double–Buffered R Register — Reference and Loop Divide Ratios

Updated Simultaneously

• R Counter Division Range: 1 and 10 to 8,191

• Dual–Modulus Capability Provides Total Division of the VCO Frequency up

to 262,143

• Direct Interface to Motorola SPI Data Port

• Evaluation Kit Available (Part Number MC145220EVK)

• See Application Note AN1253/D for Low–Pass Filter Design, and

AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping

NOTE: This product has been evaluated for operation over a wider range than 40 MHz to 1.1 GHz. If your design requires a wider frequency range, contact your local Motorola representative for further information.

BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.

Order this document

by MC145220/D



SEMICONDUCTOR TECHNICAL DATA

PIN ASSIGNMENT



F SUFFIX

SOG PACKAGE

CASE 803C

DT SUFFIX

TSSOP

CASE 948D

ORDERING INFORMATION

MC145220F SOG Package MC145220DT TSSOP

GND

′

CLK

out

′/φR′

GND

out

REF

out

REF

fin′

ENB11

OUTPUT A

V+

′

Rx/

Rx′/

φV′

fin′

 Motorola, Inc. 1998

REV 4 1/98 TN98012300

Page 2

MC145220 MOTOROLA 2

8 7

BUFFER

AND

CONTROL

REF

out

REF

BitGrabber Plus

R REGISTER

16 BITS

′

13–STAGE

R COUNTER

13–STAGE

′

COUNTER

BitGrabber Plus

A REGISTER

23 BITS

A AND N COUNTERS

32/33 OR

64/65

PRESCALER

RATIO

32/33 OR

64/65

PRESCALER

′

& N′ COUNTERS

BitGrabber Plus

′

23 BITS

RATIO

13 14

′

fin′

24 1/2 STAGE

SHIFT REGISTER

ADDRESS

LOGIC AND

STORAGE

11 20

ENB

CLK

PLL / PLL

′

SELECT FROM

A REGISTER

(INTERNAL)

MUX

′

PORT

PHASE/

FREQUENCY

DETECTOR

PAIR

BitGrabber Plus

′

7 BITS

′

Rx′/

φV′

OUTPUT A

out

′/φR′

Rx/

out

BitGrabber Plus

C REGISTER

7 BITS

PHASE/

FREQUENCY

DETECTOR

PAIR

STBY

(INTERNAL)

STBY

′

(INTERNAL)

4 5

DATA OUT

PIN 9 = V+ (Positive Power to the main PLL, Reference Circuit, and a portion of the Serial Port) PIN 6 = GND (Ground to the main PLL, Reference Circuit, and a portion of the Serial Port) PIN 12 = V+′ (Positive Power to PLL′ and a portion of the Serial Port) PIN 15 = GND′ (Ground to PLL′ and a portion of the Serial Port)

POLARITY

GAIN

PDA/B SELECT

UNUSED

TO MUX FOR

OUTPUT A

UNUSED

POLARITY

GAIN

PDA/B SELECT

UNUSED

(INTERNAL)

′

BLOCK DIAGRAM

DOUBLE BUFFER

Page 3

MC145220MOTOROLA

MAXIMUM RATINGS* (Voltages Referenced to GND, unless otherwise stated)

Symbol Parameter Value Unit

V+, V+

DC Supply Voltage – 0.5 to + 6.0 V

DC Input Voltage – 0.5 to V+ + 0.5 V

out

DC Output Voltage – 0.5 to V+ + 0.5 V

DC Input Current, per Pin ± 10 mA

out

DC Output Current, per Pin ± 20 mA

DC Supply Current, V+, V+i, GND, and GNDi Pins

30 mA

Power Dissipation, per Package 300 mW

stg

Storage Temperature – 65 to + 150 °C

Lead Temperature, 1 mm from Case for 10 Seconds

260 °C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.

ELECTRICAL CHARACTERISTICS

(V+ = V+i = 2.7 to 5.5 V , GND = GNDi, Voltages Referenced to GND, TA = – 40 to 85°C, unless otherwise stated)

Symbol

Parameter Test Condition

Guaranteed

Limit

Unit

Maximum Low–Level Input Voltage

(Din, CLK, ENB

, REFin)

Device in Reference Mode, dc Coupled 0.3 x V+ V

Minimum High–Level Input Voltage

(Din, CLK, ENB

, REFin)

Device in Reference Mode, dc Coupled 0.7 x V+ V

Hys

Minimum Hysteresis Voltage (CLK, ENB) 100 mV

Maximum Low–Level Output Voltage

(LD, LDi, REF

out

, Output A)

out

= 20 µA, Device in Reference Mode;

Output A Not Selected as Port

0.1 V

Minimum High–Level Output Voltage

(REF

out

, Output A)

out

= – 20 µA, Device in Reference Mode;

Output A Not Selected as Port

V+ – 0.1 V

Minimum Low–Level Output Current (REF

out

) V

out

= 0.3 V 0.5 mA

Minimum Low–Level Output Current

(PD

out/φR

, PD

out

/φRi

, Rx/φV, Rxi/φVi

)

out

= 0.3 V; Phase/Frequency Detectors

Configured with φR, φV Outputs

0.5 mA

Minimum Low–Level Output Current (Output A) V

out

= 0.3 V 0.5 mA

Minimum Low–Level Output Current (LD, LDi)

out

= 0.3 V 0.5 mA

Minimum High–Level Output Current (REF

out

) V

out

= V+ – 0.3 V – 0.4 mA

Minimum High–Level Output Current

(PD

out/φR

, PD

out

i/φR

, Rx/φV, Rxi/φVi

)

out

= V+ – 0.3 V; Phase/Frequency Detectors

Configured with φR, φV Outputs

– 0.4 mA

Minimum High–Level Output Current (Output A) V

out

= V+ – 0.3 V; Output A Not Selected as Port – 0.4 mA

Maximum Input Leakage Current

(Din, CLK, ENB, REFin)

Vin = V+ or GND; Device in XTAL Mode ± 1.0 µA

Maximum Input Current (REFin) Vin = V+ or GND; Device in Reference Mode ± 150 µA

Maximum Output Leakage Current

(PD

out/φR

, PD

out

/φRi

)

out

= V+ or GND; Phase/Frequency Detectors

Configured with PD

out

Output, Output in High–

Impedance State

± 150 nA

Maximum Output Leakage Current

(Output A, LD, LDi)

out

= V+ or GND; Output A Selected as Port;

Output in High–Impedance State

± 5 µA

STBY

Maximum Standby Supply Current Vin = V+ or GND; Outputs Open; Both PLLs in

Standby Mode, Shut–Down Crystal Mode or REF

out

–Static–Low Reference Mode

30 µA

Total Operating Supply Current

fin = fini

= 1.1 GHz; both loops active; REFin = 13 MHz @ 1 V p–p; Output A = Inactive; All Outputs = No Connect; Din, ENB

, CLK = V+ or GND; Phase/Frequency

Detectors Configured with φR, φV Outputs

* mA

*The nominal value is 12 mA. This is not a guaranteed limit.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit.

Page 4

MC145220 MOTOROLA 4

ANALOG CHARACTERISTICS — CURRENT SOURCE/SINK OUTPUTS — PD

out/φR

AND PD

out

′/φR′

(Phase/Frequency Detectors Configured with PD

out

Outputs, I

out

≤ 2 mA @V+ = V+i = 4.5 to 5.5 V , I

out

≤ 1 mA @V+ = V+i = 2.7 to 4.4 V ,

GND = GNDi, Voltages Referenced to GND)

Parameter Test Condition

Guaranteed

Limit

Unit

Maximum Source Current Variation Part–to–Part (Notes 3 and 4) V

out

= 0.5 x V+ ± 20 %

Maximum Sink–versus–Source Mismatch (Note 3) V

out

= 0.5 x V+ 12 %

Output Voltage Range (Note 3) I

out

variation ≤ 20% 0.5 to V+ – 0.5 V V

NOTES:

1. Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.

2. See Rx Pin Description for external resistor values.

3. This parameter is guaranteed for a given temperature within – 40 to 85°C and given supply voltage within 2.7 to 5.5 V.

4. Applicable for the Rx/φV or Rx′/φV′ reference pin tied to the GND or GND′ pin through a resistor. See Pin Descriptions for suggested resistor values.

AC INTERFACE CHARACTERISTICS

(V+ = V+i = 2.7 to 5.5 V , GND = GNDi, TA = – 40 to 85°C, CL = 25 pF, Input tr = tf = 10 ns)

Symbol

Parameter

Guaranteed

Limit

Unit

clk

Serial Data CLK Frequency (Figure 1) NOTE: Refer to Clock tw below

dc to 2.0 MHz

PLH

, t

PHL

Maximum Propagation Delay, CLK to Output A (Selected as Data Out) (Figures 1 and 5) 200 ns

PZL

, t

PLZ

Maximum Propagation Delay, ENB to Output A (Selected as Port) (Figures 2 and 6) 200 ns

TLH

, t

THL

Maximum Output Transition T ime, Output A; t

THL

only, on Output A when Selected as Port

(Figures 1, 5, and 6)

200 ns

Maximum Input Capacitance — Din, CLK, ENB 10 pF

TIMING REQUIREMENTS (V+ = V+

= 2.7 to 5.5 V , GND = GNDi, TA = – 40 to 85°C, Input tr = tf = 10 ns unless otherwise indicated)

Symbol

Parameter

Guaranteed

Limit

Unit

tsu, t

Minimum Setup and Hold Times, Din versus CLK (Figure 3) 50 ns

tsu, th, t

rec

Minimum Setup, Hold, and Recovery Times, ENB versus CLK (Figure 4) 100 ns

Minimum Pulse Width, ENB (Figure 4) * cycles

Minimum Pulse Width, CLK (Figure 1) 250 ns

tr, t

Maximum Input Rise and Fall Times — CLK (Figure 1) 100 µs

*The minimum limit is 3 REFin cycles or 195 fin or fin′ cycles with selection of a 64/65 prescale ratio or 99 fin or fin′ cycles with selection of a 32/33

prescale ratio, whichever is greater.

Page 5

MC145220MOTOROLA

Figure 1. Figure 2.

10%

V+ GND

1/f

clk

OUTPUT A

(DATA OUT)

CLK

90%

50%

90%

50%

10%

PLH

PHL

TLH

THL

ENB

OUTPUT A

10%

V+

GND

50%

PLZ

50%

PZL

CLK

50%

VALID

50%

V+

GND

V+

GND

Figure 3.

CLK

ENB

50%

FIRST

CLOCK

LAST

CLOCK

rec

50%

V+

GND

V+

GND

Figure 4.

TEST POINT

DEVICE UNDER

TEST

CL*

*Includes all probe and fixture capacitance.

TEST POINT

DEVICE UNDER

TEST

CL*

*Includes all probe and fixture capacitance.

V+

7.5 k

Ω

Figure 5. Figure 6.

Page 6

MC145220 MOTOROLA 6

LOOP SPECIFICATIONS (V+ = V+

= 2.7 to 5.5 V unless otherwise indicated, GND = GNDi, TA = – 40 to 85°C)

Guaranteed

Operating Range

Symbol Parameter Test Condition Min Max Unit

Input Sensitivity Range, fin or fini

(Figure 7)

40 MHz ≤ frequency < 300 MHz 300 MHz ≤ frequency < 700 MHz 700 MHz ≤ frequency < 1100 MHz

– 2 – 5

– 16

8 6 4

dBm*

∆P

Difference Allowed Between fin and fini

10 dB

—

Isolation Between fin and fini

15 dB

ref

Input Frequency, REFin Externally Driven in Reference Mode (Figure 8)

Vin ≥ 400 mV p–p, R Counter set to divide ratio such that fR ≤ 1 MHz, REF Counter set to divide ratio such that REF

out

≤ 5 MHz

4 27

MHz

XTAL

Crystal Frequency, Crystal Mode (Figure 9) C1 ≤ 30 pF, C2 ≤ 30 pF, Includes Stray

Capacitance; R Counter and REF Counter same as above V+ = 2.7 V

V+ = 3.5 V V+ = 4.5 V V+ = 5.5 V

2 2 2 2

10 13 15 15

MHz

out

Output Frequency, REF

out

(Figures 10 and 12) CL = 25 pF dc 5 MHz

f Operating Frequency of the Phase Detectors dc 1 MHz

Output Pulse Width, φR, φV, φRi

, φVi

(Figures 11 and 12)

fR in Phase with fV, CL = 25 pF 16 125 ns

Input Capacitance, REF

— 5 pF

*Power level at the input to the dc block.

Page 7

MC145220MOTOROLA

DEVICE UNDER

TEST

POINT

OUTPUT A

Figure 7. Test Circuit

(fv)

Figure 8. Test Circuit — Reference Mode

BLOCK

Ω

PAD

SINE WAVE

GENERAT OR

Ω

in GND V+

GNDiV+

DEVICE UNDER

TEST

POINT

REF

OUTPUT A

(fR)

0.01 µF

Ω

SINE WAVE

GENERAT OR

Ω

GND V+

GNDiV+

TEST

POINT

REF

out

*Characteristic Impedance

NOTE: Alternately, the 50 Ω pad may be a T network.

DEVICE

UNDER

TEST

POINT

REF

OUTPUT A

Figure 9. Test Circuit — Crystal Mode

(fR)

REF

out

GND V+

GNDiV+

REF

out

1/f

out

50%

Figure 10. Switching Waveform

OUTPUT

50%

Figure 11. Switching Waveform

TEST POINT

DEVICE

UNDER

TEST

CL*

*Includes all probe and fixture capacitance.

Figure 12. Test Circuit

Page 8

MC145220 MOTOROLA 8

Frequency

(MHz)

Point

Impedance (Ω)

3 V Supply

5 V Supply

50 400 800

1100

E F G H

1900 + j 149

878 + j 703 705 + j 208

215 – j 69.3

1930 + j 214

746 + j 741 626 + j 327

243 – j 61.3

Frequency

(MHz)

Point

Impedance (Ω)

3 V Supply

5 V Supply

50 400 800

1100

A B C D

1900 – j 157 1440 – j 228

552 – j 380 196 – j 141

1970 – j 102

1510 + j 19 671 – j 334

223 – j 147

fin (PIN 8) – SOG PACKAGE

′

(PIN 13) – SOG PACKAGE

Figure 13. Nominal Input Impedance of fin and fin′ — Series Format (R + jX)

(50 – 1100 MHz)

–j2

–j1

fin (PIN 8) SOG PACKAGE

–j2

–j1

fin′

(PIN 13)

SOG PACKAGE

Page 9

MC145220MOTOROLA

PIN DESCRIPTIONS

DIGITAL INTERFACE PINS D

Serial Data Input (Pin 20)

The bit stream begins with the MSB and is shifted in on the low–to–high transition of CLK. The bit pattern is 1 byte (8 bits) long to access the C or configuration registers, 2 bytes (16 bits) to access the first buffer of the R registers, or 3 bytes (24 bits) to access the A registers (see Table 1). The values in the registers do not change during shifting because the transfer of data to the registers is controlled by ENB

NOTE

The value programmed for the N counter must be greater than or equal to the value of the A counter.

The 13 LSBs of the R registers are double–buffered. As indicated above, data is latched into the first buffer on a 16–bit transfer. (The 3 MSBs are not double–buffered and have an immediate effect after a 16–bit transfer.) The two second buffers of the R register contain the two 13–bit divide ratios for the R counters. These second buffers are loaded with the contents of the first buffer as follows. Whenever the A register is loaded, the Rs (second) buffer is loaded from the R (first) buffer . Similarly , whenever the Ai register is loaded, the Rsi (second) buffer is updated from the R (first) buffer. This allows presenting new values to the R, A, and N counters simultaneously. Note that two different R counter divide ratios may be established: one for the main PLL and another for PLLi.

The bit stream does not need address bits due to the innovative BitGrabber Plus registers. A steering bit is used to direct data to either the main PLL or PLLi section of the chip. Data is retained in the registers over a supply range of 2.7 to

5.5 V. The formats are shown in Figures 14, 15, and 16.

Din typically switches near 50% of V+ to maximize noise immunity. This input can be directly interfaced to CMOS devices with outputs guaranteed to switch near rail–to–rail. When interfacing to NMOS or TTL devices, either a level shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 kΩ to 10 kΩ must be used. Parameters to consider when sizing the resistor are worst–case IOL of the driving device, maximum tolerable power consumption, and maximum data rate.

Table 1. Register Access

(MSBs are shifted in first; C0, R0, and A0 are the LSBs)

Number

of Clocks

Accessed

Bit

Nomenclature

Other Values ≤ 32

Values > 32

C Registers

R Register,

First Buffer A Registers Not Allowed See Figures

24 to 27

C7, C6, C5, . . ., C0

R15, R14, R13, . . ., R0

A23, A22, A21, . . ., A0

CLK Serial Data Clock Input (Pin 19)

Low–to–high transitions on CLK shift bits available at the Din pin, while high–to–low transitions shift bits from Output A (when configured as Data Out, see Pin 10). The 24–1/2 stage shift register is static, allowing clock rates down to dc in a continuous or intermittent mode.

Eight clock cycles are required to access the C registers. Sixteen clock cycles are needed for the first buffer of the R register. Twenty–four cycles are used to access the A registers. See Table 1 and Figures 14, 15, and 16. The number of clocks required for cascaded devices is shown in Figures 25 through 27.

CLK typically switches near 50% of V+ and has a Schmitt– triggered input buffer. Slow CLK rise and fall times are allowed. See the last paragraph of Din for more information.

NOTE

To guarantee proper operation of the power–on reset (POR) circuit, the CLK pin must be held at GND (with ENB

being a don’t care) or ENB must be held at the potential of the V+ pin (with CLK being a don’t care) during power–up. Floating, toggling, or having these pins in the wrong state during power–up does not harm the chip, but causes two potentially undesirable effects. First, the outputs of the device power up in an unknown state. Second, if two devices are cascaded, the A Registers must be written twice after power up. After these two accesses, the two cascaded chips perform normally .

ENB Active–Low Enable Input (Pin 11)

This pin is used to activate the serial interface to allow the

transfer of data to/from the device. When ENB

is in an inactive high state, shifting is inhibited and the port is held in the initialized state. To transfer data to the device, ENB

(which must start inactive high) is taken low, a serial transfer is made via Din and CLK, and ENB

is taken back high. The low–to–high transition on ENB transfers data to the C or A registers and first buffer of the R register, depending on the data stream length per Table 1.

NOTE

Transitions on ENB

must not be attempted while CLK is high. This puts the device out of synchronization with the microcontroller. Resynchronization occurs whenever ENB

is high and CLK is

low.

This input is Schmitt–triggered and switches near 50% of V+, thereby minimizing the chance of loading erroneous data into the registers. See the last paragraph of Din for more information.

For POR information, see the note for the CLK pin.

Page 10

MC145220 MOTOROLA 10

OUTPUT A Configurable Digital Output (Pin 10)

Output A is selectable as fR, fV, fRi

, fVi

, Data Out, or Port. Bits A21 and A22 and the steering bit (A23) control the selection; see Figure 15. When selected as Port, the pin becomes an open–drain N–channel MOSFET output. As such, a pullup device is needed for pin 10. With all other selections, the pin is a totem–pole (push–pull) output.

If A22 = A21 = high, Output A is configured as fR when the

steering bit is low and fRi

when the bit is high. These signals are the buffered outputs of the 13–stage R counters. The signals appear as normally low and pulse high. The signals can be used to verify the divide ratios of the R counters. These ratios extend from 10 to 8191 and are determined by the binary value loaded into bits R0 – R12 in the R register . Also, direct access to the phase detectors via the REFin pin is allowed by choosing a divide value of one. See Figure 16. The maximum frequency at which the phase detectors operate is 1 MHz. Therefore, the frequency of fR and fRi

should

not exceed 1 MHz.

If A22 = high and A21 = low, Output A is configured as f

when the steering bit is low and fVi

when the bit is high. These signals are the buffered outputs of the 12–stage N counters. The signals appear as normally low and pulse high. The signals can be used to verify the operation of the prescalers, A counters, and N counters. The divide ratio between the fin or fin′ input and the fV or fVi

signal is N x P + A. N is the divide ratio of the N counter, P is 32 with a 32/33 prescale ratio or 64 with a 64/65 prescale ratio, and A is the divide ratio of the A counter. These ratios are determined by bits loaded into the A registers. See Figure 15. The maximum frequency at which the phase detectors operate is 1 MHz. Therefore, the frequency of fV and fVi

should not

exceed 1 MHz.

If A22 = low and A21 = high, Output A is configured as Data Out. This signal is the serial output of the 24–1/2 stage shift register. The bit stream is shifted out on the high–to–low transition of the CLK input. Upon power up, Output A is automatically configured as Data Out to facilitate cascading devices.

If A22 = A21 = low, Output A is configured as Port. This signal is a general–purpose digital output which may be used as an MCU port expander. This signal is low when the Port bit (C1) of the C register is low, and high impedance when the Port bit is high. See Figure 14.

REFERENCE PINS REFin and REF

out

Reference Oscillator Input and Output (Pins 1 and 2)

Configurable Pins for a Crystal or an External Reference. This pair of pins can be configured in one of two modes: the crystal mode or the reference mode. Bits R13, R14, and R15 in the R register control the modes as shown in Figure 16.

In the crystal mode, these pins form a reference oscillator when connected to terminals of an external parallel–resonant crystal. Frequency–setting capacitors of appropriate

values, as recommended by the crystal supplier, are connected from each of the two pins to ground (up to a maximum of 30 pF each, including stray capacitance). An external resistor of 1 MΩ to 15 MΩ is connected directly across the pins to ensure linear operation of the amplifier. The required connections for the crystal are shown in Figure 9. To turn on the oscillator, bits R15, R14, and R13 must have an octal value of one (001 in binary). This is the active–crystal mode shown in Figure 16. In this mode, the crystal oscillator runs and the R Counter divides the crystal frequency, unless the part is in standby. If the part is placed in standby via the C or C′ register, the oscillator runs, but the R or R′ counter is stopped, respectively. However, if bits R15 to R13 have a value of 0, the oscillator is stopped, which saves additional power. This is the shut–down crystal mode shown in Figure 16, and can be engaged whether in standby or not.

In the reference mode, REFin (pin 1) accepts a signal from an external reference oscillator, such as a TCXO. A signal swinging from at least the VIL to VIH levels listed in the Elec- trical Characteristics table may be directly coupled to the pin. If the signal is less than this level, ac coupling must be used as shown in Figure 8. The ac–coupled signal must be at least 400 mV p–p. Due to an on–board resistor which is engaged in the reference modes, an external biasing resistor tied between REFin and REF

out

is not required.

With the reference mode, the REF

out

pin is configured as the output of a divider. As an example, if bits R15, R14, and R13 have an octal value of seven, the frequency at REF

out

is the R EFin frequency divided by 16. In addition, Figure 16 shows how to obtain ratios of eight, four, and two. A ratio of one–to–one can be obtained with an octal value of three. Upon power up, a ratio of eight is automatically initialized. The maximum frequency capability of the REF

out

pin is 5 MHz for large output swings (VOH to VOL) and 25 pF loads. Therefore, for REFin frequencies above 5 MHz, the one–to–one ratio may not be used for these large signal swing and large CL requirements. Likewise, for RE Fin frequencies above 10 MHz, the ratio must be more than two.

If REF

out

is unused, an octal value of two should be used

for R15, R14, and R13 and the RE F

out

pin should be floated. A value of two allows REFin to be functional while disabling REF

out

, which minimizes dynamic power con-

sumption and electromagnetic interference (EMI).

LOOP PINS fin, f

and fini

, fini

Frequency Inputs (Pins 8, 7 and 13, 14)

These pins feed the onboard RF amplifiers which drive the prescalers. These inputs may be fed differentially. However, they usually are used in single–ended configurations (shown in Figure 7). Note that fin is driven while f

must be tied to ac ground (via capacitor). The signal sources driving these pins originate from external VCOs.

Motorola does not recommend driving f

while terminating fin because this configuration is not tested for sensitivity. The sensitivity is dependent on the frequency as shown in the

Loop Specifications table.

Page 11

MC145220MOTOROLA

out/φR

, PD

out

/φRi

Single–Ended Phase/Frequency Detector Outputs (Pins 4 and 17)

When the C2 bits in the C or Ci registers are low, these pins are independently configured as single–ended outputs PD

out

or PD

out

, respectively. As such, each pin is a three– state current–source/sink output for use as a loop error signal when combined with an external low–pass filter. The phase/frequency detector is characterized by a linear transfer function. The operation of the phase/frequency detector is described below and is shown in Figure 17.

POL bit (C0) in the C register = low (see Figure 14) Frequency of fV > fR or Phase of fV Leading fR: current–

sinking pulses from a floating state

Frequency of fV < fR or Phase of fV Lagging fR: current–

sourcing pulses from a floating state

Frequency and Phase of fV = fR: essentially a floating

state; voltage at pin determined by loop filter POL bit (C0) = high Frequency of fV > fR or Phase of fV Leading fR: current–

sourcing pulses from a floating state Frequency of fV < fR or Phase of fV Lagging fR: current–

sinking pulses from a floating state Frequency and Phase of fV = fR: essentially a floating

state; voltage at pin determined by loop filter These outputs can be enabled, disabled, and inverted via

the C and Ci registers. If desired, these pins can be forced to the floating state by utilization of the standby feature in the C or Ci registers (bit C6). This is a patented feature.

The phase detector gain is controllable by bits C4 and C5:

gain (in amps per radian) = PD

out

current in amps divided

by 2π.

out/φR

, Rx/

φV and PD

out

/φRi

, Rxi/φVi Double–Ended Phase/Frequency Detector Outputs (Pins 4, 5 and 17, 16)

When the C2 bits in the C or Ci registers are high, these two pairs of pins are independently configured as double– ended outputs φR, φV or φRi

, φVi

, respectively. As such, these outputs can be combined externally to generate a loop error signal. Through use of a Motorola patented technique, the detector’s dead zone has been eliminated. Therefore, the phase/frequency detector is characterized by a linear transfer function. The operation of the phase/frequency detectors are described below and are shown in Figure 17.

POL bit (C0) in the C register = low (see Figure 14) Frequency of fV > fR or Phase of fV Leading fR: φV =

negative pulses, φR = essentially high

Frequency of fV < fR or Phase of fV Lagging fR: φV =

essentially high, φR = negative pulses

Frequency and Phase of fV = fR: φV and φR remain

essentially high, except for a small minimum time period

when both pulse low in phase POL bit (C0) = high Frequency of fV > fR or Phase of fV Leading fR: φR =

negative pulses, φV = essentially high Frequency of fV < fR or Phase of fV Lagging fR: φR =

essentially high, φV = negative pulses Frequency and Phase of fV = fR: φV and φR remain

essentially high, except for a small minimum time period

when both pulse low in phase

These outputs can be enabled, disabled, or interchanged via C register bits C6 or C0. This is a patented feature. Note that when disabled in standby, these outputs are forced to their rest condition (high state). See Figure 14.

The φR and φV output signals swing from approximately GND to V+.

LD and LD

Lock Detector Outputs (Pins 3 and 18)

Each output is essentially at a high–impedance state with very narrow low–going pulses of a few nanoseconds when the respective loop is locked (fR and fV of the same phase and frequency). The output pulses low when fV and fR are out of phase or different frequencies. LD is the logical ANDing of φR and φV, while LDi is the logical ANDing of φRi

and

φVi

. See Figure 17.

Upon power up, on–chip initialization circuitry forces LD and LDi to the high–impedance state. These pins are low during standby . If unused, LD should be tied to GND and LD

should be tied to GNDi.

These outputs have open–drain N–channel MOSFET drivers. This facilitates a wired–OR function. See Figure 21.

Rx/φV and Rxi/φVi External Current Setting Resistors (Pins 5 and 16)

When the C2 bits in the C or Ci registers are low, these two pins are independently configured as current setting pins Rx or Rxi, respectively. As such, resistors tied between each of these pins and GND and GNDi, in conjunction with bits C4 and C5 in the C and Ci registers, determine the amount of current that the PD

out

pins sink and source. When bits C4 and C5 are both set high, the maximum current is obtained; see Table 2 for other values of current.

Table 2. PD

out

or PD

out

′ Current

C5 C4 Current

0 0 1 1

0 1 0 1

5% 50% 80%

100%

The formula for determining the value of Rx or Rxi is as

follows.

Rx =

V1 – V2

where Rx is the value of external resistor in ohms, V1 is the supply voltage, V2 is 1.5 V for a reference current through Rx of 100 µA or 1.745 V for a reference current of 200 µA, and I is the reference current flowing through Rx or Rxi.

The reference current flowing through Rx or Rx′ is multiplied by a factor of approximately 10 (in the 100% current mode) and delivered by the PD

out

or PD

out

′ pin, respectively . To achieve a maximum phase detector output current of 1 mA, the resistor should be about 15 kΩ when a 3 V supply is employed. See Table 3.

Table 3. Rx Values

Supply

Voltage

out

or PD

out

′

Current in

100% Mode

3 V 5 V

15 kΩ 16 kΩ

1 mA 2 mA

Page 12

MC145220 MOTOROLA 12

Do not use a decoupling capacitor on the Rx or Rxi pin. Use of a capacitor causes undesirable current spikes to appear on the phase detector output when invoking the standby mode.

POWER SUPPLY PINS V+ and V+

Positive Supply Potentials (Pins 9 and 12)

V+ supplies power to the main PLL, reference circuit, and a portion of the serial port. V+i supplies power to PLLi and a portion of the serial port. Both V+ and V+i must be at the same voltage level and may range from 2.7 V to 5.5 V with respect to the GND and GNDi pins.

For optimum performance, V+ should be bypassed to GND and V+i bypassed to GNDi using separate low–inductance capacitors mounted very close to the MC145220. Lead lengths and printed circuit board traces to the capacitors should be minimized. (The very fast switching speed of the device can cause excessive current spikes on the power leads if they are improperly bypassed.)

GND and GND

Grounds (Pins 6 and 15)

The GND pin is the ground for the main PLL and GNDi is the ground for PLLi.

Page 13

MC145220MOTOROLA

ENB

CLK

C7 C6 C5 C4 C3 C2 C1 C0

12345678

MSB LSB

*At this point, the new byte is transferred to the C or Ci register and stored. No other registers are affected.

C7 – Steer: Used to direct the data to either the C or Ci register. A low level directs data to the C register; a high

level is for the Ci register.

C6 – Standby: When set high, places both the main PLL and PLLi (when C6 is set in the C register) or PLLi only

(when C6 is set in the Ci register) in the standby mode for reduced power consumption. The associated PD

out

is forced to the floating state, the associated counters (A, N, and R) are inhibited from counting, the associated Rx current is shut off, and the associated prescaler stops counting and is placed in a low current mode. The associated double–ended phase/frequency detector outputs are forced to a high level. In standby, the associated LD output is placed in the low–state, thus indicating “not locked” (open loop). During standby, data is retained in all registers and any register may be accessed.

In standby, the condition of the REF/OSC circuitry is determined by bits R13, R14, and R15 in the R register per Figure 16. However, if REF

out

static low

is selected, the internal feedback resistor is disconnected and the REFin is inhibited when both PLL and PLLi are placed in standby via the C register. Thus, the REFin only presents a capacitive load. Note: PLL/PLLi standby does not affect the other modes of the REF/OSC circuitry as determined by bits R13, R14, and R15 in the R register. The PLLi standby mode (controlled from the Ci register) has no effect on the REF/OSC circuit.

When C6 is reset low, the associated PLL (or PLLs) is (are) taken out of standby in two steps. First, the REFin (only in 1 mode, PLL/PLLi in standby) resistor is reconnected, REFin (only 1 mode) is gated on, all counters are enabled, and the Rx current is enabled. Any fR and fV signals are inhibited from toggling the phase/frequency detectors and lock detectors. Second, when the appropriate fR pulse occurs, the A and N counters are jam loaded, the prescaler is gated on, and the phase/frequency and lock detectors are initialized. Immediately after the jam load, the A, N, and R counters begin counting down together. At this point, the fR and fV pulses are enabled to the phase and lock detectors. (Patented feature.)

C5, C4 – I2, I1: Independently controls the PD

out

or PD

out

′ source/sink current per Table 2. With both bits high, the

maximum current (as set by Rx or Rx′) is available. POR forces C5 and C4 to high levels.

C3 – Spare: Unused

C2 – PDA/B: Independently selects which phase/frequency detector is to be used. When set high, the double–ended

detector is selected with outputs φR and φV or φRi

and φVi

. When reset low, the current source/sink

detector is selected with outputs PD

out

or PD

out

. In the second case, the appropriate Rx or Rxi pin

is tied to an external resistor. POR forces C2 low.

C1 – Port: When the Output A pin is selected as “Port” via bits A22 and A21, C1 of the C register determines

the state of Output A. When C1 is set high, Output A is forced to the high–impedance state; C1 low forces Output A low. The Port bit is not affected by the standby mode. Note: C1 of the Ci register is not used in any mode.

C0 – POL: Selects the output polarity of the associated phase/frequency detectors. When set high, this bit inverts

the associated current source/sink output and interchanges the associated double–ended output relative to the waveforms in Figure 17. Also, see the phase detector output pin descriptions for more information. This bit is cleared low at power up.

Figure 14. C and Ci Register Accesses and Format (8 Clock Cycles are Used)

Page 14

MC145220 MOTOROLA 14

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A23

NOTE 3

234567891011121314151617181920212223241

MSB LSB

001

010

PORT

DATA OUTff

BINARY

VALUE

OUTPUT A

FUNCTION

(NOTES 1 AND 4)

000

012

A COUNTER = 0

A COUNTER = 1

A COUNTER = 2

A COUNTER = 3

A COUNTER = 62

4 1 NOT ALLOWED

HEXADECIMAL VALUE

FOR A COUNTER

A COUNTER = 63

NOT ALLOWED

...

F NOT ALLOWED

÷÷÷

...

NOTES:

1. A power-on initialize circuit forces the Output A function to default to Data Out.

2. The values programmed for the N counter must be greater than or equal to the values programmed for the A counter. This results in a total divide value = N x P + A where

3. At this point, the three new bytes are transferred to the A register if bit A23 is a “0” or A register if A23 is a “1”. In addition, the 13 LSBs in the first buffer of the R register are

ENB

CLK

Figure 15. A and Ai Register Accesses and Format (24 Clock Cycles are Used)

32/33

64/65

PRESCALE

RATIO

MAIN PLL, A REGISTER

PLL , A REGISTER

STEER

N is the value programmed for the N counter, P is 32 if bit A20 is low or 64 if A20 is high, and A is the value programmed for the A counter.

000

111

012

NOT ALLOWED

...

N COUNTER = 4094

N COUNTER = 4095

HEXADECIMAL VALUE

FOR N COUNTER

014

N COUNTER = 19

N COUNTER = 18÷N COUNTER = 20

(NOTE 4)

AND BITS A7 AND A6

OR f

transferred to the R register’s relative second buffer, Rs or Rs . Thus, the R, N, and A (or R , N , and A ) counters can be presented new divide ratios at the same time. The first

buffer of the R register is not affected. The C or C registers are not affected.

4. A “0” for the Steering bit allows selection of f , f , Data Out, or Port by bits A21 and A22. A “1” for the Steering bit allows selection of f , , f , Data Out, or Port.

Page 15

MC145220MOTOROLA

ENB

CLK

123

45 78

MSB LSB

910

11 12 13 14 15 16

0 0 0 0 0 0 0 0 0 0 0 0 0

· F F

0 0 0 0 0 0 0 0 0 0 0 0 0

· F F

0 1 2 3 4 5 6 7 8

9 A B C

· E F

NOT ALLOWED R COUNTER =

1 (NOTE 6) NOT ALLOWED NOT ALLOWED NOT ALLOWED NOT ALLOWED NOT ALLOWED NOT ALLOWED NOT ALLOWED NOT ALLOWED R COUNTER =

10 R COUNTER =

11 R COUNTER =

R COUNTER = ÷8190 R COUNTER =

8191

HEXADECIMAL VALUE

0 0 0 0 0 0 0 0 0 0 0 0 0

· 1 1

BINARY VALUE

0 1 2

3 4 5 6 7

CRYST AL MODE, SHUT DOWN CRYST AL MODE, ACTIVE REFERENCE MODE, REFin ENABLED AND REF

out

STATIC LOW

REFERENCE MODE, REF

out

= REFin (BUFFERED)

REFERENCE MODE, REF

out

= REFin/2

REFERENCE MODE, REF

out

= REFin/4

REFERENCE MODE, REF

out

= REFin/8 (NOTE 3)

REFERENCE MODE, REF

out

= REFin/16

OCTAL VALUE

NOTES:

1. Bits R15

– R13 control the configurable “Buffer and Control” block (see Block Diagram).

2. Bits R12 – R0 control the “13–stage R counter” blocks (see Block Diagram).

3. A power–on initialize circuit forces a default REFin to REF

out

ratio of eight.

4. At this point, bits R13, R14, and R15 are stored and sent to the “Buffer and Control” block in the Block Diagram. Bits R0

– R12 are loaded

into the first buffer in the double–buffered section of the R register . Therefore, the R or R′ counter divide ratio is not altered yet and retains the previous ratio loaded. The C, Ci, A, and Ai registers are not affected.

5. Bits R0 – R12 are transferred to the second buffer of the R register (Rs in the Block Diagram) on a subsequent 24–bit write to the A register. The bits are transferred to Rsi on a subsequent 24–bit write to the Ai register. The respective R counter begins dividing by the new ratio after completing the rest of its present count cycle.

6. Allows direct access to reference input of phase/frequency detectors.

NOTE

R1 R0R5

R3 R2

R15 R14

R13 R12 R11 R10

R8 R7 R6

Figure 16. R Register Access and Format (16 Clock Cycles are Used)

Page 16

MC145220 MOTOROLA 16

NOTES:

1. At this point, when both fR and fV are in phase, the output source and sink circuits are turned on for a short interval.

2. The PD

out

either sources or sinks current during out–of–lock conditions. When locked in phase and frequency, the output

is mostly in a floating condition and the voltage at that pin is determined by the low–pass filter capacitor. PD

out

, φR, and φ

are shown with the polarity bit (POL) = low; see Figure 14 for POL.

3. VH = High voltage level, VL = Low voltage level.

4. The waveforms are applicable to both the main PLL and PLL′.

REFERENCE

REFin

FEEDBACK

fin

(N x P + A)

out

SOURCING CURRENT

HIGH IMPEDANCE

FLOAT

SINKING CURRENT

NOTE 1

Figure 17. Phase/Frequency Detectors and Lock Detector Output Waveforms

Page 17

MC145220MOTOROLA

DESIGN CONSIDERA TIONS

CRYSTAL OSCILLATOR CONSIDERATIONS

The following options may be considered to provide a reference frequency to Motorola’s CMOS frequency synthesizers.

Use of a Hybrid Crystal Oscillator

Commercially available temperature–compensated crystal oscillators (TCXOs) or crystal–controlled data clock oscillators provide very stable reference frequencies. An oscillator capable of CMOS logic levels at the output may be direct or dc coupled to REFin. If the oscillator does not have CMOS logic levels on the outputs, capacitive or ac coupling to REF

must be used. See Figure 8.

For additional information about TCXOs and data clock oscillators, please consult the latest version of the

eem Elec-

tronic Engineers Master Catalog,

the

Gold Book,

or similar

publications.

Design an Off–Chip Reference

The user may design an off–chip crystal oscillator using discrete transistors or ICs specifically developed for crystal oscillator applications, such as the MC12061 MECL device. The reference signal from the MECL device is ac coupled to REFin. (See Figure 8.) For large amplitude signals (standard CMOS logic levels), dc coupling may be used.

Use of the On–Chip Oscillator Circuitry

The on–chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source frequency. A fundamental mode crystal, parallel resonant at the desired operating frequency, should be connected as shown in Figure 18.

The crystal should be specified for a loading capacitance, CL, which does not exceed approximately 20 pF when used near the highest operating frequency of the MC145220. Assuming R1 = 0 Ω, the shunt load capacitance, CL, presented across the crystal can be estimated to be:

CL =

CinC

out

Cin + C

out

+ Ca + C

stray

C1 • C2

C1 + C2

where

Cin = 5 pF (see Figure 19)

out

= 6 pF (see Figure 19)

Ca = 1 pF (see Figure 19)

C1 and C2 = external capacitors (see Figure 18)

stray

= the total equivalent external circuit stray

capacitance appearing across the crystal terminals

The oscillator can be “trimmed” on–frequency by making either a portion or all of C1 variable. The crystal and associated components must be located as close as possible to the REFin and REF

out

pins to minimize distortion, stray capacitance, stray inductance, and startup stabilization time. Circuit stray capacitance can also be handled by adding the appropriate stray value to the values for Cin and C

out

. For

this approach, the term C

stray

becomes zero in the above

expression for CL.

Power is dissipated in the effective series resistance of the crystal, Re, in Figure 20. The maximum drive level specified by the crystal manufacturer represents the maximum stress

that the crystal can withstand without damage or excessive shift in operating frequency. R1 in Figure 18 limits the drive level. The use of R1 is not necessary in most cases.

To verify that the maximum dc supply voltage does not cause the crystal to be overdriven, monitor the output frequency (fR) at Output A as a function of supply voltage. (REF

out

is not used because loading impacts the oscillator.) The frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal decreases in frequency or becomes unstable with an increase in supply voltage. The operating supply voltage must be reduced or R1 must be increased in value if the overdriven condition exists. Note that the oscillator start–up time is proportional to the value of R1.

Through the process of supplying crystals for use with CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can prove very helpful. See Table 4.

Figure 18. Pierce Crystal Oscillator Circuit

R1*

C2C1

FREQUENCY

SYNTHESIZER

REF

out

REF

*May be needed in certain cases. See text.

Figure 19. Parasitic Capacitances of the

Amplifier and C

stray

out

REF

out

stray

Figure 20. Equivalent Crystal Networks

NOTE: V alues are supplied by crystal manufacturer

(parallel resonant crystal).

121

ReX

Page 18

MC145220 MOTOROLA 18

RECOMMENDED READING:

Gardner, Floyd M.,

Phaselock Techniques (second edition).

New York, Wiley–Interscience, 1979.

Manassewitsch, Vadim,

Frequency Synthesizers: Theory and Design (second edition).

New York, Wiley–Interscience, 1980.

Blanchard, Alain,

Phase–Locked Loops: Application to Coherent Receiver Design.

New York, Wiley–Interscience, 1976.

Egan, William F.,

Frequency Synthesis by Phase Lock.

New York, Wiley–Interscience, 1981.

Rohde, Ulrich L.,

Digital PLL Frequency Synthesizers Theory and Design.

Englewood Cliffs, NJ, Prentice–Hall, 1983.

Berlin, Howard M.,

Design of Phase–Locked Loop Circuits, with Experiments.

Indianapolis, Howard W. Sams and Co., 1978.

Kinley, Harold,

The PLL Synthesizer Cookbook.

Blue Ridge Summit, PA, Tab Books, 1980.

Seidman, Arthur H.,

Integrated Circuits Applications Handbook

, Chapter 17, pp. 538–586. New Y ork, John Wiley & Sons.

Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,”

EDN

. March 5, 1980. AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970. AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from

Electronic Design,

1987.

AN1253, An Improved PLL Design Method Without ωn and ζ, Motorola Semiconductor Products, Inc., 1995.

–

VCO

1 + sRC

NOTE:

For (A), using Kφ in amps per radian with the filter’s impedance transfer function, Z(s), maintains units of volts per radian for the detector/ filter combination. Additional sideband filtering can be accomplished by adding a capacitor C′ across R. The corner ωc = 1/RC′ should be chosen such that ωn is not significantly affected.

VCO

out

radians per volt

Either loop filter (A) or (B) is frequently followed by additional sideband filtering to further attenuate fR–related VCO sidebands. This

additional filtering may be active or passive.

ωnRC

Z(s) =

ωn=

Page 20

MC145220 MOTOROLA 20

20 19

16 15

LOW–PASS

FILTER

′

VCO

′

OUTPUT

′

BUFFER

′

1 2

LOW–PASS

FILTER

VCO

OUTPUT

5 6

MCU

NOTE 4

GENERAL PURPOSE

DIGITAL OUTPUT

REF

out

Rx/

GND

V+

OUTPUT A (PORT)

CLK

out

i/φRi

Rxi/

φVi

GND

fini

V+

ENB

BUFFER

MC145220

NOTE 5

NOTE 6

NOTES:

1. The PD

out

output is fed to an external loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page for additional informa-

tion.

2. For optimum performance, bypass the V+ and V+i pins to GND and GNDi with low–inductance capacitors.

3. The R counter is programmed for a divide value = REFin/fR. Typically , fR is the tuning resolution required for the VCO. Also, the VCO frequency divided by fR = NT = N S P + A; this determines the values (N, A) that must be programmed into the N and A counters, respectively. P is the lower divide ratio of the dual–modulus prescaler (i.e., 32 or 64).

4. Pull–up voltage must be at the same potential as the V+ pin or less. Pull–up device other than a resistor may be used. (Pull–up device not required when Output A is configured as fR, fR′, fV, fV′, DATA OUT.)

5. LD and LD′ are open–drain outputs. This allows the wired–OR configuration shown. Note that R1 and Q1 form the “pull–up device”.

6. Use of Q1 is optional and depends on loading.

Figure 21. Application Showing Use of the Two Single–Ended Phase/Frequency Detectors

Page 21

MC145220MOTOROLA

20 19

16 15

LOW–PASS

FILTER

′

VCO

′

OUTPUT

′

BUFFER

′

1 2

LOW–PASS

FILTER

VCO

OUTPUT

5 6

MCU

NOTE 4

GENERAL PURPOSE

DIGITAL OUTPUT

REF

out

Rx/

GND

V+

OUTPUT A (PORT)

CLK

out

i/φRi

Rxi/

φVi

GND

fini

V+

ENB

BUFFER

MC145220

NOTE 5

NOTE 6

NOTES:

1. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range of the op amp used in the combiner/loop filter.

2. For optimum performance, bypass the V+ and V+i pins to GND and GNDi with low–inductance capacitors.

3. The R counter is programmed for a divide value = REFin/fR. Typically, fR is the tuning resolution required for the VCO. Also, the VCO frequency divided by fR = NT = N S P + A; this determines the values (N, A) that must be programmed into the N and A counters, respectively. P is the lower divide ratio of the dual–modulus prescaler (i.e., 32 or 64).

5. LD and LD′ are open–drain outputs. This allows the wired–OR configuration shown. Note that R1 and Q1 form the “pull–up device”.

6. Use of Q1 is optional and depends on loading.

Figure 22. Application Showing Use of the Two Double–Ended Phase/Frequency Detectors

Page 22

MC145220 MOTOROLA 22

20 19

16 15

LOW–PASS

FILTER

′

VCO

′

OUTPUT

′

BUFFER

′

1 2

LOW–PASS

FILTER

VCO

OUTPUT

5 6

MCU

NOTE 4

GENERAL PURPOSE

DIGITAL OUTPUT

REF

out

Rx/

GND

V+

OUTPUT A (PORT)

CLK

out

′/φR′

Rxi/

φVi

GND

fini

V+

ENB

BUFFER

MC145220

NOTE 5

NOTE 6

NOTES:

1. See the Phase–Locked Loop — Low–Pass Filter Design page for additional information.

2. For optimum performance, bypass the V+ and V+i pins to GND and GNDi with low–inductance capacitors.

3. The R counter is programmed for a divide value = REFin/fR. Typically, fR is the tuning resolution required for the VCO. Also, the VCO frequency divided by fR = NT = N S P + A; this determines the values (N, A) that must be programmed into the N and A counters, respectively. P is the lower divide ratio of the dual–modulus prescaler (i.e., 32 or 64).

5. LD and LD′ are open–drain outputs. This allows the wired–OR configuration shown. Note that R1 and Q1 form the “pull–up device”.

6. Use of Q1 is optional and depends on loading.

Figure 23. Application Showing Use of Both the Single– and Double–Ended Phase/Frequency Detectors

CMOS

MCU

OUTPUT A

(DATA OUT)

ENB

CLKD

DEVICE #1

OUTPUT A

(DATA OUT)

ENB

CLKD

DEVICE #2

OPTIONAL

Figure 24. Cascading Two Devices

NOTE: See related Figures 25, 26, and 27.

Page 23

MC145220MOTOROLA

1 2 7 8 9 10 15161718 23242526 3132

C OR C REGISTER BITS OF DEVICE #2

IN FIGURE 24

*At this point, the new bytes are transferred to the C or C registers of both devices and stored. No other registers are affected.

C6 C0 X X X X X X C7 C6 C0

CLK

ENB

C OR C REGISTER BITS OF DEVICE #1

IN FIGURE 24

Figure 25. Accessing the C or C′ Registers of

Two Cascaded MC145220 Devices

(32 Clock Cycles are Used)

Page 24

MC145220 MOTOROLA 24

Figure 26. Accessing the A or A′ Registers of

Two Cascaded MC145220 Devices

(48 Clock Cycles are Used)

7 8 9 151617 232425 3132

A OR A REGISTER BITS OF DEVICE #1

IN FIGURE 24

A23 A22 A16 A15 A8 A7 A0 A23 A16

38 39 40 47 48

A9 A8 A0

*At this point, the new bytes are transferred to the A or A registers of both devices and stored. Additionally, for both devices, the 13 LSBs in each of the first buffers of the

CLK

ENB

A OR A REGISTER BITS OF DEVICE #2

IN FIGURE 24

R Registers are transferred to the respective R register’s second buffer. Thus, the R, N, and A (R , N , and A ) counters can be presented new divide ratios at the same

time. The first buffer of each R register is not affected. None of the C or C registers are af fected.

Page 25

MC145220MOTOROLA

7 8 9 151617 232425

R REGISTER BITS OF DEVICE #2

IN FIGURE 24

R REGISTER BITS OF DEVICE #1

IN FIGURE 24

R15 R14 R8 R7 R0 X X R15

31 32 33 39 40

R8 R7

NOTE 1

NOTES APPLICABLE TO EACH DEVICE:

1. At this point, bits R13, R14, and R15 are stored and sent to the Buffer and Control block in the Block Diagram. Bits R0 through R12 are loaded into the

2. See note of Figure 26 for the method of loading the second buffers in the R register to achieve new divide ratios.

CLK

ENB

Figure 27. Accessing the R Registers of

Two Cascaded MC145220 Devices

(40 Clock Cycles are Used)

first buffer in the double–buffered section of the R register. Therefore, the R and R counter divide ratios are not altered yet and retain the previous

ratios loaded. The other registers are not affected.

Page 26

MC145220 MOTOROLA 26

P ACKAGE DIMENSIONS

F SUFFIX

SOG (SMALL OUTLINE GULL–WING) PACKAGE

CASE 803C–01

DIMAMIN MAX MIN MAX

INCHES

12.35 12.80 0.486 0.504

MILLIMETERS

B 5.10 5.45 0.201 0.215 C 1.95 2.05 0.077 0.081 D 0.35 0.50 0.014 0.020 E ––– 0.81 ––– 0.032 F 12.40* 0.488* G 1.15 1.39 0.045 0.055 H 0.59 0.81 0.023 0.032 J 0.18 0.27 0.007 0.011 K 1.10 1.50 0.043 0.059 L 0.05 0.20 0.001 0.008 M 0 10 N 0.50 0.85 0.020 0.033 S 7.40 8.20 0.291 0.323

0 10

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.008) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.006) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

*APPROXIMATE

A0.13 (0.005)MTB

0.13 (0.005)MB

S 10 PL

D 20 PL

0.10 (0.004)

SEATING PLANE

–A– –F–

–B–

–T–

DT SUFFIX

TSSOP (THIN SHRUNK SMALL OUTLINE PACKAGE)

CASE 948D–03

-U-

0.200 (0.008)

DIMAMIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B 4.30 4.50 0.169 0.177 C 0.95 1.05 0.037 0.041 D 0.05 0.25 0.002 0.010

F 0.45 0.55 0.018 0.022 G 0.65 BSC 0.026 BSC H 0.275 0.375 0.010 0.015

J 0.09 0.24 0.004 0.009 K 0.16 0.32 0.006 0.013

L 6.30 6.50 0.248 0.256 M 0 10 0 10

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -U-.

°°°°

J1 0.09 0.18 0.004 0.007

K1 0.16 0.26 0.006 0.010

20 X K REF

PIN ONE IDENTIFICATION

SEATING PLANE

-T-

0.100 (0.004)

SECTION A-A

Page 27

MC145220MOTOROLA

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Mfax is a trademark of Motorola, Inc.

How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAP AN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,

P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 4–32–1 Nishi–Gotanda, Shagawa–ku, Tokyo, Japan. 03–5487–8488 Mfax: RMFAX0@email.sps.mot.com – TOUCHT ONE 1–602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

Moto rola Fax B ack System – US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

– http://sps.motorola.com/mfax/

HOME PAGE: http://motorola.com/sps/ CUSTOMER FOCUS CENTER: 1–800–521–6274

MC145220/D

◊

Datasheet MC145220DT, MC145220F Datasheet (Motorola)

Specifications and Main Features

Frequently Asked Questions

User Manual