Datasheet MC145202DT, MC145202F Datasheet (Motorola)

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SEMICONDUCTOR TECHNICAL DATA

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Includes On–Board 64/65 Prescaler

The MC145202 is a low–voltage single–package synthesizer with serial

interface capable of direct usage up to 2.0 GHz.

The counters are programmed via a synchronous serial port which is SPI
compatible. The serial port is byte-oriented to facilitate control via an MCU. Due
to the innovative BitGrabber Plus registers, the MC145202 may be cascaded
with other peripherals featuring BitGrabber Plus without requiring leading
dummy bits or address bits in the serial data stream. In addition, BitGrabber
Plus peripherals may be cascaded with existing BitGrabber peripherals.

The device features a single–ended current source/sink phase detector A
output and a double–ended phase detector B output. Both phase detectors
have linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor tied
from the Rx pin to ground. This current can be varied via the serial port.

Slew–rate control is provided by a special driver designed for the REF
This minimizes interference caused by REF

out

.

This part includes a differential RF input that may be operated in a
single–ended mode. Also featured are on–board support of an external crystal
and a programmable reference output. The R, A, and N counters are fully
programmable. The C register (configuration register) allows the part to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.

In order to have consistent lock times and prevent erroneous data from being
loaded into the counters, on–board circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly , an update of the R register
is synchronized if the R counter is loading.

The double–buffered R register allows new divide ratios to be presented to
the three counters (R, A, and N) simultaneously .

• Maximum Operating Frequency: 2000 MHz @ – 10 dBm

• Operating Supply Current: 4 mA Nominal at 3.0 V

• Operating Supply Voltage Range (VDD and VCC Pins): 2.7 to 5.5 V

• Operating Supply Voltage Range of Phase Detectors (VPD Pin): 2.7 to 5.5 V

• Current Source/Sink Phase Detector Output Capability: 1.7 mA @ 5.0 V

1.0 mA @ 3.0 V

• Gain of Current Source/Sink Phase/Frequency Detector Controllable via

Serial Port

• Operating Temperature Range: – 40 to + 85°C

• R Counter Division Range: 1 and 5 to 8191

• Dual–Modulus Capability Provides Total Division up to 262,143

• High–Speed Serial Interface: 4 Mbps

• OUTPUT A Pin, When Configured as Data Out, Permits Cascading of Devices

• Two General–Purpose Digital Outputs — OUTPUT A: Totem–Pole (Push–Pull)

with Four Output Modes

OUTPUT B: Open–Drain

• Patented Power–Saving Standby Feature with Orderly Recovery for

Minimizing Lock Times, Standby Current: 30 µA

• Evaluation Kit Available (Part Number MC145202EVK)

• See Application Note AN1253/D for Low–Pass Filter Design, and

AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping

BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.

REV 3
1/98 TN98012300

out

pin.

20

1

20

1

SOG PACKAGE

CASE 751J

DT SUFFIX

CASE 948D

ORDERING INFORMATION

MC145202F SOG Package
MC145202DT TSSOP

PIN ASSIGNMENT

REF

out

LD

φ

R

φ

V

V

PD

PD

out

GND

Rx

TEST 1

f

in

1
2
3
4
5
6
7
8
9

20
19
18
17

16
15
14

13
12

1110

F SUFFIX

TSSOP

REF

in

D

in

CLK
ENB
OUTPUT A
OUTPUT B
V

DD

TEST 2
V

CC

f

in

 Motorola, Inc. 1998

MC145202MOTOROLA

1

REF

REF

out

BLOCK DIAGRAM

DATA OUT

20

in

1

OSC OR

4–STAGE

DIVIDER

(CONFIGURABLE)

3

13–STAGE R COUNTER

13

DOUBLE–BUFFERED

BitGrabber



R REGISTER

16 BITS

f

R

PORT

f

V

LOCK DETECTOR

AND CONTROL

SELECT

LOGIC

16

OUTPUT A

2

LD

CLK

D

in

ENB

f

in

f

in

18

19

17

11

10

REGISTER

CONTROL

INTERNAL
CONTROL

INPUT
AMP

SHIFT

AND

LOGIC

8

Rx



BitGrabber

24

STANDBY

LOGIC

BitGrabber

4

6–STAGE

A COUNTER

64/65

PRESCALER

C REGISTER

8 BITS

POR

2



A REGISTER

24 BITS

6 12

12–STAGE

N COUNTER

MODULUS
CONTROL

LOGIC

PHASE/FREQUENCY

DETECTOR A AND CONTROL

PHASE/FREQUENCY

DETECTOR B AND CONTROL

15

13

9

6

PD

out

3

φ

R

4

φ

V

OUTPUT B
(OPEN–
DRAIN
OUTPUT)

TEST 2

TEST 1

SUPPLY CONNECTIONS:

PIN 12 = VCC (V+ TO INPUT AMP AND 64/65 PRESCALER)
PIN 5 = VPD (V+ TO PHASE/FREQUENCY DETECTORS A AND B)
PIN 14 = VDD (V+ TO BALANCE OF CIRCUIT)
PIN 7 = GND (COMMON GROUND)

MC145202 MOTOROLA
2

MAXIMUM RATINGS* (Voltages Referenced to GND, unless otherwise stated)

Symbol Parameter Value Unit

VCC, V

V

PD

V

in

V

out

V

out

Iin, I

I

out

I

DD
P

D

T

stg

T

L

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.

DC Supply Voltage (Pins 12 and 14) – 0.5 to + 6.0 V

DD

DC Supply Voltage (Pin 5) VDD – 0.5 to + 6.0 V
DC Input Voltage – 0.5 to VDD + 0.5 V
DC Output Voltage (except OUTPUT B,

PD

, φR, φV)

out

DC Output Voltage (OUTPUT B, PD

φR, φV)

DC Input Current, per Pin (Includes

PD

VPD)
DC Output Current, per Pin ± 20 mA
DC Supply Current, VDD and GND Pins ± 30 mA
Power Dissipation, per Package 300 mW
Storage Temperature – 65 to + 150 °C
Lead Temperature, 1 mm from Case for

10 Seconds

– 0.5 to VDD + 0.5 V

,

– 0.5 to VPD + 0.5 V

out

± 10 mA

260 °C

This device contains protection circuitry to
guard against damage due to high static volt­ages or electric fields. However, precautions
must be taken to avoid applications of any volt­age higher than maximum rated voltages to this
high–impedance circuit.

ELECTRICAL CHARACTERISTICS

(VDD = VCC = 2.7 to 5.5 V , Voltages Referenced to GND, unless otherwise stated; VPD = 2.7 to 5.5 V, TA = – 40 to 85°C)

Symbol

V

IL

V

IH

V

Hys

V

OL

V

OH

I

OL

I

OL

I

OL

I

OL

I

OH

I

OH

I

OH

Maximum Low–Level Input Voltage

(Din, CLK, ENB

Minimum High–Level Input Voltage

(Din, CLK, ENB

Minimum Hysteresis Voltage (CLK, ENB) VDD = 2.7 V

Maximum Low–Level Output Voltage

(REF

out

Minimum High–Level Output Voltage

(REF

out

Minimum Low–Level Output Current

(REF

out

Minimum Low–Level Output Current

(φR, φV)

Minimum Low–Level Output Current

(OUTPUT A)

Minimum Low–Level Output Current

(OUTPUT B)

Minimum High–Level Output Current

(REF

out

Minimum High–Level Output Current

(φR, φV)

Minimum High–Level Output Current

(OUTPUT A Only)

Parameter Test Condition

)

)

VDD = 4.5 V
I

= 20 µA, Device in Reference Mode 0.1 V

, OUTPUT A)

, OUTPUT A)

, LD)

, LD)

out

I

= – 20 µA, Device in Reference Mode VDD – 0.1 V

out

V

= 0.3 V 0.36 mA

out

V

= 0.3 V 0.36 mA

out

V

= 0.4 V

out

VDD = 4.5 V
V

= 0.4 V 1.0 mA

out

V

= VDD – 0.3 V – 0.36 mA

out

V

= VPD – 0.3 V – 0.36 mA

out

V

= VDD – 0.4 V

out

VDD = 4.5 V

Guaranteed

Limit

0.3 x V

DD

0.7 x V

DD

100
250

1.0 mA

– 0.6 mA

(continued)

Unit

V

V

mV

MC145202MOTOROLA

3

ELECTRICAL CHARACTERISTICS (continued)

Symbol

I

Maximum Input Leakage Current

in

I

in

I

OZ

I

STBY

I

PD

I

T

*The nominal values are:

4 mA at VDD = 3.0 V and VPD = 3.0 V
6 mA at VDD = 5.0 V and VPD = 5.0 V

These are not guaranteed limits.

(Din, CLK, ENB

Maximum Input Current

(REFin)

Maximum Output Leakage Current (PD

Maximum Standby Supply Current

(VDD + VPD Pins)

Maximum Phase Detector

Quiescent Current (VPD Pin)

Total Operating Supply Current

(VDD + VPD + VCC Pins)

Parameter Test Condition

, REFin)

(OUTPUT B) V

Guaranteed

Limit

Vin = VDD or GND, Device in XTAL Mode ± 1.0 µA

Vin = VDD or GND, Device in Reference Mode ± 100 µA

) V

out

= VPD or GND, Output in Floating State ± 130 nA

out

= VPD or GND, Output in High–Impedance State ± 1 µA

out

Vin = VDD or GND; Outputs Open; Device in Standby Mode,
Shut–Down Crystal Mode or REF
Mode; OUTPUT B Controlling VCC per Figure 21

Bit C6 = High Which Selects Phase Detector A,
PD

= Open, PD

out

not

Standby, IRx = 170 µA, VPD = 5.5 V

Bit C6 = Low Which Selects Phase Detector B, φR and

φV = Open, φR and φV = Static Low or High, Bit

C4 = Low Which is
fin = 2.0 GHz; REFin = 13 MHz @ 1 Vp–p;

OUTPUT A = Inactive and No Connect; VDD = VCC,
REF

, φV, φR, PD

out

Din, ENB
(Bit C6 = Low)

, CLK = VDD or GND, Phase Detector B Selected

= Static State, Bit C4 = Low Which is

out

not

Standby

, LD = No Connect;

out

–Static–Low Reference

out

Unit

30 µA

750 µA

30

*

mA

ANALOG CHARACTERISTICS — CURRENT SOURCE/SINK OUTPUT — PD

(I

≤ 1 mA @ VDD = 2.7 V and I

out

Parameter

Maximum Source Current Variation (Part–to–Part) V

Maximum Sink–vs–Source Mismatch (Note 3) V

Output Voltage Range (Note 3) I

NOTES:

1. Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.

2. See Rx Pin Description for external resistor values.

3. This parameter is guaranteed for a given temperature within – 40 to + 85°C.

≤ 1.7mA @ VDD ≥ 4.5 V, VDD = VCC = 2.7 to 5.5 V, Voltages Referenced to GND)

out

Test Condition V

= 0.5 x V

out

= 0.5 x V

out

PD

PD

out

Variation ≤ 15% 2.7 0.5 to 2.2 V

out

I

Variation ≤ 20% 4.5 0.5 to 3.7

out

I

Variation ≤ 22% 5.5 0.5 to 4.7

out

Guaranteed

PD

2.7 ± 15 %

4.5 ± 15

5.5 ± 15

2.7 11 %

4.5 11

5.5 11

Limit

Unit

MC145202 MOTOROLA
4

AC INTERFACE CHARACTERISTICS

(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, CL = 25 pF, Input tr = tf = 10 ns; VPD = 2.7 to 5.5 V)

Symbol

f

t

PLH

t

PLH

t

PZL

t

TLH

C

clk

, t
, t
, t
, t

Serial Data Clock Frequency (Note: Refer to Clock tw below) 1 dc to 4.0 MHz
Maximum Propagation Delay, CLK to OUTPUT A (Selected as Data Out) 1, 5 100 ns

PHL

Maximum Propagation Delay, ENB to OUTPUT A (Selected as Port) 2, 5 150 ns

PHL

Maximum Propagation Delay, ENB to OUTPUT B 2, 6 150 ns

PLZ

Maximum Output Transition Time, OUTPUT A and OUTPUT B; t

THL

Maximum Input Capacitance – Din, ENB, CLK 10 pF

in

Parameter

only, on OUTPUT B 1, 5, 6 50 ns

THL

TIMING REQUIREMENTS

(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, Input tr = tf = 10 ns, unless otherwise indicated)

Symbol

tsu, t

tsu, th, t

t

w

t

w

tr, t

*The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.

Minimum Setup and Hold Times, Din vs CLK 3 50 ns

h

Minimum Setup, Hold and Recovery Times, ENB vs CLK 4 100 ns

rec

Minimum Pulse Width, ENB 4
Minimum Pulse Width, CLK 1 125 ns
Maximum Input Rise and Fall Times, CLK 1 100 µs

f

Parameter

Figure

No.

Figure

No.

Guaranteed

Limit

Guaranteed

Limit

*

Unit

Unit

cycles

MC145202MOTOROLA

5

SWITCHING WAVEFORMS

CLK

OUTPUT A

(DATA OUT)

D

in

CLK

90%

50%

10%

50%

10%

90%

t

f

t

w

t

PLH

t

TLH

1/f

clk

t

r

t

w

t

PHL

t

THL

V

DD

GND

ENB

OUTPUT A

OUTPUT B

50%

Figure 1. Figure 2.

50%

VALID

V

DD

GND

t

su

50%

t

h

V

DD

GND

ENB

CLK

50%

t

su

50%

FIRST

CLK

t

w

10%

t

PLHtPHL

50%

t

PLZ

LAST

CLK

t

PZL

t

h

V

DD

GND

50%

t

w

t

rec

V

DD

GND

V

DD

GND

Figure 3. Figure 4.

TEST POINT

DEVICE

UNDER

TEST

*Includes all probe and fixture capacitance.

*

C

L

Figure 5. Figure 6.

7.5 k

C

+V

Ω

*

L

TEST POINT

DEVICE
UNDER

TEST

*Includes all probe and fixture capacitance.

PD

MC145202 MOTOROLA
6

LOOP SPECIFICATIONS (V

Fig

Symbol Parameter Test Condition

P

Input Sensitivity Range, f

in

f

Input Frequency, REFin Externally Driven in

ref

Reference Mode

f

XTAL

f

t

TLH

t

THL

*Power level at the input to the dc block.

**When PD

Crystal Frequency, Crystal Mode C1 ≤ 30 pF, C2 ≤ 30 pF, Includes Stray

Output Frequency, REF

out

f Operating Frequency of the Phase Detectors dc 2 MHz

t

Output Pulse Width (φR, φV, and LD) fR in Phase with fV, CL = 20 pF, φR and φ

w

,

Output Transition Times (LD, φV, and φR) CL = 20 pF, VPD = 2.7 V,

C

Input Capacitance, REF

in

is active, LD minimum pulse width is approximately 5 ns.

out

= VCC = 2.7 to 5.5 V unless otherwise indicated, TA = – 40 to + 85°C)

DD

in

out

in

500 MHz ≤ fin ≤ 2000 MHz 7 – 10 4 dBm*
Vin ≥ 400 mV p–p 2.7 ≤ VDD < 4.5 V

Capacitance
CL = 20 pF, V

active for LD measurement, **
VPD = 2.7 to 5.5 V VDD = 2.7 V

VDD = VCC = 2.7 V

≥ 1 V p–p 10, 12 dc 10 MHz

out

4.5 ≤ VDD ≤ 5.5 V

VDD = 4.5 V
VDD = 5.5 V

Guaranteed

Operating

.

No.

8 1.5

9 2 15 MHz

11, 12

V

11, 12 — 80 ns

Range

Min Max

1.5

40
18
14

— 7 pF

20
30

120

60
50

Unit

MHz

ns

SINE WAVE

GENERATOR

50

NOTE: Alternately, the 50 Ω pad may be a T network.

50

Ω

PAD

Ω

DC

BLOCK

f

in

f

in

V

CC

OUTPUT A

DEVICE
UNDER

TEST

GND

Figure 7. T est Circuit

TEST

POINT

(fR)

V+

C1

C2

REF

OUTPUT A

in

DEVICE UNDER

TEST

REF

out

V

CC

GND

V

DD

Figure 9. T est Circuit — Crystal Mode

TEST

POINT

(fV)

V

DD

V+

SINE WAVE

GENERATOR

50

0.01

µ

F

REF

OUTPUT A

in

DEVICE

V

CC

UNDER

TEST

REF

GND

out

V

DD

V

in

Ω

(fR)

TEST

POINT

TEST

POINT

V+

Figure 8. T est Circuit — Reference Mode

1/f REF

out

REF

out

50%

Figure 10. Switching Waveform

TEST POINT

OUTPUT

t

w

90%

50%

10%

t

THL

Figure 11. Switching Waveform

t

TLH

DEVICE

UNDER

TEST

CL*

*Includes all probe and

fixture capacitance.

Figure 12. T est Circuit

MC145202MOTOROLA

7

fin (PIN 11)
SOG PACKAGE

4

4

1

3

1

3

2

2

Figure 13. Normalized Input Impedance at fin — Series Format (R + jx)

T able 1. Input Impedence at fin — Series Format (R + jx), VCC = 3 V

Frequency

Marker

1 0.5 11.4 – 168 1.9 pF
2 1 12.4 – 59.4 2.68 pF
3 1.5 19.8 – 34.9 3.04 pF
4 2 18.1 9.43 751 pH

(GHz)

Resistance

(Ω)

Reactance

(Ω)

Capacitance/

Inductance

T able 2. Input Impedence at fin — Series Format (R + jx), VCC = 5 V

Frequency

Marker

1 0.5 11.8 –175 1.82 pF
2 1 11.5 – 64.4 2.47 pF
3 1.5 22.2 – 36.5 2.91 pF
4 2 18.4 1.14 90.4 pH

(GHz)

Resistance

(Ω)

Reactance

(Ω)

Capacitance/

Inductance

3 V
5 V

MC145202 MOTOROLA
8

PIN DESCRIPTIONS

DIGITAL INTERFACE PINS
D

in

Serial Data Input (Pin 19)

The bit stream begins with the most significant bit (MSB)
and is shifted in on the low–to–high transition of CLK. The bit
pattern is 1 byte (8 bits) long to access the C or configuration
register, 2 bytes (16 bits) to access the first buffer of the R
register, or 3 bytes (24 bits) to access the A register (see
Table 3). The values in the C, R, and A registers do not
change during shifting because the transfer of data to the
registers is controlled by ENB

The value programmed for the N counter must be
greater than or equal to the value of the A counter.

The 13 least significant bits (LSBs) of the R register are
double–buffered. As indicated above, data is latched into the
first buffer on a 16–bit transfer . (The 3 MSBs are not double–
buffered and have an immediate effect after a 16–bit
transfer.) The second buf fer of the R register contains the 13
bits for the R counter. This second buffer is loaded with the
contents of the first buffer when the A register is loaded (a
24–bit transfer). This allows presenting new values to the R,
A, and N counters simultaneously . If this is not required, then
the 16–bit transfer may be followed by pulsing ENB
no signal on the CLK pin. This is an alternate method of tran­sferring data to the second buffer of the R register (see Fig­ure 16).

The bit stream needs neither address nor steering bits due
to the innovative BitGrabber Plus registers. Therefore, all bits
in the stream are available to be data for the three registers.
Random access of any register is provided (i.e., the registers
may be accessed in any sequence). Data is retained in the
registers over a supply range of 2.7 to 5.5 V . The formats are
shown in Figures 14, 15, and 16.

Din typically switches near 50% of VDD to maximize noise
immunity. This input can be directly interfaced to CMOS de­vices with outputs guaranteed to switch near rail–to–rail.
When interfacing to NMOS or TTL devices, either a level
shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 kΩ
to 10 kΩ must be used. Parameters to consider when sizing
the resistor are worst–case IOL of the driving device, maxi­mum tolerable power consumption, and maximum data rate.

T able 3. Register Access

(MSBs are shifted in first; C0, R0, and A0 are the LSBs)

Number

of Clocks

8
16
24

Other Values ≤ 32

Values > 32

.

CAUTION

Accessed

Register

C Register
R Register

A Register
Not Allowed
See Figures

22 – 25

low with

Bit

Nomenclature

C7, C6, C5, . . ., C0

R15, R14, R13, . . ., R0

A23, A22, A21, . . ., A0

CLK
Serial Data Clock Input (Pin 18)

Low–to–high transitions on CLK shift bits available at the
Din pin, while high–to–low transitions shift bits from OUT­PUT A (when configured as Data Out, see Pin 16). The
24–1/2–stage shift register is static, allowing clock rates
down to dc in a continuous or intermittent mode.

Eight clock cycles are required to access the C register.
Sixteen clock cycles are needed for the first buffer of the R
register. Twenty–four cycles are used to access the A regis­ter. See Table 3 and Figures 14, 15, and 16. The number of
clocks required for cascaded devices is shown in Figures 23
through 25.

CLK typically switches near 50% of VDD an d has a
Schmitt–triggered input buffer. Slow CLK rise and fall times
are allowed. See the last paragraph of Din for more informa­tion.

NOTE

To guarantee proper operation of the power–on
reset (POR) circuit, the CLK pin must be held at
GND (with ENB

being a don’t care) or ENB must
be held at the potential of the V+ pin (with CLK be­ing a don’t care) during power–up. Floating, tog­gling, or having these pins in the wrong state
during power–up does not harm the chip, but
causes two potentially undesirable effects. First,
the outputs of the device power up in an unknown
state. Second, if two devices are cascaded, the A
Registers must be written twice after power up.
After these two accesses, the two cascaded chips
perform normally.

ENB
Active Low Enable Input (Pin 17)

This pin is used to activate the serial interface to allow the
transfer of data to/from the device. When ENB is in an inac­tive high state, shifting is inhibited and the port is held in the
initialized state. To transfer data to the device, ENB (which
must start inactive high) is taken low, a serial transfer is
made via Din and CLK, and ENB
low–to–high transition on ENB

is taken back high. The

transfers data to the C or A
registers and first buffer of the R register, depending on the
data stream length per Table 3.

Transitions on ENB

must not be attempted while CLK is
high. This puts the device out of synchronization with the
microcontroller. Resynchronization occurs when ENB

is high

and CLK is low.

This input is also Schmitt–triggered and switches near
50% of VDD, thereby minimizing the chance of loading erro­neous data into the registers. See the last paragraph of D

in

for more information.

For POR information, see the note for the CLK pin.

MC145202MOTOROLA

9

OUTPUT A
Configurable Digital Output (Pin 16)

OUTPUT A is selectable as fR, fV, Data Out, or Port. Bits
A22 and A23 in the A register control the selection; see
Figure 15.

If A23 = A22 = high, OUTPUT A is configured as fR. This
signal is the buffered output of the 13–stage R counter. The
fR signal appears as normally low and pulses high. The f
signal can be used to verify the divide ratio of the R counter.
This ratio extends from 5 to 8191 and is determined by the
binary value loaded into bits R0–R12 in the R register. Also,
direct access to the phase detectors via the REFin pin is al­lowed by choosing a divide value of 1 (see Figure 16). The
maximum frequency at which the phase detectors operate is
2 MHz. Therefore, the frequency of fR should not exceed
2 MHz.

If A23 = high and A22 = low, OUTPUT A is configured as
fV. This signal is the buffered output of the 12–stage N
counter. The fV signal appears as normally low and pulses
high. The fV signal can be used to verify the operation of the
prescaler, A counter , and N counter . The divide ratio between
the fin input and the fV signal is N × 64 + A. N is the divide
ratio of the N counter and A is the divide ratio of the A
counter. These ratios are determined by bits loaded into the
A register. See Figure 15. The maximum frequency at which
the phase detectors operate is 2 MHz. Therefore, the fre­quency of fV should not exceed 2 MHz.

If A23 = low and A22 = high, OUTPUT A is configured as
Data Out. This signal is the serial output of the 24–1/2–stage
shift register. The bit stream is shifted out on the high–to–low
transition of the CLK input. Upon power up, OUTPUT A is
automatically configured as Data Out to facilitate cascading
devices.

If A23 = A22 = low, OUTPUT A is configured as Port. This
signal is a general–purpose digital output which may be used
as an MCU port expander. This signal is low when the Port
bit (C1) of the C register is low, and high when the Port bit is
high.

OUTPUT B
Open–Drain Digital Output (Pin 15)

This signal is a general–purpose digital output which may
be used as an MCU port expander. This signal is low when
the Out B bit (C0) of the C register is low. When the Out B bit
is high, OUTPUT B assumes the high–impedance state.
OUTPUT B may be pulled up through an external resistor or
active circuitry to any voltage less than or equal to the poten­tial of the VPD pin. Note: the maximum voltage allowed on
the VPD pin is 5.5 V.

Upon power–up, power–on reset circuitry forces OUTPUT
B to a low level.

REFERENCE PINS
REFin and REF

Reference Input and Reference Output (Pins 20 and 1)

Configurable pins for a Crystal or an External Reference.
This pair of pins can be configured in one of two modes: the
crystal mode or the reference mode. Bits R13, R14, and R15
in the R register control the modes as shown in Figure 16.

In crystal mode, these pins form a reference oscillator
when connected to terminals of an external parallel–reso-

out

nant crystal. Frequency–setting capacitors of appropriate
values, as recommended by the crystal supplier, are con­nected from each of the two pins to ground (up to a maximum
of 30 pF each, including stray capacitance). An external re­sistor of 1 MΩ to 15 MΩ is connected directly across the pins
to ensure linear operation of the amplifier. The required con­nections for the components are shown in Figure 9.

R

T o turn on the oscillator, bits R15, R14, and R13 must have
an octal value of one (001 in binary , respectively). This is the
active–crystal mode shown in Figure 16. In this mode, the
crystal oscillator runs and the R Counter divides the crystal
frequency , unless the part is in standby . If the part is placed in
standby via the C register, the oscillator runs, but the R
counter is stopped. However, if bits R15 to R13 have a value
of 0, the oscillator is stopped, which saves additional power.
This is the shut–down crystal mode (shown in Figure 16) and
can be engaged whether in standby or not.

In the reference mode, REFin (Pin 20) accepts a signal
from an external reference oscillator , such as a TCXO. A sig­nal swinging from at least the VIL to VIH levels listed in the
Electrical Characteristics table may be directly coupled to the
pin. If the signal is less than this level, ac coupling must be
used as shown in Figure 8. Due to an on–board resistor
which is engaged in the reference modes, an external bias­ing resistor tied between REFin and REF

With the reference mode, the REF
the output of a divider. As an example, if bits R15, R14, and
R13 have an octal value of seven, the frequency at REF
the REFin frequency divided by 16. In addition, Figure 16
shows how to obtain ratios of eight, four, and two. A ratio of
one–to–one can be obtained with an octal value of three.
Upon power up, a ratio of eight is automatically initialized.
The maximum frequency capability of the REF
in the Loop Specifications table for an output swing of
1 V p–p and 20 pF loads. Therefore, for higher REFin fre­quencies, the one–to–one ratio may not be used for this
magnitude of signal swing and loading requirements. Like­wise, for REFin frequencies above two times the highest
rated frequency , the ratio must be more than two.

The output has a special on–board driver that has slew–
rate control. This feature minimizes interference in the ap­plication.

If REF
for R15, R14, and R13 and the REF
A value of two allows REFin to be functional while disabling
REF

LOOP PINS

fin and f
Frequency Inputs (Pins 11 and 10)

These pins are frequency inputs from the VCO. These pins
feed the on–board RF amplifier which drives the 64/65 pre­scaler. These inputs may be fed differentially. However, they
are usually used in a single–ended configuration (shown in
Figure 7). Note that fin is driven while f
ground via a capacitor.

Motorola does not recommend driving f
fin because this configuration is not tested for sensitivity. The
sensitivity is dependent on the frequency as shown in the
Loop Specifications table.

is unused, an octal value of two should be used

out

, which minimizes dynamic power consumption.

out

in

out

pin is configured as

out

pin should be floated.

out

must be tied to

in

while terminating

in

is not required.

out

pin is listed

out

is

MC145202 MOTOROLA
10

PD

out

Single–Ended Phase/Frequency Detector Output (Pin 6)

This is a three–state current–source/sink output for use as
a loop error signal when combined with an external low–pass
filter. The phase/frequency detector is characterized by a lin­ear transfer function. The operation of the phase/frequency
detector is described below and is shown in Figure 17.

POL bit (C7) in the C register = low (see Figure 14)

Frequency of fV > fR or Phase of fV Leading fR: current–

sinking pulses from a floating state

Frequency of fV < fR or Phase of fV Lagging fR: current–

sourcing pulses from a floating state

Frequency and Phase of fV = fR: essentially a floating

state; voltage at pin determined by loop filter
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR: current–

sourcing pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR: current–

sinking pulses from a floating state
Frequency and Phase of fV = fR: essentially a floating

state; voltage at pin determined by loop filter
This output can be enabled, disabled, and inverted via the

C register. If desired, PD

can be forced to the high–imped-

out

ance state by utilization of the disable feature in the C regis­ter (bit C6). This is a patented feature. Similarly, PD

out

is
forced to the high–impedance state when the device is put
into standby (STBY bit C4 = high).

The PD

circuit is powered by VPD. The phase detector

out

gain is controllable by bits C3, C2, and C1: gain (in amps per
radian) = PD

current divided by 2π.

out

φR and φV (Pins 3 and 4)
Double–Ended Phase/Frequency Detector Outputs

These outputs can be combined externally to generate a
loop error signal. Through use of a Motorola patented tech­nique, the detector’s dead zone has been eliminated. There­fore, the phase/frequency detector is characterized by a
linear transfer function. The operation of the phase/frequen­cy detector is described below and is shown in Figure 17.

POL bit (C7) in the C register = low (see Figure 14)

Frequency of fV > fR or Phase of fV Leading fR: φV = nega-

tive pulses, φR = essentially high

Frequency of fV < fR or Phase of fV Lagging fR: φV = essen-

tially high, φR = negative pulses

Frequency and Phase of fV = fR: φV and φR remain essen-

tially high, except for a small minimum time period when

both pulse low in phase
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR: φR = nega-

tive pulses, φV = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φR = essen-

tially high, φV = negative pulses
Frequency and Phase of fV = fR: φV and φR remain essen-

tially high, except for a small minimum time period when

both pulse low in phase
These outputs can be enabled, disabled, and inter-

changed via C register bits C6 or C4. This is a patented fea-

ture. Note that when disabled or in standby, φR and φV are
forced to their rest condition (high state).

The φR and φV output signal swing is approximately from

GND to VPD.

LD
Lock Detector Output (Pin 2)

This output is essentially at a high level with narrow low–
going pulses when the loop is locked (fR and fV of the same
phase and frequency). The output pulses low when fV and f
are out of phase or different frequencies. LD is the logical
ANDing of φR and φV (see Figure 17).

This output can be enabled and disabled via the C register.
This is a patented feature. Upon power up, on–chip initializa­tion circuitry disables LD to a static low logic level to prevent
a false “lock” signal. If unused, LD should be disabled and
left open.

The LD output signal swing is approximately from GND to
VDD.

Rx
External Resistor (Pin 8)

A resistor tied between this pin and GND, in conjunction
with bits in the C register, determines the amount of current
that the PD
are both set high, the maximum current is obtained at PD

pin sinks and sources. When bits C2 and C3

out

out

see Tables 4 and 5 for other current values. The recom­mended value for Rx is 3.9 kΩ . A value of 3.9 kΩ provides
current at the PD

pin of approximately 1 mA @ VDD = 3 V

out

and approximately 1.7 mA @ VDD = 5 V in the 100% current
mode. Note that VDD, not VPD, is a factor in determining the
current.

When the φR and φV outputs are used, the Rx pin may be
floated.

T able 4. PD

OUTPUT A

Current*, C1 = Low with

out

not

Selected as “Port”;

Also, Default Mode When OUTPUT A

Selected as “Port”

Bit C3 Bit C2 PD

0
0
1
1

*At the time the data sheet was printed, only the 100%

current mode was guaranteed. The reduced current
modes were for experimentation only.

T able 5. PD

OUTPUT A

Bit C3 Bit C2 PD

0
0
1
1

*At the time the data sheet was printed, only the 100%

current mode was guaranteed. The reduced current
modes were for experimentation only.

0
1
0
1

Current*, C1 = High with

out

not

Selected as “Port”

0
1
0
1

Current*

out

70%
80%
90%

100%

Current*

out

25%
50%
75%

100%

R

;

MC145202MOTOROLA

11

TEST POINT PINS
TEST 1

Modulus Control Signal (Pin 9)

This pin may be used in conjunction with the Test 2 pin for
access to the on–board 64/65 prescaler. When Test 1 is low,
the prescaler divides by 65. When high, the prescaler divides
by 64.

CAUTION

This pin is an unbuffered output and must be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.

TEST 2
Prescaler Output (Pin 13)

This pin may be used to access the on–board 64/65 pres­caler output.

CAUTION

This pin is an unbuffered output and must be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.

POWER SUPPLY PINS
V

DD

Positive Power Supply (Pin 14)

This pin supplies power to the main CMOS digital portion
of the device. Also, this pin, in conjunction with the Rx resis­tor, determines the internal reference current for the PD
pin. The voltage range is +

2.7 to + 5.5 V with respect to the

out

GND pin.

For optimum performance, VDD should be bypassed to
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.

V

CC

Positive Power Supply (Pin 12)

This pin supplies power to the RF amp and 64/65 pres­caler. The voltage range is +

2.7 to + 5.5 V with respect to the

GND pin. In standby mode, the VCC pin still draws a few mil­liamps from the power supply . This current drain can be elim­inated with the use of transistor Q1 as shown in Figure 21.

For optimum performance, VCC should be bypassed to
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.

V

PD

Positive Power Supply (Pin 5)

This pin supplies power to both phase/frequency detectors
A and B. The voltage applied on this pin may be more or less
than the potential applied to the VDD and VCC pins. The volt­age range for VPD is 2.7 to 5.5 V with respect to the GND pin.

For optimum performance, VPD should be bypassed to
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.

GND
Ground (Pin 7)

Common ground.

MC145202 MOTOROLA
12

ENB

CLK

D

in

*At this point, the new byte is transferred to the C register and stored. No other registers

are affected.

C7 – POL: Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts PD

C6 – PDA/B: Selects which phase/frequency detector is to be used. When set high, enables the output of phase/fre-

C5 – LDE: Enables the lock detector output when set high. When the bit is cleared low, the LD output is forced

C4 – STBY: When set, places the CMOS section of device, which is powered by the VDD and VPD pins, in the

C3, C2 – I2, I1: Controls the PD

C1 – Port: When the OUTPUT A pin is selected as “Port” via bits A22 and A23, C1 determines the state of

C0 – Out B: Determines the state of OUTPUT B. When C0 is set high, OUTPUT B is high–impedance; C0 low

and interchanges the φR function with φV as depicted in Figure 17. Also see the phase detector output
pin descriptions for more information. This bit is cleared low at power up.

quency detector A (PD
high state. When cleared low, phase/frequency detector B is enabled (φR and φV) and phase/frequency
detector A is disabled with PD
up.

to a static low level. This bit is cleared low at power up.

standby mode for reduced power consumption: PD

φV are forced high, the A, N, and R counters are inhibited from counting, and the Rx current is shut

off. In standby, the state of LD is determined by bit C5. C5 low forces LD low (no change). C5 high
forces LD static high. During standby, data is retained in the A, R, and C registers. The condition
of REF/OSC circuitry is determined by the control bits in the R register: R13, R14, and R15. However,
if REF

out

when in standby; in addition, the REFin input only presents a capacitive load. NOTE: Standby does
not affect the other modes of the REF/OSC circuitry.

When C4 is reset low, the part is taken out of standby in two steps. First, the REFin (only in one
mode) resistor is reconnected, all counters are enabled, and the Rx current is enabled. Any fR and
fV signals are inhibited from toggling the phase/frequency detectors and lock detector. Second, when
the first fV pulse occurs, the R counter is jam loaded, and the phase/frequency and lock detectors
are initialized. Immediately after the jam load, the A, N, and R counters begin counting down together.
At this point, the fR and fV pulses are enabled to the phase and lock detectors. (Patented feature.)

is available. Also, see C1 bit description.

OUTPUT A. When C1 is set high, OUTPUT A is forced high; C1 low forces OUTPUT A low. When
OUTPUT A is
Tables 4 and 5.) When low, steps are 10%. When high, steps are 25%. Default is 10% steps when
OUTPUT A is selected as “Port.” The Port bit is not affected by the standby mode.

forces OUTPUT B low. The Out B bit is not affected by the standby mode. This bit is cleared low
at power up.

12345678

MSB LSB

C7 C6 C5 C4 C3 C2 C1 C0

) and disables phase/frequency detector B by forcing φR and φV to the static

out

forced to the high–impedance state. This bit is cleared low at power

out

is forced to the high–impedance state, φR and

out

= static low is selected, the internal feedback resistor is disconnected and the input is inhibited

source/sink current per Tables 4 and 5. With both bits high, the maximum current

out

not

selected as “Port,” C1 controls whether the PD

step size is 10% or 25%. (See

out

*

out

Figure 14. C Register Access and Format (8 Clock Cycles are Used)

MC145202MOTOROLA

13

NOTE 3

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

÷÷÷

A COUNTER = 0
012

000

÷

A COUNTER = 1

A COUNTER = 2

A COUNTER = 3

...

3

...

0

÷÷÷

NOT ALLOWED

NOT ALLOWED

NOT ALLOWED

NOT ALLOWED

NOT ALLOWED

N COUNTER = 5

0123456

÷

A COUNTER = 62
E

3

N COUNTER = 6

÷

A COUNTER = 63

NOT ALLOWED

F

0

3

4

N COUNTER = 7

...

7

...

...

4 1 NOT ALLOWED

÷

÷

N COUNTER = 4094

N COUNTER = 4095

E

F

F NOT ALLOWED

F

HEXADECIMAL VALUE

FOR A COUNTER

ENB

234567891011121314151617181920212223241

CLK

MSB LSB

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

in

D

0000000

0000000

11

HIGH

MUST BE

BOTH BITS

PORT

010
001

DATA OUTff

...

F

0

...

0

V

R

1

1

F

F

F

(NOTE 1)

OUTPUT A

FUNCTION

VALUE

BINARY

FOR N COUNTER

HEXADECIMAL VALUE

NOTES:

Thus, the R, N, and A counters can be presented new divide ratios at the same time. The first buffer of the R register is not affected. The C register is not affected.

1. A power-on initialize circuit forces the OUTPUT A function to default to Data Out.

2. The values programmed for the N counter must be greater than or equal to the values programmed for the A counter. This results in a total divide value= N x 64 + A.

3. At this point, the three new bytes are transferred to the A register. In addition, the 13 LSBs in the first buf fer of the R register are transferred to the R register’s second buf fer.

Figure 15. A Register Access and Format (24 Clock Cycles are Used)

MC145202 MOTOROLA
14

ENB

CLK

D

in

0
1
2

3
4
5
6
7

NOTES:

1. Bits R15 through R13 control the configurable “OSC or 4–stage divider” block (see Block Diagram).

2. Bits R12 through R0 control the “13–stage R counter” block (see Block Diagram).

3. A power–on initialize circuit forces a default REFin to REF

4. At this point, bits R13, R14, and R15 are stored and sent to the “OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 – R12
are loaded into the first buffer in the double–buffered section of the R register. Therefore, the R counter divide ratio is not altered yet
and retains the previous ratio loaded. The C and A registers are not affected.

5. Optional load pulse. At this point, bits R0 – R12 are transferred to the second buffer of the R register. The R counter begins dividing
by the new ratio after completing the rest of the present count cycle. CLK must be low during the ENB
registers are not affected. The first buffer of the R register is not affected. Also, see note 3 of Figure 15 for an alternate method of loading
the second buffer in the R register .

6. Allows direct access to reference input of phase/frequency detectors.

12345678

MSB LSB

R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R11R12R13R14R15

CRYSTAL MODE, SHUT DOWN
CRYSTAL MODE, ACTIVE
REFERENCE MODE, REFin ENABLED and REF

STATIC LOW
REFERENCE MODE, REF
REFERENCE MODE, REF
REFERENCE MODE, REF
REFERENCE MODE, REF
REFERENCE MODE, REF

OCTAL VALUE

= REFin (BUFFERED)

out

= REFin/2

out

= REFin/4

out

= REFin/8 (NOTE 3)

out

= REFin/16

out

BINARY VALUE

out

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

·

·

·

·

·

·

1

F

1

F

HEXADECIMAL VALUE

out

9 10111213141516

0

0
0
0
0
0
0
0
0
0

·

·

·
F
F

NOT ALLOWED

1

R COUNTER =
NOT ALLOWED

2

NOT ALLOWED

3

NOT ALLOWED

4

R COUNTER = ÷5

5

R COUNTER =

6

R COUNTER =

7

R COUNTER = ÷8

8

·

·

·
R COUNTER = ÷8190

E

R COUNTER =

F

ratio of eight.

÷

1 (NOTE 6)

÷

6

÷

7

÷

8191

pulse, as shown. The C and A

NOTE4NOTE

5

Figure 16. R Register Access and Format (16 Clock Cycles are Used)

MC145202MOTOROLA

15

REFERENCE

REFin

FEEDBACK

÷

(N x 64 + A)

fin

f

R

÷

R

f

V

V

H

V

L

V

H

V

L

*

PD

out

φ

R

φ

V

LD

VH = High voltage level
VL = Low voltage level
*At this point, when both fR and fV are in phase, the output source and sink circuits are turned on for a short interval.

NOTE: The PD

the floating condition and the voltage at that pin is determined by the low–pass filter capacitor. PD
the polarity bit (POL) = low; see Figure 14 for POL.

either sources or sinks current during out–of–lock conditions. When locked in phase and frequency, the output is in

out

, φR, and φV are shown with

out

Figure 17. Phase/Frequency Detectors and Lock Detector Output Waveforms

SOURCING CURRENT
FLOAT

SINKING CURRENT

V
V

V
V

V
V

H
L

H
L

H
L

MC145202 MOTOROLA
16

DESIGN CONSIDERATIONS

CRYSTAL OSCILLATOR CONSIDERATIONS

The following options may be considered to provide a ref­erence frequency to Motorola’s CMOS frequency synthe­sizers.

Use of a Hybrid Crystal Oscillator

Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscilla­tors provide very stable reference frequencies. An oscillator
capable of CMOS logic levels at the output may be direct or
dc coupled to REFin. If the oscillator does not have CMOS
logic levels on the outputs, capacitive or ac coupling to REF
may be used (see Figure 8).

For additional information about TCXOs and data clock
oscillators, please consult the latest version of the

the

tronic Engineers Master Catalog,

Gold Book,

publications.

Design an Off–Chip Reference

The user may design an off–chip crystal oscillator using
discrete transistors or ICs specifically developed for crystal
oscillator applications, such as the MC12061 MECL device.
The reference signal from the MECL device is ac coupled to
REFin (see Figure 8). For large amplitude signals (standard
CMOS logic levels), dc coupling may be used.

eem Elec-

or similar

by the crystal manufacturer represents the maximum stress
that the crystal can withstand without damage or excessive
shift in operating frequency. R1 in Figure 18 limits the drive
level. The use of R1 is not necessary in most cases.

To verify that the maximum dc supply voltage does not
cause the crystal to be overdriven, monitor the output
frequency (fR) at OUTPUT A as a function of supply voltage.
(REF

is not used because loading impacts the oscillator.)

out

The frequency should increase very slightly as the dc supply
voltage is increased. An overdriven crystal decreases in fre­quency or becomes unstable with an increase in supply volt­age. The operating supply voltage must be reduced or R1
must be increased in value if the overdriven condition exists.

in

The user should note that the oscillator start–up time is pro­portional to the value of R1.

Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have devel­oped expertise in CMOS oscillator design with crystals. Dis­cussions with such manufacturers can prove very helpful
(see Table 6).

FREQUENCY SYNTHESIZER

R1*

REF

out

REF

in

R

f

Use of the On–Chip Oscillator Circuitry

The on–chip amplifier (a digital inverter) along with an ap­propriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 18.

The crystal should be specified for a loading capacitance
(CL) which does not exceed approximately 20 pF when used
at the highest operating frequencies listed in the Loop Speci­fications table. Assuming R1 = 0 Ω, the shunt load capaci­tance (CL) presented across the crystal can be estimated to
be:

CL =

CinC

Cin + C

out

out

+ Ca + C

stray

C1 • C2

+

C1 + C2

where

Cin = 5 pF (see Figure 19)

C

= 6 pF (see Figure 19)

out

Ca = 1 pF (see Figure 19)

C1 and C2 = external capacitors (see Figure 18)

C

= the total equivalent external circuit stray

stray

capacitance appearing across the crystal
terminals

The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated com­ponents must be located as close as possible to the REF
and REF

pins to minimize distortion, stray capacitance,

out

stray inductance, and startup stabilization time. Circuit stray
capacitance can also be handled by adding the appropriate
stray value to the values for Cin and C
the term C

becomes 0 in the above expression for CL.

stray

. For this approach,

out

Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 20. The maximum drive level specified

C2C1

*May be needed in certain cases. See text.

Figure 18. Pierce Crystal Oscillator Circuit

C

C

stray

a

C

out

REF

out

REF

in

C

in

Figure 19. Parasitic Capacitances of the

Amplifier and C

121

in

1

NOTE: Values are supplied by crystal manufacturer

(parallel resonant crystal).

R

R

S

e

stray

X

C

L

C

e

S

S

2

O

2

Figure 20. Equivalent Crystal Networks

MC145202MOTOROLA

17

RECOMMENDED READING

Technical Note TN–24, Statek Corp.

Technical Note TN–7, Statek Corp.

E. Hafner, “The Piezoelectric Crystal Unit–Definitions and
Method of Measurement”,

Proc. IEEE,

Vol. 57, No. 2, Feb.

1969.

D. Kemper, L. Rosine, “Quartz Crystals for Frequency

T able 6. Partial List of Crystal Manufacturers

Control”,

Electro–Technology

P. J. Ottowitz, “A Guide to Crystal Selection”,

Design

, May 1966.

D. Babin, “Designing Crystal Oscillators”,

, June 1969.

Electronic

Machine Design

March 7, 1985.

D. Babin, “Guidelines for Crystal Oscillator Design”,

Machine Design

, April 25, 1985.

,

Motorola — Internet Address

NOTE: Motorola cannot recommend one supplier over another and in no way suggests

that this is a complete listing of crystal manufacturers.

http://motorola.com

United States Crystal Corp.

Crystek Crystal

Statek Corp.

Fox Electronics

(Search for resonators)

MC145202 MOTOROLA
18

PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN

K

(A)

NOTE:

For (A), using Kφ in amps per radian with the filter’s impedance transfer function, Z(s), maintains units of volts per radian for the detector/filter
combination. Additional sideband filtering can be accomplished by adding a capacitor C′ across R. The corner ωc = 1/RC′ should be chosen
such that ωn is not significantly affected.

(B)

NOTE:

For (B), R1 is frequently split into two series resistors; each resistor is equal to R1 divided by 2. A capacitor CC is then placed from the midpoint
to ground to further filter the error pulses. The value of CC should be such that the corner frequency of this network does not significantly
affect ωn.

DEFINITIONS:

N = T otal Division Ratio in Feedback Loop
Kφ (Phase Detector Gain) = I
Kφ (Phase Detector Gain) = VPD/2π volts per radian for φV and φ

K

VCO

For a nominal design starting point, the user might consider a damping factor ζ ≈ 0.7 and a natural loop frequency ωn ≈ (2πfR/50) where f
is the frequency at the phase detector input. Larger ωn values result in faster loop lock times and, for similar sideband filtering, higher fR–related
VCO sidebands.

Either loop filter (A) or (B) is frequently followed by additional sideband filtering to further attenuate fR–related VCO sidebands. This additional
filtering may be active or passive.

RECOMMENDED READING:

Gardner, Floyd M.,
Manassewitsch, Vadim,
Blanchard, Alain,
Egan, William F.,
Rohde, Ulrich L.,
Berlin, Howard M.,
Kinley, Harold,
Seidman, Arthur H.,
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,”
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from

1987.

AN1253, An Improved PLL Design Method Without ωn and ζ, Motorola Semiconductor Products, Inc., 1995.

PD

out

R

C

R

φ

R

φ

V

(VCO Transfer Function) =

1

R

1

Phaselock Techniques (second edition).

VCO

R

2

–
+

R

2

C

/2π amps per radian for PD

PDout

2π∆f

∆V

C

A

VCO

VCO

VCO

out

radians per volt

New York, Wiley–Interscience, 1979.

Frequency Synthesizers: Theory and Design (second edition).

Phase–Locked Loops: Application to Coherent Receiver Design.

Frequency Synthesis by Phase Lock.

New York, Wiley–Interscience, 1981.

Digital PLL Frequency Synthesizers Theory and Design.

Design of Phase–Locked Loop Circuits, with Experiments.

The PLL Synthesizer Cookbook.

Integrated Circuits Applications Handbook

Blue Ridge Summit, PA, Tab Books, 1980.

, Chapter 17, pp. 538–586. New Y ork, John Wiley & Sons.

ωn =

ζ

=

Z(s) =

ωn =

ζ

=

ASSUMING GAIN A IS VERY LARGE, THEN:

F(s) =

R

New York, Wiley–Interscience, 1980.

New York, Wiley–Interscience, 1976.

Englewood Cliffs, NJ, Prentice–Hall, 1983.

Indianapolis, Howard W. Sams and Co., 1978.

EDN

. March 5, 1980.

φKVCO

R
2

1 + sRC

sC

K

φKVCO

NCR

ω

C

nR2

2

R2sC + 1

R1sC

NC

K

C

K

VCO

φ

N

1

Electronic Design,

ωnRC

=

2

R

MC145202MOTOROLA

19

THRESHOLD

DETECTOR

1

REF

out

2

INTEGRATOR

+ 3 V

LOW–PASS

FILTER

1000 pF

NOTES:

1. When used, the φR and φV outputs are fed to an external combiner/loop filter. See the Phase–
Locked Loop — Low–Pass Filter Design page for additional information.

2. Transistor Q1 is required only if the standby feature is needed. Q1 permits the bipolar section
of the device to be shut down via use of the general–purpose digital pin, OUTPUT B. If the stand­by feature is not needed, tie Pin 12 directly to the power supply.

3. For optimum performance, bypass the VCC, VDD, and VPD pins to GND with low–inductance ca­pacitors.

4. The R counter is programmed for a divide value = REFin/fR. Typically , fR is the tuning resolution
required for the VCO. Also, the VCO frequency divided by fR = NT = N x 64 + A; this determines
the values (N, A) that must be programmed into the N and A counters, respectively.

LD

3

φ

R

4

φ

V

5

V

6

PD

7

GND

8

Rx

9

TEST 1

NC

10 11

f

UHF
VCO

PD

in

out

OUTPUT A
OUTPUT B

TEST 2

REF

CLK

ENB

V

V

D

DD

CC

f

20

in

19

in

18

17
16
15

14

13

12

in

GENERAL–PURPOSE
DIGITAL OUTPUT

+3 V

NC

Q1

BUFFER

NOTE 2

UHF OUTPUT

+3 V

MCU

Figure 21. Example Application

DEVICE #1

CLKD

in

CMOS

MCU

NOTE: See related Figures 23, 24, and 25.

Figure 22. Cascading T wo Devices

ENB

OUTPUT A

(DATA OUT)

OPTIONAL

DEVICE #2

OUTPUT A

(DATA OUT)

CLKD

in

ENB

MC145202 MOTOROLA
20

*

*

A9 A8 A0

38 39 40 47 48

IN FIGURE 22

IN FIGURE 22

C REGISTER BITS OF DEVICE #1

7 8 9 151617 232425 3132

A16

A REGISTER BITS OF DEVICE #1

IN FIGURE 22

A REGISTER BITS OF DEVICE #2

IN FIGURE 22

ENB

1 2 7 8 910 15161718 23242526 3132

CLK

C7 C6 C0 X X X X X X C7 C6 C0

D

C REGISTER BITS OF DEVICE #2

in

*At this point, the new bytes are transferred to the C registers of both devices and stored. No other registers are affected.

Figure 23. Accessing the C Registers of T wo

Cascaded MC145202 Devices

12

A23 A22 A16 A15 A8 A7 A0 A23

ENB

CLK

in

D

13 LSBs in each of the first buffers of the R registers are transferred to the respective R register’s second buffer. Thus, the

* At this point, the new bytes are transferred to the A registers of both devices and stored. Additionally , for both devices, the

Figure 24. Accessing the A Registers of T wo

Cascaded MC145202 Devices

MC145202MOTOROLA

R, N, and A counter can be presented new divide ratios at the same time. The first buffer of each R register is not affected.

Neither C register is affected.

21

Note 1 Note 2

31 32 33 39 40

7 8 9 151617 232425

R8 R7 R0

IN FIGURE 22

R REGISTER BITS OF DEVICE #1

IN FIGURE 22

R REGISTER BITS OF DEVICE #2

12

R15 R14 R8 R7 R0 X X R15

1. At this point, bits R13, R14 and R15 are stored and sent to the ‘‘OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 through

R12 are loaded into the first buffer in the double–buffered section of the R register. Therfore, the R counter divide is not altered yet and

retains the previous ratio loaded. The C and A registers are not affected.

2. Optional load pulse. At this point, the bits R0 through R12 are transfered to the second buffer of the R register. The R counter begins dividing

are not affected. The first buffer of the R register is not affected. Also, see note of Figure 24 for an alternate method of loading the second

buffer in the R register.

ENB

CLK

in

D

NOTES APPLICABLE TO EACH DEVICE:

by the new ratio after completing the rest of the present count cycle. CLK must be low during the ENB pulse, as shown. The C and A registers

Figure 25. Accessing the R Registers of T wo Cascaded

MC145202 Devices

MC145202 MOTOROLA
22

P ACKAGE DIMENSIONS

1

G

S

10 PL

0.13 (0.005) B

D

0.13 (0.005)MT

–A

–

MM

20 PL

S

B

SOG (SMALL OUTLINE GULL–WING) PACKAGE

F SUFFIX

CASE 751J–01

1120

–B

–

10

C

L

S

A

0.10 (0.004)

SEATING
PLANE

–T

–

M

J

K

DT SUFFIX

TSSOP (THIN SHRUNK SMALL OUTLINE PACKAGE)

CASE 948D–03

NOTES:

1. DIMENSIONS “A” AND “B” ARE DATUMS AND
“T” IS A DATUM SURFACE.

2. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

3. CONTROLLING DIM: MILLIMETER.

4. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.

5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

MILLIMETERS INCHES

MIN MINMAX MAX

DIM

A

12.55

12.80

0.494

B

5.10

C

—

D

0.35

G

1.27 BSC 0.050 BSC

J

0.18

K

0.55

L

0.05

M

0

°

S

7.40

5.40

2.00

0.45

0.23

0.85

0.20

8.20

7

°

0.201
—

0.014

0.007

0.022

0.002

0.291

0.504

0.213

0.079

0.018

0.009

0.033

0.008

0

7

°

°

0.323

PIN 1

IDENTIFICATION

0.100 (0.004)

SEATING

-T-

PLANE

A

20X REFK

0.200 (0.004)MT

20

L

1

11

B

10

C

J1

G

D

K

K1

H

A

M

J

A

SECTION A-A

F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE –U–.

-U-

MILLIMETERS

DIMAMIN MAX MIN MAX

––– 6.60 ––– 0.260

B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.25 0.002 0.010
F 0.45 0.55 0.018 0.022

G 0.65 BSC 0.026 BSC

H 0.275 0.375 0.011 0.015
J 0.09 0.24 0.004 0.009

J1 0.09 0.18 0.004 0.007

K 0.16 0.32 0.006 0.013

K1 0.16 0.26 0.006 0.010

L 6.30 6.50 0.248 0.256

M 0 10 0 10

°°°°

INCHES

MC145202MOTOROLA

23

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
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Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

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MC145202/D

24