Page 1
MC145190•MC145191MOTOROLA
1
Include On–Board 64/65 Prescalers
The MC145190 and MC145191 are single–package synthesizers with serial
interfaces capable of direct usage up to 1.1 GHz. A special architecture makes
these PLLs very easy to program because a byte–oriented format is utilized.
Due to the patented BitGrabber
registers, no address/steering bits are
required for
random access
of the three registers. Thus, tuning can be
accomplished via a 3–byte serial transfer to the 24–bit A register. The interface
is both SPI and MICROWIRE
compatible.
Each device features a single–ended current source/sink phase detector
output and a double–ended phase detector output. Both phase detectors have
linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor tied
from the Rx pin to ground. This current can be varied via the serial port.
The MC145190 features logic–level converters and high–voltage phase/
frequency detectors; the detector supply may range up to 9.5 V. The
MC145191 has lower–voltage phase/frequency detectors optimized for
single–supply systems of 5 V ±10%.
Each part includes a differential RF input which may be operated in a
single–ended mode. Also featured are on–board support of an external crystal
and a programmable reference output. The R, A, and N counters are fully
programmable. The C register (configuration register) allows the parts to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
In order to have consistent lock times and prevent erroneous data from being
loaded into the counters, on–board circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly, an update of the R register
is synchronized if the R counter is loading.
The double–buffered R register allows new divide ratios to be presented to
the three counters (R, A, and N) simultaneously.
• Maximum Operating Frequency: 1100 MHz @ Vin = 200 mV p–p
• Operating Supply Current: 7 mA Nominal
• Operating Supply Voltage Range (VDD and VCC Pins): 4.5 to 5.5 V
• Operating Supply Voltage Range of Phase Detectors (VPD Pin) —
MC145190: 8.0 to 9.5 V
MC145191: 4.5 to 5.5 V
• Current Source/Sink Phase Detector OUTPUT Capability: 2 mA Maximum
• Gain of Current Source/Sink Phase/Frequency Detector Controllable via
Serial Port
• Operating Temperature Range: – 40 to + 85°C
• R Counter Division Range: (1 and) 5 to 8191
• Dual–Modulus Capability Provides Total Division up to 262,143
• High–Speed Serial Interface: 4 Mbps
• OUTPUT A Pin, When Configured as Data Out, Permits Cascading of Devices
• Two General–Purpose Digital Outputs — OUTPUT A: Totem–Pole (Push–Pull)
OUTPUT B: Open–Drain
• Patented Power–Saving Standby Feature with Orderly Recovery for
Minimizing Lock Times, Standby Current: 30 µA
• Evaluation Kit Available (Part Numbers MC145190EVK and MC145191EVK)
• See Application Note AN1253/D for Low–Pass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
Order this document
by MC145190/D
SEMICONDUCTOR TECHNICAL DATA
f
in
TEST 2
OUTPUT B
OUTPUT A
CLK
12
13
14
15
16
1110
D
in
REF
in
V
CC
ENB
8
7
6
5
4
3
2
1
TEST 1
Rx
GND
PD
out
φ
V
φ
R
LD
REF
out
9
18
19
20
17
PIN ASSIGNMENT
V
PD
f
in
V
DD
F SUFFIX
SOG PACKAGE
CASE 751J
ORDERING INFORMATION
MC145190F SOG Package
MC145191F SOG Package
MC145190DT TSSOP
MC145191DT TSSOP
20
1
DT SUFFIX
TSSOP
CASE 948D
20
1
Motorola, Inc. 1998
REV 5
1/98 TN98012300
Page 2
MC145190•MC145191 MOTOROLA
2
ENB
REF
in
D
in
CLK
REF
out
f
in
f
in
OSC OR
4–STAGE
DIVIDER
(CONFIGURABLE)
20
1
18
19
11
10
OUTPUT A
INPUT
AMP
SELECT
LOGIC
3
13
24
13–STAGE R COUNTER
64/65
PRESCALER
MODULUS
CONTROL
LOGIC
12–STAGE
N COUNTER
6–STAGE
A COUNTER
INTERNAL
CONTROL
SHIFT
REGISTER
AND
CONTROL
LOGIC
STANDBY
LOGIC
POR
BitGrabber
A REGISTER
24 BITS
BitGrabber
C REGISTER
8 BITS
DOUBLE–BUFFERED
BitGrabber
R REGISTER
16 BITS
PHASE/FREQUENCY
DETECTOR B AND CONTROL
PHASE/FREQUENCY
DETECTOR A AND CONTROL
LOCK DETECTOR
AND CONTROL
6 12
4
2
LD
Rx
PD
out
φ
R
φ
V
OUTPUT B
(OPEN–DRAIN
OUTPUT)
TEST 2
TEST 1
9
15
13
4
3
6
8
2
16
SUPPLY CONNECTIONS:
PIN 12 = VCC (V+ TO INPUT AMP AND 64/65 PRESCALER)
PIN 5 = VPD (V+ TO PHASE/FREQUENCY DETECTORS A AND B)
PIN 14 = VDD (V+ TO BALANCE OF CIRCUIT)
PIN 7 = GND (COMMON GROUND)
17
DATA OUT
f
R
f
V
PORT
BLOCK DIAGRAM
MAXIMUM RATINGS*
(Voltages Referenced to GND, unless otherwise stated)
Symbol Parameter Value Unit
VCC,
V
DD
DC Supply Voltage (Pins 12 and 14) – 0.5 to + 6.0 V
V
PD
DC Supply Voltage (Pin 5) MC145190
MC145191
VDD – 0.5 to + 9.5
VDD – 0.5 to + 6.0
V
V
in
DC Input Voltage – 0.5 to VDD + 0.5 V
V
out
DC Output Voltage (except OUTPUT B, PD
out
,
φR, φV)
– 0.5 to VDD + 0.5 V
V
out
DC Output Voltage (OUTPUT B, PD
out
, φR, φV) – 0.5 to VPD + 0.5 V
Iin, I
PD
DC Input Current, per Pin (Includes VPD) ± 10 mA
I
out
DC Output Current, per Pin ± 20 mA
I
DD
DC Supply Current, VDD and GND Pins ± 30 mA
P
D
Power Dissipation, per Package 300 mW
T
stg
Storage Temperature – 65 to + 150 °C
T
L
Lead Temperature, 1 mm from Case for
10 seconds
260 °C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics tables
or Pin Descriptions section.
This device contains protection circuitry to
guard against damage due to high static voltages or electric fields. However, precautions
must be taken to avoid applications of any voltage higher than maximum rated voltages to
this high–impedance circuit.
Page 3
MC145190•MC145191MOTOROLA
3
ELECTRICAL CHARACTERISTICS
(VDD = VCC = 4.5 to 5.5 V , Voltages Referenced to GND, TA = –40 to +85°C, unless otherwise stated;
MC145190: VPD = 8.0 to 9.5 V; MC145191: VPD = 4.5 to 5.5 V with VDD ≤ VPD.)
Symbol
Parameter Test Condition
Guaranteed
Limit
Unit
V
IL
Maximum Low–Level Input Voltage
(Din, CLK, ENB
, REFin)
Device in Reference Mode, dc Coupled 0.3 × V
DD
V
V
IH
Minimum High–Level Input Voltage
(Din, CLK, ENB
, REFin)
Device in Reference Mode, dc Coupled 0.7 × V
DD
V
V
hys
Minimum Hysteresis Voltage (CLK, ENB) 300 mV
V
OL
Maximum Low–Level Output Voltage
(REF
out
, OUTPUT A)
I
out
= 20 µA, Device in Reference Mode 0.1 V
V
OH
Minimum High–Level Output Voltage
(REF
out
, OUTPUT A)
I
out
= –20 µA, Device in Reference Mode VDD – 0.1 V
I
OL
Minimum Low–Level Output Current
(REF
out
, LD, φR, φV)
V
out
= 0.4 V 0.36 mA
I
OH
Minimum High–Level Output Current
(REF
out
, LD, φR, φV)
V
out
= VDD – 0.4 V for REF
out
, LD
V
out
= VPD – 0.4 V for φR, φ
V
– 0.36 mA
I
OL
Minimum Low–Level Output Current
(OUTPUT A, OUTPUT B)
V
out
= 0.4 V 1.0 mA
I
OH
Minimum High–Level Output Current
(OUTPUT A, Only)
V
out
= VDD – 0.4 V – 0.6 mA
I
in
Maximum Input Leakage Current
(Din, CLK, ENB
, REFin)
Vin = VDD or GND, Device in XTAL Mode ± 1.0 µA
I
in
Maximum Input Current
(REFin)
Vin = VDD or GND, Device in Reference Mode ± 150 µA
I
OZ
Maximum Output Leakage Current (PD
out
) V
out
= VPD – 0.5 V or 0.5 V, MC145190
Output in High–Impedance State MC145191
± 150
± 200
nA
I
OZ
Maximum Output Leakage Current
(OUTPUT B)
V
out
= VPD or GND,
Output in High–Impedance State
± 10 µA
I
STBY
Maximum Standby Supply Current
(VDD + VPD Pins)
Vin = VDD or GND; Outputs Open; Device in Standby
Mode, Shut–Down Crystal Mode or REF
out
–Static–Low
Reference Mode; OUTPUT B Controlling VCC per
Figure 22
30 µA
I
PD
Maximum Phase Detector
Quiescent Current (VPD Pin)
Bit C6 = High Which Selects Phase Detector A,
PD
out
= Open, PD
out
= Static Low or High, Bit C4 = Low
Which is
not
Standby, IRx = 113 µA
600 µA
Bit C6 = Low Which Selects Phase Detector B, φR and
φV = Open, φR and φV = Static Low or High, Bit
C4 = Low Which is
not
Standby
30
I
T
Total Operating Supply Current
(VDD + VPD + VCC Pins)
fin = 1.1 GHz; REFin = 13 MHz @ 1 V p–p;
OUTPUT A = Inactive and No Connect;
REF
out
÷ 8; φV, φR, PD
out
, LD = No Connect;
Din, ENB
, CLK = VDD or GND, Phase Detector B Selected
(Bit C6 = Low)
* mA
*The nominal value = 7 mA. This is not a guaranteed limit.
Page 4
MC145190•MC145191 MOTOROLA
4
ANALOG CHARACTERISTICS—CURRENT SOURCE/SINK OUTPUT—PD
out
(I
out
≤ 2 mA, VDD = VCC = 4.5 to 5.5 V , VDD ≤ VPD. Voltages Referenced to GND)
Parameter
Test Condition V
PD
Guaranteed
Limit
Unit
Maximum Source Current Variation (Part–to–Part) MC145190: V
out
= 0.5 × V
PD
8.0 ± 20 %
9.5 ± 20
MC145191: V
out
= 0.5 × V
PD
4.5 ± 20 %
5.5 ± 20
Maximum Sink–vs–Source Mismatch (Note 3) MC145190: V
out
= 0.5 × V
PD
8.0 12 %
9.5 12
MC145191: V
out
= 0.5 × V
PD
4.5 12 %
5.5 12
Output Voltage Range (Note 3) MC145190: I
out
Variation ≤ 20% 8.0 0.5 to 7.5 V
9.5 0.5 to 9.0
MC145191: I
out
Variation ≤ 20% 4.5 0.5 to 4.0 V
5.5 0.5 to 5.0
NOTES:
1. Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.
2. See Rx Pin Description for external resistor values.
3. This parameter is guaranteed for a given temperature within – 40° to + 85°C.
AC INTERFACE CHARACTERISTICS (V
DD
= 4.5 to 5.5 V , TA = – 40 to + 85°C, CL = 50 pF, Input tr = tf = 10 ns;
MC145190: VPD = 8.0 to 9.5 V; MC145191: VPD = 4.5 to 5.5 V with VDD ≤ VPD)
Symbol
Parameter
Figure
No.
Guaranteed
Limit
Unit
f
clk
Serial Data Clock Frequency (Note: Refer to Clock tw below) 1 dc to 4.0 MHz
t
PLH
, t
PHL
Maximum Propagation Delay, CLK to OUTPUT A (Selected as Data Out) 1, 5 105 ns
t
PLH
, t
PHL
Maximum Propagation Delay, ENB to OUTPUT A (Selected as Port) 2, 5 100 ns
t
PZL
, t
PLZ
Maximum Propagation Delay, ENB to OUTPUT B 2, 6 120 ns
t
TLH
, t
THL
Maximum Output Transition Time, OUTPUT A and OUTPUT B;
t
THL
ONLY, on OUTPUT B
1, 5, 6 100 ns
C
in
Maximum Input Capacitance – Din, ENB, CLK 10 pF
TIMING REQUIREMENTS
(VDD = VCC = 4.5 to 5.5 V , TA = – 40 to + 85°C, Input tr = tf = 10 ns unless otherwise indicated)
Symbol
Parameter
Figure
No.
Guaranteed
Limit
Unit
tsu, t
h
Minimum Setup and Hold Times, Din vs CLK 3 20 ns
tsu, th, t
rec
Minimum Setup, Hold and Recovery Times, ENB vs CLK 4 100 ns
t
w
Minimum Pulse Width, ENB 4 * cycles
t
w
Minimum Pulse Width, CLK 1 125 ns
tr, t
f
Maximum Input Rise and Fall Times – CLK 1 100 µs
*The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.
Page 5
MC145190•MC145191MOTOROLA
5
SWITCHING W AVEFORMS
10%
V
DD
GND
1/f
clk
OUTPUT A
(DATA OUT)
CLK
90%
50%
90%
50%
10%
t
PLH
t
PHL
t
TLH
t
THL
t
w
t
w
t
f
t
r
Figure 1.
ENB
OUTPUT A
OUTPUT B
10%
V
DD
GND
50%
50%
t
PLZ
t
PLHtPHL
50%
t
PZL
Figure 2.
D
in
CLK
50%
VALID
50%
t
su
t
h
V
DD
GND
V
DD
GND
Figure 3.
CLK
ENB
50%
t
su
t
h
FIRST
CLK
LAST
CLK
t
rec
50%
Figure 4.
V
DD
GND
V
DD
GND
t
w
t
w
TEST POINT
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and fixture capacitance.
Figure 5. Test Circuit
TEST POINT
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and fixture capacitance.
Figure 6. Test Circuit
V +
7.5 k
Ω
Page 6
MC145190•MC145191 MOTOROLA
6
LOOP SPECIFICATIONS (V
DD
= VCC = 4.5 to 5.5 V unless otherwise indicated, TA = – 40 to + 85°C)
Figure
Guaranteed
Operating Range
Symbol Parameter Test Condition
Figure
No.
Min Max
Unit
V
in
Input Voltage Range, f
in
100 MHz ≤ fin < 250 MHz
250 MHz ≤ fin ≤ 1100 MHz
7 400
200
1500
1500
mV p–p
f
ref
Input Frequency Range, REF
in
MC145190
Externally Driven in
Reference Mode MC145191
Vin ≥ 400 mV p–p
Vin ≥ 1 V p–p
Vin ≥ 400 mV p–p
Vin ≥ 1 V p–p
8 13
6*
12
4.5*
27
27
27
27
MHz
f
XTAL
Crystal Frequency, Crystal Mode C1 ≤ 30 pF, C2 ≤ 30 pF, Includes
Stray Capacitance
9 2 15 MHz
f
out
Output Frequency, REF
out
CL = 30 pF 10, 12 dc 10 MHz
f Operating Frequency of the Phase Detectors dc 2 MHz
t
w
Output Pulse Width, φR, φV, LD MC145190
MC145191
fR in Phase with fV, CL = 50 pF,
VPD = 5.5 V , VDD = VCC = 5.0 V
11, 12 17 85 ns
t
TLH
,
t
THL
Output Transition Times, LD, φV,
φR— MC145191
CL = 50 pF, VPD = 5.5 V,
VDD = VCC = 5.0 V
11, 12 — 65 ns
C
in
Input Capacitance, REF
in
— 5 pF
*If lower frequency is desired, use wave shaping or higher amplitude sinusoidal signal.
SINE WAVE
GENERATOR
1000 pF
DEVICE
UNDER
TEST
1000 pF
TEST
POINT
V+
V
CC
V
DD
f
in
f
in
GND
OUTPUT A
V
in
50
Ω
*
Figure 7. Test Circuit
(fv)
*Characteristic Impedance
SINE WAVE
GENERATOR
50
Ω
DEVICE
UNDER
TEST
0.01
µ
F
TEST
POINT
V
CC
V
DD
REF
in
GND
OUTPUT A
V
in
Figure 8. Test Circuit — Reference Mode
(fR)
TEST
POINT
REF
out
V+
DEVICE
UNDER
TEST
C1
TEST
POINT
V
CC
V
DD
OUTPUT A
GND
REF
in
REF
out
C2
Figure 9. Test Circuit — Crystal Mode
(fR)
V+
50%
REF
out
1/f REF
out
Figure 10. Switching Waveform
Page 7
MC145190•MC145191MOTOROLA
7
10%
90%
OUTPUT
t
TLH
t
THL
Figure 11. Switching Waveform
50%
t
w
TEST POINT
DEVICE
UNDER
TEST
C
L
*
Figure 12. Test Circuit
*Includes all probe and
fixture capacitance.
NORMALIZED INPUT IMPEDANCE AT fin — SERIES FORMAT (R + jX)
(100 MHz to 1.1 GHz)
3
4
2
1
Frequency Resistance Capacitive Capacitance
Marker (MHz) (Ω) Reactance (Ω) (pF)
1 100 338 – 785 2.03
2 500 20.2 – 183 1.74
3 800 11.5 – 109 1.83
4 1100 8.2 – 70.2 2.06
fin (PIN 11)
SOG PACKAGE
Page 8
MC145190•MC145191 MOTOROLA
8
2
3
STAR T 50 MHz STOP 1500 MHz
1
4
RETURN LOSS AT f
in
STAR T 50 MHz STOP 1500 MHz
STANDING WAVE RATIO AT f
in
4
2
3
Frequency Return Loss
Marker (MHz) SWR (dB)
1 100 43.7 0.40
2 500 34.7 0.48
3 800 25.3 0.68
4 1100 17.9 0.98
0 dB
– 5 dB
– 10 dB
51
26
1
1
Page 9
MC145190•MC145191MOTOROLA
9
PIN DESCRIPTIONS
DIGITAL INTERFACE PINS
D
in
Serial Data Input (Pin 19)
The bit stream begins with the most significant bit (MSB)
and is shifted in on the low–to–high transition of CLK. The bit
pattern is 1 byte (8 bits) long to access the C or configuration
register, 2 bytes (16 bits) to access the first buffer of the R
register, or 3 bytes (24 bits) to access the A register (see
Table 1). The values in the C, R, and A registers do not
change during shifting because the transfer of data to the
registers is controlled by ENB.
CAUTION
The value programmed for the N–counter must be
greater than or equal to the value of the A–counter.
The 13 least significant bits (LSBs) of the R register are
double–buffered. As indicated above, data is latched into the
first buffer on a 16–bit transfer. (The 3 MSBs are not double–
buffered and have an immediate effect after a 16–bit transfer.) The second buffer of the R register contains the 13 bits
for the R counter. This second buffer is loaded with the contents of the first buffer when the A register is loaded (a 24–bit
transfer). This allows presenting new values to the R, A, and
N counters simultaneously. If this is not required, then the
16–bit transfer may be followed by pulsing ENB
low with no
signal on the CLK pin. This is an alternate method of
transferring data to the second buffer of the R register (see
Figure 17).
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber registers. Therefore, all bits in
the stream are available to be data for the three registers.
Random access of any register is provided. That is, the registers may be accessed in any sequence. Data is retained in
the registers over a supply range of 4.5 to 5.5 V . The formats
are shown in Figures 15, 16, and 17.
Din typically switches near 50% of VDD to maximize noise
immunity. This input can be directly interfaced to CMOS devices with outputs guaranteed to switch near rail–to–rail.
When interfacing to NMOS or TTL devices, either a level
shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 kΩ
to 10 kΩ must be used. Parameters to consider when sizing
the resistor are worst–case IOL of the driving device, maximum tolerable power consumption, and maximum data rate.
Table 1. Register Access
(MSBs are shifted in first; C0, R0, and A0 are the LSBs)
Number
of Clocks
Accessed
Register
Bit
Nomenclature
8
16
24
Other Values ≤ 32
Values > 32
C Register
R Register
A Register
See Figure 13
See Figures
22 – 25
C7, C6, C5, . . ., C0
R15, R14, R13, . . ., R0
A23, A22, A21, . . ., A0
CLK
Serial Data Clock Input (Pin 18)
Low–to–high transitions on CLK shift bits available at
the Din pin, while high–to–low transitions shift bits from
OUTPUT A (when configured as Data Out, see Pin 16).
The 24–1/2–stage shift register is static, allowing clock
rates down to dc in a continuous or intermittent mode.
Eight clock cycles are required to access the C register.
Sixteen clock cycles are needed for the first buffer of the R
register. Twenty–four cycles are used to access the A register. See Table 1 and Figures 15, 16, and 17. The number of
clocks required for cascaded devices is shown in Figures 24
through 26.
CLK typically switches near 50% of VDD an d has a
Schmitt–triggered input buffer. Slow CLK rise and fall times
are allowed. See the last paragraph of Din for more information.
NOTE
To guarantee proper operation of the power–on
reset (POR) circuit, the CLK pin must be held at
GND (with ENB
being a don’t care) or ENB must
be held at the potential of the V+ pin (with CLK being a don’t care) during power–up. As an alternative, the bit sequence of Figure 13 may be used.
ENB
Active Low Enable Input (Pin 17)
This pin is used to activate the serial interface to allow the
transfer of data to/from the device. When ENB
is in an inactive high state, shifting is inhibited and the port is held in the
initialized state. To transfer data to the device, ENB
(which
must start inactive high) is taken low, a serial transfer is
made via Din and CLK, and ENB
is taken back high. The
low–to–high transition on ENB
transfers data to the C or A
registers and first buffer of the R register, depending on the
data stream length per Table 1.
NOTE
Transitions on ENB
must not be attempted while
CLK is high. This puts the device out of synchronization with the microcontroller. Resynchronization occurs whenever ENB
is high and CLK is
low.
This input is also Schmitt–triggered and switches near
50% of VDD, thereby minimizing the chance of loading erroneous data into the registers. See the last paragraph of D
in
for more information.
For POR information, see the note for the CLK pin.
OUTPUT A
Configurable Digital Output (Pin 16)
OUTPUT A is selectable as fR, fV, Data Out, or Port.
Bits A22 and A23 in the A register control the selection;
see Figure 16.
If A23 = A22 = high, OUTPUT A is configured as
fR. This signal is the buffered output of the 13–stage R
counter. The fR signal appears as normally low and
pulses high, and can be used to verify the divide ratio of
the R counter. This ratio extends from 5 to 8191 and is
determined by the binary value loaded into bits R0–R12
in the R register. Also, direct acc ess to the phase detectors via the REFin pin is allowed by choosing a divide
value of 1 (see Figure 17). The maximum frequency at
which the phase detectors operate is 2 MHz. Therefore,
the frequency of fR should not exceed 2 MHz.
If A23 = high and A22 = low, OUTPUT A is configured as
fV. This signal is the buffered output of the 12–stage N
counter. The fV signal appears as normally low and pulses
high, and can be used to verify the operation of the prescaler,
Page 10
MC145190•MC145191 MOTOROLA
10
A counter, and N counter. The divide ratio between the fin input and the fV signal is N × 64 + A. N is the divide ratio of the
N counter and A is the divide ratio of the A counter. The s e
ratios are determined by bits loaded into the A register. See
Figure 16. The max imum frequency at which the phase
detectors operate is 2 MHz. Therefore, the frequency of f
V
should not exceed 2 MHz.
If A23 = low and A22 = high, OUTPUT A is configured as
Data Out. This signal is the serial output of the 24–1/2–stage
shift register. The bit stream is shifted out on the high–to–low
transition of the CLK input. Upon power up, OUTPUT A is
automatically configured as Data Out to facilitate cascading
devices.
If A23 = A22 = low, OUTPUT A is configured as Port. This
signal is a general–purpose digital output which may be used
as an MCU port expander. This signal is low when the Port
bit (C1) of the C register is low, and high when the Port bit is
high.
OUTPUT B
Open–Drain Digital Output (Pin 15)
This signal is a general–purpose digital output which
may be used as an MCU port expander. This signal is low
when the Out B bit (C0) of the C register is low. When the
Out B bit is high, OUTPUT B assumes the high–impedance state. OUTPUT B may be pulled up through an
external resistor or active circuitry to any voltage less
than or equal to the potential of the VPD pin. Note: the
maximum voltage allowed on the VPD pin is 9.5 V for the
MC145190 and 5.5 V for the MC145191.
Upon power–up, power–on reset circuitry forces OUTPUT
B to a low level.
REFERENCE PINS
REFin and REF
out
Reference Input and Reference Output (Pins 20 and 1)
Configurable pins for a Crystal or an External Reference.
This pair of pins can be configured in one of two modes: the
crystal mode or the reference mode. Bits R13, R14, and R15
in the R register control the modes as shown in Figure 17.
In crystal mode, these pins form a reference oscillator
when connected to terminals of an external parallel–resonant crystal. Frequency–setting capacitors of appropriate
values as recommended by the crystal supplier are connected from each of the two pins to ground (up to a maximum
of 30 pF each, including stray capacitance). An external resistor of 1 MΩ to 15 MΩ is connected directly across the pins
to ensure linear operation of the amplifier. The device is designed to operate with crystals up to 15 MHz; the required
connections are shown in Figure 9. To turn on the oscillator,
bits R15, R14, and R13 must have an octal value of one (001
in binary, respectively). This is the active–crystal mode
shown in Figure 17. In this mode, the crystal oscillator runs
and the R Counter divides the crystal frequency, unless the
part is in standby. If the part is placed in standby via the C
register, the oscillator runs, but the R counter is stopped.
However, if bits R15 to R13 have a value of 0, the oscillator is
stopped, which saves additional power. This is the shut–
down crystal mode (shown in Figure 17) and can be engaged
whether in standby or not.
In the reference mode, REFin (Pin 20) accepts a signal up
to 27 MHz from an external reference oscillator, such as a
TCXO. A signal swinging from at least the VIL to VIH levels
listed in the Electrical Characteristics table may be directly
coupled to the pin. If the signal is less than this level, ac coupling must be used as shown in Figure 8. Due to an on–
board resistor which is engaged in the reference modes, an
external biasing resistor tied between REFin and REF
out
is
not required.
With the reference mode, the REF
out
pin is configured as
the output of a divider. As an example, if bits R15, R14, and
R13 have an octal value of seven, the frequency at REF
out
is
the REFin frequency divided by 16. In addition, Figure 17
shows how to obtain ratios of eight, four, and two. A ratio of
one–to–one can be obtained with an octal value of three.
Upon power up, a ratio of eight is automatically initialized.
The maximum frequency capability of the REF
out
pin is
10 MHz. Therefore, for REFin frequencies above 10 MHz,
the one–to–one ratio may not be used. Likewise, for REF
in
frequencies above 20 MHz, the ratio must be more than two.
If REF
out
is unused, an octal value of two should be used
for R15, R14, and R13 and the REF
out
pin should be floated.
A value of two allows REFin to be functional while disabling
REF
out
, which minimizes dynamic power consumption and
electromagnetic interference (EMI).
LOOP PINS
fin and f
in
Frequency Inputs (Pins 11 and 10)
These pins are frequency inputs from the VCO. These pins
feed the on–board RF amplifier which drives the 64/65 prescaler. These inputs may be fed differentially. However, they
usually are used in a single–ended configuration (shown in
Figure 7). Note that fin is driven while f
in
must be tied to
ground via a capacitor.
Motorola does not recommend driving f
in
while terminating
fin because this configuration is not tested for sensitivity. The
sensitivity is dependent on the frequency as shown in the
Loop Specifications table.
PD
out
Single–Ended Phase/Frequency Detector Output (Pin 6)
This is a three–state current–source/sink output for use as
a loop error signal when combined with an external low–pass
filter. The phase/frequency detector is characterized by a linear transfer function (no dead zone). The operation of the
phase/frequency detector is described below and is shown in
Figure 18.
POL bit (C7) in the C register = low (see Figure 15)
Frequency of fV > fR or Phase of fV Leading fR: current–
sinking pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR: current–
sourcing pulses from a floating state
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR: current–
sourcing pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR: current–
sinking pulses from a floating state
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
This output can be enabled, disabled, and inverted via the
C register. If desired, PD
out
can be forced to the floating state
by utilization of the disable feature in the C register (bit C6).
This is a patented feature. Similarly, PD
out
is forced to the
Page 11
MC145190•MC145191MOTOROLA
11
floating state when the device is put into standby (STBY bit
C4 = high).
The PD
out
circuit is powered by VPD. The phase detector gain is controllable by bits C3, C2, and C1: gain (in
amps per radian) = PD
out
current divided by 2π.
φR and φV (Pins 3 and 4)
Double–Ended Phase/Frequency Detector Outputs
These outputs can be combined externally to generate
a loop error signal. Through use of a Motorola patented
technique, the detector’s dead zone has been eliminated.
Therefore, the phase/frequency detector is characterized
by a linear transfer function. The operation of the phase/
frequency detector is des cribed below and is shown in
Figure 18.
POL bit (C7) in the C register = low (see Figure 15)
Frequency of fV > fR or Phase of fV Leading fR: φV = nega-
tive pulses, φR = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φV = essen-
tially high, φR = negative pulses
Frequency and Phase of fV = fR: φV and φR remain essen-
tially high, except for a small minimum time period when
both pulse low in phase
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR: φR = nega-
tive pulses, φV = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φR = essen-
tially high, φV = negative pulses
Frequency and Phase of fV = fR: φV and φR remain essen-
tially high, except for a small minimum time period when
both pulse low in phase
These outputs can be enabled, disabled, and inter-
changed via C register bits C6 or C4. This is a patented feature. Note that when disabled or in standby, φR and φV are
forced to their rest condition (high state).
The φR and φV output signal swing is approximately from
GND to VPD.
LD
Lock Detector Output (Pin 2)
This output is essentially at a high level with narrow
low–going pulses when the loop is locked (fR and fV of the
same phase and frequency). The output pulses low when
fV and fR are out of phase or different frequencies. LD is
the logical ANDing of φR and φV (see Figure 18).
This output can be enabled and disabled via the C register.
This is a patented feature. Upon power up, on–chip initialization circuitry disables LD to a static low logic level to prevent
a false “lock” signal. If unused, LD should be disabled and
left open.
The LD output signal swing is approximately from GND to
VDD.
Rx
External Resistor (Pin 8)
A resistor tied between this pin and GND, in conjunction
with bits in the C register, determines the amount of current
that the PD
out
pin sinks and sources. When bits C2 and C3
are both set high, the maximum current is obtained at PD
out
;
see Tables 2 and 3 for other values of current. To achieve a
maximum current of 2 mA, the resistor should be about
47 kΩ when VPD is 9 V or about 18 kΩ when VPD is 5.0 V.
See Figure 14 if lower maximum current values are desired.
When the φR and φV outputs are used, the Rx pin may be
floated.
TEST POINT PINS
TEST 1
Modulus Control Signal (Pin 9)
This pin may be used in conjunction with the Test 2 pin for
access to the on–board 64/65 prescaler. When Test 1 is low,
the prescaler divides by 65. When high, the prescaler divides
by 64.
CAUTION
This pin is an unbuffered output and
must
be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.
TEST 2
Prescaler Output (Pin 13)
This pin may be used to access to the on–board 64/65
prescaler output.
CAUTION
This pin is an unbuffered output and
must
be
floated in an actual application. This pin must be
attached to an isolated pad with no trace.
POWER SUPPLY PINS
V
DD
Positive Power Supply (Pin 14)
This pin supplies power to the main CMOS digital portion of the device. The voltage range is + 4.5 to + 5.5 V
with respect to the GND pin.
For optimum performance, VDD should be bypassed to
GND using a low–inductance capacitor mounted very
close to these pins. Lead lengths on the capacitor should
be minimized.
V
CC
Positive Power Supply (Pin 12)
This pin supplies power to the RF amp and 64/65 prescaler. The voltage range is +
4.5 to + 5.5 V with respect to
the GND pin. In the standby mode, the VCC pin still draws a
few milliamps from the power supply. This current drain can
be eliminated with the use of transistor Q1 as shown in
Figure 22.
For optimum performance, VCC should be bypassed to
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
V
PD
Positive Power Supply (Pin 5)
This pin supplies power to both phase/frequency detectors
A and B. The voltage applied on this pin must be no less than
the potential applied to the VDD pin. The maximum voltage
can be +9.5 V with respect to the GND pin for the MC145190
and +5.5 V for the MC145191.
For optimum performance, VPD should be bypassed to
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
GND
Ground (Pin 7)
Common ground.
Page 12
MC145190•MC145191 MOTOROLA
12
100 ns MINIMUM
12 4 531245312453
Figure 13. Initializing the PLL through the Serial Port
NOTE: It may not be convenient to control the ENB or CLK pins during power up per the Pin Descriptions. If this is the case, the part may
be initialized through the serial port as shown in the figure above. The sequence is similar to accessing the registers except that the
CLK must remain high at least 100 ns after ENB
is brought high. Note that 3 groups of 5 bits are needed.
CLK
D
in
ENB
MC145190
Nominal PD
out
Spurious Current vs fR Frequency
(1 V t PD
out
t VPD – 1 V)
f
R
(kHz)
Current
(RMS nA)
10 1.6
20 5.3
50 22
100 95
200 320
MC145191
Nominal PD
out
Spurious Current vs fR Frequency
(1 V t PD
out
t VPD – 1 V)
f
R
(kHz)
Current
(RMS nA)
10 3.6
20 4.6
50 17
100 75
200 244
NOTE: For information on spurious current measurement see AN1253/D, “An Improved PLL Design Method Without ωn and ζ”.
Table 2. PD
out
Current, C1 = Low with OUTPUT A
NOT
Selected as “Port”; Also, Default Mode When
OUTPUT A Selected as “Port”
C3 C2 PD
out
Current
0 0 70%
0 1 80%
1 0 90%
1 1 100%
Table 3. PD
out
Current, C1 = High with OUTPUT A
NOT
Selected as “Port”
C3 C2 PD
out
Current
0 0 25%
0 1 50%
1 0 75%
1 1 100%
Page 13
MC145190•MC145191MOTOROLA
13
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3
I
out
, SOURCE CURRENT (mA)
Ω
Rx, EXTERNAL RESISTOR (k )
Nominal MC145190 PD
out
Source Current vs Rx Resistance
VPD = 9.5 V
VPD = 8.75 V
VPD = 8.0 V
PD
out
CURRENT SET TO 100%;
PD
out
VOLTAGE IS FORCED TO ONE–HALF OF VPD.
0
10
20
30
40
50
60
70
80
90
100
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3
I
out
, SOURCE CURRENT (mA)
VPD = 5.5 V
VPD = 5.0 V
VPD = 4.5 V
NOTE: The MC145191 is optimized for Rx values in the 18 kΩ to 40 kΩ range. For example, to achieve 0.3 mA of output current,
it is preferable to use a 30–kΩ resistor for Rx and bit settings for 25% (as shown in Table 3).
Ω
Rx, EXTERNAL RESISTOR (k )
Nominal MC145191 PD
out
Source Current vs Rx Resistance
PD
out
CURRENT SET TO 100%;
PD
out
VOLTAGE IS FORCED TO ONE–HALF OF VPD.
Figure 14.
Page 14
MC145190•MC145191 MOTOROLA
14
ENB
CLK
D
in
MSB LSB
C7 C6 C5 C4 C3 C2 C1 C0
12345678
*
*At this point, the new byte is transferred to the C register and stored. No other registers are
affected.
C7 — POL: Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts the polarity
of PD
out
and interchanges the φR function with φV as depicted in Figure 18. Also see the phase detector
output pin descriptions for more information. This bit is cleared low at power up.
C6 — PDA/B: Selects which phase/frequency detector is to be used. When set high, enables the output of phase/
frequency detector A (PD
out
) and disables phase/frequency detector B by forcing φR and φV to the
static high state. When cleared low, phase/frequency detector B is enabled (φR and φV) and phase/
frequency detector A is disabled with PD
out
forced to the high–impedance state. This bit is cleared
low at power up.
C5 — LDE: Enables the lock detector output (LD) when set high. When the bit is cleared low, the LD output
is forced to a static low level. This bit is cleared low at power up.
C4 — STBY: When set high, places the CMOS section of device, which is powered by the VDD and VPD pins,
in the standby mode for reduced power consumption: PD
out
is forced to the high–impedance state,
φR and φV are forced high, the A, N, and R counters are inhibited from counting, and the Rx current
is shut off. In standby, the state of LD is determined by bit C5. C5 low forces LD low (no change).
C5 high forces LD static high. During standby, data is retained in the A, R, and C registers. The
condition of REF/OSC circuitry is determined by the control bits in the R register: R13, R14, and
R15. However, if REF
out
= static low is selected, the internal feedback resistor is disconnected and
the input is inhibited when in standby; in addition, the REFin input only presents a capacitive load.
NOTE: Standby does not affect the other modes of the REF/OSC circuitry.
When C4 is reset low, the part is taken out of standby in 2 steps. First, the REFin (only in one mode)
resistor is reconnected, all counters are enabled, and the Rx current is enabled. Any fR and fV signals
are inhibited from toggling the phase/frequency detectors and lock detector. Second, when the first
fV pulse occurs, the R counter is jam loaded, and the phase/frequency and lock detectors are
initialized. Immediately after the jam load, the A, N, and R counters begin counting down together.
At this point, the fR and fV pulses are enabled to the phase and lock detectors. (Patented feature.)
C3, C2 — I2, I1: Controls the PD
out
source/sink current per Tables 2 and 3. With both bits high, the maximum current
(as set by Rx per Figure 14) is available. Also, see C1 bit description.
C1 — Port: When the OUTPUT A pin is selected as “Port” via bits A22 and A23, C1 determines the state of
OUTPUT A. When C1 is set high, OUTPUT A is forced high; C1 low forces OUTPUT A low. When
OUTPUT A is NOT selected as “Port,” C1 controls whether the PD
out
step size is 10% or 25%. (See
Tables 2 and 3.) When low, steps are 10%. When high, steps are 25%. Default is 10% steps when
OUTPUT A is selected as “Port.” The Port bit is not affected by the standby mode.
C0 — Out B: Determines the state of OUTPUT B. When C0 is set high, OUTPUT B is high–impedance; C0 low
forces OUTPUT B low. The Out B bit is not affected by the standby mode. This bit is cleared low
at power up.
Figure 15. C Register Access and Format (8 Clock Cycles are Used)
Page 15
MC145190•MC145191MOTOROLA
15
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A23
NOTE 3
234567891011121314151617181920212223241
11
MSB LSB
001
1
010
1
PORTDf
f
V
R
BINARY
VALUE
OUTPUT A
FUNCTION
(NOTE 1)
BOTH BITS
MUST BE
HIGH
0000000
0
0000000
0
0123456
7
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
N COUNTER = 5
N COUNTER = 6
N COUNTER = 7
÷÷÷
...
F
F
...
F
F
...
E
F
N COUNTER = 4094
N COUNTER = 4095
÷
÷
HEXADECIMAL VALUE
FOR N COUNTER
000
0
3
012
3
E
A COUNTER = 0
A COUNTER = 1
A COUNTER = 2
A COUNTER = 3
A COUNTER = 62
÷
4 1 NOT ALLOWED
HEXADECIMAL VALUE
FOR A COUNTER
3
4
F
0
A COUNTER = 63
NOT ALLOWED
÷
...
F
...
F NOT ALLOWED
÷÷÷
÷
...
...
NOTES:
1. A power–on initialize circuit forces the OUTPUT A function to default to Data Out.
2. The values programmed for the N counter must be greater than or equal to the values programmed for the A counter. This results in a total divide value = N x 64 + A.
3. At this point, the three new bytes are transferred to the A register. In addition, the 13 LSBs in the first buffer of the R register are transferred to the R register’s second buffer.
Thus, the R, N, and A counters can be presented new divide ratios at the same time. The first buffer of the R register is not affected. The C register is not affected.
ENB
CLK
Figure 16. A Register Access and Format (24 Clock Cycles are Used)
D
in
out
Page 16
MC145190•MC145191 MOTOROLA
16
ENB
CLK
D
in
12345678
MSB LSB
R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0R11R12R13R14R15
9 10111213 1415 16
0
0
0
0
0
0
0
0
0
·
·
·
F
F
0
0
0
0
0
0
0
0
0
·
·
·
F
F
0
1
2
3
4
5
6
7
8
·
·
·
E
F
NOT ALLOWED
R COUNTER =
÷
1 (NOTE 6)
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
R COUNTER =
÷
5
R COUNTER =
÷
6
R COUNTER =
÷
7
R COUNTER =
÷
8
R COUNTER =
÷
8190
R COUNTER =
÷
8191
HEXADECIMAL VALUE
0
0
0
0
0
0
0
0
0
·
·
·
1
1
BINARY VALUE
0
1
2
3
4
5
6
7
CRYST AL MODE, SHUT DOWN
CRYST AL MODE, ACTIVE
REFERENCE MODE, REFin ENABLED and REF
out
STATIC LOW
REFERENCE MODE, REF
out
= REFin (BUFFERED)
REFERENCE MODE, REF
out
= REFin/2
REFERENCE MODE, REF
out
= REFin/4
REFERENCE MODE, REF
out
= REFin/8 (NOTE 3)
REFERENCE MODE, REF
out
= REFin/16
OCTAL VALUE
NOTES:
1. Bits R15 through R13 control the configurable “OSC or 4–stage divider” block (see Block Diagram).
2. Bits R12 through R0 control the “13–stage R counter” block (see Block Diagram).
3. A power–on initialize circuit forces a default REFin to REF
out
ratio of eight.
4. At this point, bits R13, R14, and R15 are stored and sent to the “OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 through
R12 are loaded into the first buffer in the double–buffered section of the R register. Therefore, the R counter divide ratio is not altered
yet and retains the previous ratio loaded. The C and A registers are not affected.
5. At this point, bits R0 through R12 are transferred to the second buffer of the R register. The R counter begins dividing by the new ratio
after completing the rest of the present count cycle. CLK must be low during the ENB
pulse, as shown. Also, see note 3 of Figure 16 for
an alternate method of loading the second buffer in the R register . The C and A registers are not affected. The first buf fer of the R register
is not affected.
6. Allows direct access to reference input of phase/frequency detectors.
NOTE4NOTE
5
Figure 17. R Register Access and Format (16 Clock Cycles Are Used)
Page 17
MC145190•MC145191MOTOROLA
17
NOTE: The PD
out
either sources or sinks current during out–of–lock conditions. When locked in phase and frequency,
the output is high impedance and the voltage at that pin is determined by the low–pass filter capacitor. PD
out
, φR,
and φV are shown with the polarity bit (POL) = low; see Figure 14 for POL.
f
R
REFERENCE
REFin
÷
R
f
V
FEEDBACK
fin
÷
(N ×64 + A)
PD
out
φ
R
φ
V
LD
V
H
V
L
SOURCING CURRENT
V
H
V
H
V
L
FLOAT
V
H
V
L
V
L
V
L
V
H
SINKING CURRENT
VH = High voltage level
VL = Low voltage level
*At this point, when both fR and fV are in phase, the output source and sink circuits are turned on for a short interval.
*
Figure 18. Phase/Frequency Detectors and Lock Detector Output Waveforms
DESIGN CONSIDERA TIONS
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a reference frequency to Motorola’s CMOS frequency synthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscillators provide very stable reference frequencies. An oscillator
capable of CMOS logic levels at the output may be direct or
dc coupled to REFin. If the oscillator does not have CMOS
logic levels on the outputs, capacitive or ac coupling to REF
in
may be used (see Figure 8).
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the
eem Elec-
tronic Engineers Master Catalog,
the
Gold Book,
or similar
publications.
Design an Off–Chip Reference
The user may design an off–chip crystal oscillator using
discrete transistors or ICs specifically developed for crystal
oscillator applications, such as the MC12061 MECL device.
The reference signal from the MECL device is ac coupled to
REFin (see Figure 8). For large amplitude signals (standard
CMOS logic levels), dc coupling may be used.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 19.
The crystal should be specified for a loading capacitance
(CL) which does not exceed approximately 20 pF when used
at the highest operating frequency of 15 MHz. Assuming
R1 = 0 Ω, the shunt load capacitance (CL) presented across
the crystal can be estimated to be:
CL =
CinC
out
Cin+C
out
+ Ca + C
stray
+
C1 • C2
C1 + C2
where
Cin = 5 pF (see Figure 20)
C
out
= 6 pF (see Figure 20)
Ca = 1 pF (see Figure 20)
C1 and C2 =external capacitors (see Figure 19)
C
stray
= the total equivalent external circuit stray capaci–
tance appearing across the crystal terminals
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated components must be located as close as possible to the REF
in
and REF
out
pins to minimize distortion, stray capacitance,
stray inductance, and startup stabilization time. Circuit stray
capacitance can also be handled by adding the appropriate
stray value to the values for Cin and C
out
. For this approach,
the term C
stray
becomes 0 in the above expression for CL.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 21. The maximum drive level specified
by the crystal manufacturer represents the maximum stress
that the crystal can withstand without damage or excessive
shift in operating frequency. R1 in Figure 19 limits the drive
level. The use of R1 is not necessary in most cases.
To verify that the maximum dc supply voltage does not
cause the crystal to be overdriven, monitor the output
Page 18
MC145190•MC145191 MOTOROLA
18
frequency (fR) at OUTPUT A as a function of supply voltage.
(REF
out
is not used because loading impacts the oscillator.)
The frequency should increase very slightly as the dc supply
voltage is increased. An overdriven crystal decreases in frequency or becomes unstable with an increase in supply voltage. The operating supply voltage must be reduced or R1
must be increased in value if the overdriven condition exists.
The user should note that the oscillator start–up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can prove very helpful
(see Table 4).
RECOMMENDED READING
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit–Definitions and
Method of Measurement”,
Proc. IEEE,
Vol. 57, No. 2, Feb.
1969.
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”,
Electro–Technology
, June 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”,
Electronic
Design
, May 1966.
D. Babin, “Designing Crystal Oscillators”,
Machine
Design
, March 7, 1985.
D. Babin, “Guidelines for Crystal Oscillator Design”,
Machine Design
, April 25, 1985.
R1*
C2C1
FREQUENCY
SYNTHESIZER
REF
out
REF
in
R
f
*May be needed in certain cases. See text.
Figure 19. Pierce Crystal Oscillator Circuit
Figure 20. Parasitic Capacitances of the Amplifier
and C
stray
C
in
C
out
C
a
REF
in
REF
out
C
stray
Figure 21. Equivalent Crystal Networks
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
2
1
2
121
R
S
L
S
C
S
R
e
X
e
C
O
Table 4. Partial List of Crystal Manufacturers
Motorola — Internet Address
http://motorola.com
(Search for resonators)
United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics
NOTE: Motorola cannot recommend one supplier over another and in no way suggests
that this is a complete listing of crystal manufacturers.
Page 19
MC145190•MC145191MOTOROLA
19
F(s) =
ASSUMING GAIN A IS VERY LARGE, THEN:
Z(s) =
ζ
=
ω
n
=
PHASE–LOCKED LOOP—LOW PASS FILTER DESIGN
(B)
A
C
R
2
C
VCO
(A)
φ
R
φ
V
R
1
R
1
R
2
K
φKVCO
NC
R
2
sC
ωn =
K
φKVCO
NCR
1
ζ
=
ωnR2C
2
R2sC + 1
R1sC
NOTE:
For (B), R1 is frequently split into two series resistors; each resistor is equal to R1 divided by 2. A capacitor CC is then placed from
the midpoint to ground to further filter the error pulses. The value of CC should be such that the corner frequency of this network does
not significantly affect ωn.
DEFINITIONS:
N = Total Division Ratio in Feedback Loop
Kφ (Phase Detector Gain) = I
PDout
/2π amps per radian for PD
out
Kφ (Phase Detector Gain) = VPD/2π volts per radian for φV and φ
R
K
VCO
(VCO Transfer Function) =
2π∆f
VCO
∆V
VCO
For a nominal design starting point, the user might consider a damping factor ζ≈0.7 and a natural loop frequency ωn ≈ (2πfR/50) where fR is
the frequency at the phase detector input. Larger ωn values result in faster loop lock times and, for similar sideband filtering, higher fR–related
VCO sidebands.
RECOMMENDED READING:
Gardner, Floyd M.,
Phaselock Techniques (second edition).
New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim,
Frequency Synthesizers: Theory and Design (second edition).
New York, Wiley–Interscience, 1980.
Blanchard, Alain,
Phase–Locked Loops: Application to Coherent Receiver Design.
New York, Wiley–Interscience, 1976.
Egan, William F.,
Frequency Synthesis by Phase Lock.
New York, Wiley–Interscience, 1981.
Rohde, Ulrich L.,
Digital PLL Frequency Synthesizers Theory and Design.
Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M.,
Design of Phase–Locked Loop Circuits, with Experiments.
Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold,
The PLL Synthesizer Cookbook.
Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H.,
Integrated Circuits Applications Handbook
, Chapter 17, pp. 538–586. New Y ork, John Wiley & Sons.
Fadrhons, Jan, “Design and Analyze PLLs on a Programmable Calculator,”
EDN
. March 5, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from
Electronic Design,
1987.
AN1253/D, An Improved PLL Design Method Without ωn and ζ, Motorola Semiconductor Products, Inc., 1995.
–
+
K
VCO
C
N
K
φ
1 + sRC
NOTE:
For ( A ), u s i n g Kφ in amps per radian with the filter’s impedance transfer function, Z(s), maintains units of volts per radian for the
detector/ filter combination. Additional sideband filtering can be accomplished by adding a capacitor C′ across R. The corner ωc = 1/RC′
should be chosen such that ωn is not significantly affected.
C
VCO
R
PD
out
radians per volt
Either loop filter (A) or (B) is frequently followed by additional sideband filtering to further attenuate fR–related VCO sidebands. This additional
filtering may be active or passive.
=
ωnRC
2
*The φR and φV outputs are fed to an external combiner/loop filter. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful
not to exceed the common mode input range of the op amp used in the combiner/loop filter.
Page 20
MC145190•MC145191 MOTOROLA
20
THRESHOLD
DETECTOR
LOW–PASS
FILTER
NC
1000 pF
UHF
VCO
INTEGRATOR
MCU
OPTIONAL LOOP
ERROR SIGNALS
(NOTE 1)
+5 V
GENERAL–PURPOSE
DIGITAL OUTPUT
+5 V
REF
out
REF
in
V
CC
V
DD
GND
LD
φ
R
φ
V
V
PD
PD
out
Rx
TEST 1
f
in
f
in
TEST 2
OUTPUT B
OUTPUT A
ENB
CLK
D
in
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
Q1
NC
+ V
UHF OUTPUT
BUFFER
NOTE 2
NOTES:
1. When used, the φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked
Loop — Low–Pass Filter Design page for additional information.
2. Transistor Q1 is required only if the standby feature is needed. Q1 permits the bipolar section of the device to
be shut down via use of the general–purpose digital pin, OUTPUT B. If the standby feature is not needed, tie
Pin 12 directly to the power supply.
3. For optimum performance, bypass the VCC, VDD, and VPD pins to GND with low–inductance capacitors.
4. The R counter is programmed for a divide value = REFin/fR. Typically, fR is the tuning resolution required for
the VCO. Also, the VCO frequency divided by fR = NT = N
× 64 + A; this determines the values (N, A) that must
be programmed into the N and A counters, respectively.
Figure 22. Example Application
CMOS
MCU
OUTPUT A
(DATA OUT)
ENB
CLKD
in
DEVICE #1
OUTPUT A
(DATA OUT)
ENB
CLKD
in
DEVICE #2
OPTIONAL
NOTE:See related Figures 24 through 26; these bit streams apply to the MC145190, MC145191, MC145200,
and MC145201.
Figure 23. Cascading Two Devices
Page 21
MC145190•MC145191MOTOROLA
21
1 2 7 8 9 10 15161718 23242526 31323334 3940
C REGISTER BITS OF DEVICE #2
IN FIGURE 23
C REGISTER BITS OF DEVICE #1
IN FIGURE 23
*At this point, the new bytes are transferred to the C registers of both devices and stored. No other registers are affected.
X
X X C7 C6 C0 X X X X X X C7 C6 C0
*
CLK
ENB
D
in
Figure 24. Accessing the C Registers
of Two Cascaded Devices
12 8910
15 16 17 23 24 25 31 32 33 39 40
A REGISTER BITS OF DEVICE #2
IN FIGURE 23
A REGISTER BITS OF DEVICE #1
IN FIGURE 23
X
X A23 A22 A16 A15 A8 A7 A0 A23 A16
46 47 48 55 56
A9 A8 A0
*At this point, the new bytes are transferred to the A registers of both devices and stored. Additionally, for both devices, the 13 LSBs in each of the first buffers of the R registers are
transferred to the respective R register’s second buffer. Thus, the R, N, and A counters can be presented new divide ratios at the same time. The first buffer of each R register is not affected.
Neither C register is affected.
*
CLK
ENB
D
in
Figure 25. Accessing the A Registers
of Two Cascaded Devices
Page 22
MC145190•MC145191 MOTOROLA
22
12 8910
15 16 17 23 24 25 31 32 33
R REGISTER BITS OF DEVICE #2
IN FIGURE 23
R REGISTER BITS OF DEVICE #1
IN FIGURE 23
X
X R15 R14 R8 R7 R0 X X R15
39 40 41 47 48
R8 R7
R0
NOTE 1 NOTE 2
NOTES APPLICABLE TO EACH DEVICE:
1. At this point, bits R13, R14, and R15 are stored and sent to the “OSC or 4-Stage Divider” block in the Block Diagram. Bits R0 through R12 are loaded into the first buffer in the double-
buffered section of the R register . Therefore, the R counter divide ratio is not altered yet and retains the previous ratio loaded. The C and A registers are not affected.
2. At this point, the bits R0 through R12 are transferred to the second buffer of the R register. The R counter begins dividing by the new ratio after completing the rest of the present count
cycle. CLK must be low during the ENB pulse, as shown. Also, see note of Figure 25 for an alternate method of loading the second buffer in the R register. The C and A registers
are not affected. The first buffer of the R register is not af fected.
CLK
ENB
D
in
Figure 26. Accessing the R Registers of Two Cascaded Devices
Page 23
MC145190•MC145191MOTOROLA
23
P ACKAGE DIMENSIONS
F SUFFIX
SOG (SMALL OUTLINE GULL–WING) PACKAGE
CASE 751J–02
0.10 (0.004)
SEATING
PLANE
-T-
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
G
J
K
L
M
S
0.494
0.201
—
0.014
0.007
0.022
0.002
0
°
0.291
1.27 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
12.55
5.10
—
0.35
0.18
0.55
0.05
0
°
7.40
12.80
5.40
2.00
0.45
0.23
0.85
0.20
7
°
8.20
0.504
0.213
0.079
0.018
0.009
0.033
0.008
7
°
0.323
0.050 BSC
-A-
-B-
1
10
1120
G
D
20 PL
C
M
S 10 PL
L
B0.13 (0.005)
M M
T
0.13 (0.005) B A
M
S S
K
J
DT SUFFIX
TSSOP (THIN SHRUNK SMALL OUTLINE PACKAGE)
CASE 948D–03
A
B
L
D
C
G
H
DIMAMIN MAX MIN MAX
INCHES
––– 6.60 ––– 0.260
MILLIMETERS
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.25 0.002 0.010
F 0.45 0.55 0.018 0.022
G 0.65 BSC 0.026 BSC
H 0.275 0.375 0.011 0.015
J 0.09 0.24 0.004 0.009
K 0.16 0.32 0.006 0.013
L 6.30 6.50 0.248 0.256
M 0 10 0 10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE –U–.
°°°°
F
M
K
K1
J
J1
A
A
J1 0.09 0.18 0.004 0.007
K1 0.16 0.26 0.006 0.010
0.100 (0.004)
SECTION A-A
PIN 1
IDENTIFICATION
-T-
-U-
0.200 (0.004)MT
20X REFK
20
1
10
11
SEATING
PLANE
Page 24
MC145190•MC145191 MOTOROLA
24
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/ Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,
P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 4–32–1 Nishi–Gotanda, Shagawa–ku, Tokyo, Japan. 03–5487–8488
Mfax: RMFAX0@email.sps.mot.com – TOUCHTONE 1–602–244–6609 ASIA/P ACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
Moto rola Fax Back System – US & Canada ONLY 1–800–774–1848 51 T ing Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
– http://sps.motorola.com/mfax/
HOME PAGE: http://motorola.com/sps/ CUSTOMER FOCUS CENTER: 1–800–521–6274
MC145190/D
◊
Loading...