Datasheet MC14517BDW, MC14517BCL, MC14517BCP Datasheet (Motorola)

MOTOROLA CMOS LOGIC DATA

403

MC14517B

    

The MC14517B dual 64–bit static shift register consists of two identical,
independent, 64–bit registers. Each register has separate clock and write
enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data
input is entered by clocking, regardless of the state of the write enable input.
An output is disabled (open circuited) when the write enable input is high.
During this time, data appearing at the data input as well as the 16–bit,
32–bit, and 48–bit taps may be entered into the device by application of a
clock pulse. This feature permits the register to be loaded with 64 bits in 16
clock periods, and also permits bus logic to be used. This device is useful in
time delay circuits, temporary memory storage circuits, and other serial shift
register applications.

• Diode Protection on All Inputs

• Fully Static Operation

• Output Transitions Occur on the Rising Edge of the Clock Pulse

• Exceedingly Slow Input Transition Rates May Be Applied to the Clock

Input

• 3–State Output at 64th–Bit Allows Use in Bus Logic Applications

• Shift Registers of any Length may be Fully Loaded with 16 Clock Pulses

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

MAXIMUM RATINGS (Voltages referenced to V

SS

)

Symbol

Parameter

Value

Unit

V

DD

DC Supply Voltage

– 0.5 to + 18.0

V

Vin, V

out

Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

V

Iin, I

out

Input or Output Current (DC or Transient),
per Pin

± 10

mA

P

D

Power Dissipation, per Package†

500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature (8–Second Soldering)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

FUNCTIONAL TRUTH TABLE (X = Don’t Care)

Clock

Write

Enable

Data 16–Bit Tap 32–Bit Tap 48–Bit Tap 64–Bit Tap

0 0 X Content of 16–Bit

Displayed

Content of 32–Bit

Displayed

Content of 48–Bit

Displayed

Content of 64–Bit

Displayed
0 1 X High Impedance High Impedance High Impedance High Impedance
1 0 X Content of 16–Bit

Displayed

Content of 32–Bit

Displayed

Content of 48–Bit

Displayed

Content of 64–Bit

Displayed
1 1 X High Impedance High Impedance High Impedance High Impedance

0 Data entered

into 1st Bit

Content of 16–Bit

Displayed

Content of 32–Bit

Displayed

Content of 48–Bit

Displayed

Content of 64–Bit

Displayed

1 Data entered

into 1st Bit

Data at tap

entered into 17–Bit

Data at tap

entered into 33–Bit

Data at tap

entered into 49–Bit

High Impedance

0 X Content of 16–Bit

Displayed

Content of 32–Bit

Displayed

Content of 48–Bit

Displayed

Content of 64–Bit

Displayed

1 X High Impedance High Impedance High Impedance High Impedance



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3
1/94



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBDW SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

DW SUFFIX

SOIC

CASE 751G

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

C

B

WE

B

Q48

B

Q16

B

V

DD

D

B

Q32

B

Q64

B

C

A

WE

A

Q48

A

Q16

A

V

SS

Q32

A

Q64

A

D

A

MOTOROLA CMOS LOGIC DATAMC14517B

404

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C 25_C 125_C

Characteristic

Symbol

V

DD

Vdc

Min Max Min Typ # Max Min Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

V

OL

5.0
10
15

—
—
—

0.05

0.05

0.05

—
—
—

0
0
0

0.05

0.05

0.05

—
—
—

0.05

0.05

0.05

Vdc

“1” Level

Vin = 0 or V

DD

V

OH

5.0
10
15

4.95

9.95

14.95

—
—
—

4.95

9.95

14.95

5.0
10
15

—
—
—

4.95

9.95

14.95

—
—
—

Vdc

Input Voltage

“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)

V

IL

5.0
10
15

—
—
—

1.5

3.0

4.0

—
—
—

2.25

4.50

6.75

1.5

3.0

4.0

—
—
—

1.5

3.0

4.0

Vdc

“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

V

IH

5.0
10
15

3.5

7.0
11

—
—
—

3.5

7.0
11

2.75

5.50

8.25

—
—
—

3.5

7.0
11

—
—
—

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)

I

OH

5.0

5.0
10
15

– 3.0

– 0.64

– 1.6
– 4.2

—
—
—
—

– 2.4

– 0.51

– 1.3
– 3.4

– 4.2
– 0.88
– 2.25

– 8.8

—
—
—
—

– 1.7

– 0.36

– 0.9
– 2.4

—
—
—
—

mAdc

(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

I

OL

5.0
10
15

0.64

1.6

4.2

—
—
—

0.51

1.3

3.4

0.88

2.25

8.8

—
—
—

0.36

0.9

2.4

—
—
—

mAdc

Input Current I

in

15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance

(Vin = 0)

C

in

— — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package)

I

DD

5.0
10
15

—
—
—

5.0
10
20

—
—
—

0.005

0.010

0.015

5.0
10
20

—
—
—

150
300
600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)

I

T

5.0
10
15

IT = (4.2 µA/kHz) f + I

DD

IT = (8.8 µA/kHz) f + I

DD

IT = (13.7 µA/kHz) f + I

DD

µAdc

Three–State Leakage Current I

TL

15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**āThe formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATA

405

MC14517B

SWITCHING CHARACTERISTICS* (C

L

= 50 pF, TA = 25_C)

Characteristic

Symbol V

DD

Min Typ # Max Unit

Output Rise and Fall Time

t

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

TLH

, t

THL

= (0.65 ns/pF) CL + 9.5 ns

t

TLH

, t

THL

5.0
10
15

—
—
—

100

50
40

200
100

80

ns

Propagation Delay Time

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 390 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 177 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 115 ns

t

PLH

, t

PHL

5.0
10
15

—
—
—

475
210
140

770
300
215

ns

Clock Pulse Width t

WH

5.0
10
15

330
125
100

170

75
60

—
—
—

ns

Clock Pulse Frequency f

cl

5.0
10
15

—
—
—

3.0

6.7

8.3

1.5

4.0

5.3

MHz

Clock Pulse Rise and Fall Time t

TLH

, t

THL

5.0
10
15

**See Note

—

Data to Clock Setup Time t

su

5.0
10
15

0
10
15

– 40
– 15

0

—
—
—

ns

Data to Clock Hold Time t

h

5.0
10
15

150

75
35

75
25
10

—
—
—

ns

Write Enable to Clock Setup Time t

su

5.0
10
15

400
200
110

170

65
50

—
—
—

ns

Write Enable to Clock Release Time t

rel

5.0
10
15

380
180
100

160

55
40

—
—
—

ns

*The formulas given are for the typical characteristics only at 25_C.

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

**āWhen shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall

time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.

Figure 1. Power Dissipation Test Circuit and Waveform

C

L

C

L

C

L

C

L

CLCLCLC

L

V

DD

Q16 Q32 Q48 Q64

Q16 Q32 Q48 Q64

V

DD

V

DD

V

SS

V

SS

D
C
WE

D
C
WE

V

SS

I

D

D
C

50

µ

F

REPETITIVE WAVEFORM

C

D

f

o

(f = 1/2 fo)

MOTOROLA CMOS LOGIC DATAMC14517B

406

Figure 2. Typical Output Source Current

Characteristics Test Circuit

Figure 3. Typical Output Sink Current

Characteristics Test Circuit

EXTERNAL

POWER
SUPPLY

I

OH

V

out

= V

OH

VDD = V

GS

V

SS

D
C

WE

D
C

WE

Q16 Q32 Q48 Q64

Q16 Q32 Q48 Q64

(Output being tested should be in the high–logic state)

EXTERNAL

POWER
SUPPLY

I

OL

V

out

= V

OL

VDD = V

GS

V

SS

D
C

WE

D
C

WE

Q16 Q32 Q48 Q64

Q16 Q32 Q48 Q64

(Output being tested should be in the low–logic state)

Figure 4. AC Test Waveforms

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

50%

1 22 16 17 18 19 33

90%

10%

t

su

16–BIT OUTPUT 1 (15)
17–BIT INPUT

32–BIT OUTPUT 6 (10)
33–BIT INPUT

48–BIT OUTPUT 2 (14)
49–BIT INPUT

64–BIT OUTPUT 5 (11)

t

h1

t

h1

t

h1

t

h1

t

WH

t

WL

t

THL

t

THL

t

THL

t

THL

V

OL

V

OL

V

OL

V

OH

V

OH

V

OH

50%

90%

10%

20 ns

t

rel

t

PHL

t

PHL

t

PHL

t

PHL

t

PLH

90%

10%

t

TLH

t

TLH

t

TLH

t

TLH

t

h0

t

h0

t

h0

t

h0

t

su0

t

su0

t

su0

50%

20 ns

20 ns

20 ns

V

DD

V

DD

V

DD

t

su0

t

su1

t

su1

t

su1

t

su1

DATA IN 7 (9)

WRITE 3 (13)

CLOCK 4 (12)

PIN NO’S

90%

10%

50%

t

PLH

t

PLH

t

PLH

EXPANDED BLOCK DIAGRAM (1/2 OF DEVICE SHOWN)

WRITE ENABLE = 0, 16–BIT OUTPUT
WRITE ENABLE = 1, 17–BIT INPUT

CLOCK

DATA

WRITE

ENABLE

32–BIT OUTPUT
33–BIT INPUT

48–BIT OUTPUT
49–BIT INPUT

64–BIT OUTPUT
HIGH IMPEDANCE

D
C
3–STATE

Q

32

D
C
WE

Q

33

D
C
3–STATE

Q

48

D
C
WE

Q

49

D
C
3–STATE

Q

64

D
C

Q

1

D
C

Q

2

D
C
3–STATE

Q

16

D
C
WE

Q

17

MOTOROLA CMOS LOGIC DATA

407

MC14517B

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

1 8

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

–A–

–B–

–T–

F

E

G

N

K

C

SEATING
PLANE

16 PLD

S

A

M

0.25 (0.010) T

16 PLJ

S

B

M

0.25 (0.010) T

M

L

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATAMC14517B

408

OUTLINE DIMENSIONS

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751G–02

ISSUE A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 10.15 10.45 0.400 0.411
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029

M

B

M

0.010 (0.25)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.

–A–

–B– P8X

G14X

D16X

SEATING
PLANE

–T–

S

A

M

0.010 (0.25) B

S

T

16 9

81

F

J

R

X 45

_

_ _ _ _

M

C

K

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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MC14517B/D

*MC14517B/D*

◊