Datasheet MC14516BCP, MC14516BD, MC14516BDR2, MC14516BF, MC14516BFEL Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14516B/D

MC14516B

Binary Up/Down Counter

The MC14516B synchronous up/down binary counter is
constructed with MOS P–channel and N–channel enhancement mode
devices in a monolithic structure.

This counter can be preset by applying the desired value, in binary,
to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset
Enable (PE) high. The direction of counting is controlled by applying
a high (for up counting) or a low (for down counting) to the
UP/DOWN input. The state of the counter changes on the positive
transition of the clock input.

Cascading can be accomplished by connecting the Carry Out

to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high
to the reset (R) pin.

This CMOS counter finds primary use in up/down and difference
counting. Other applications include: (1) Frequency synthesizer
applications where low power dissipation and/or high noise immunity
is desired, (2) Analog–to–digital and digital–to–analog conversions,
and (3) Magnitude and sign generation.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Internally Synchronous for High Speed

• Logic Edge–Clocked Design — Count Occurs on Positive Going

Edge of Clock

• Single Pin Reset

• Asynchronous Preset Enable Operation

• Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky Load Over the Rated Temperature Range

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note 3.)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

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A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14516BCP PDIP–16 2000/Box
MC14516BD SOIC–16 48/Rail
MC14516BDR2 SOIC–16 2500/Tape & Reel

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

MARKING

DIAGRAMS

1

16

PDIP–16

P SUFFIX

CASE 648

MC14516BCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

1

16

14516B

AWLYWW

SOEIAJ–16

F SUFFIX

CASE 966

1

16

MC14516B

AWLYWW

MC14516BF SOEIAJ–16 See Note 1.
MC14516BFEL SOEIAJ–16 See Note 1.

This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap­plications of any voltage higher than maximum rated
voltages to this high–impedance circuit. For proper
operation, V

in

and V

out

should be constrained to the

range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either V

SS

or VDD). Unused out-

puts must be left open.

MC14516B

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2

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

P1

P2

Q2

C

V

DD

R

U/D

Q1

P0

P3

Q3

PE

V

SS

CARRY OUT

Q0

CARRY IN

BLOCK DIAGRAM

VDD = PIN 16

VSS = PIN 8

6

11

14

2

7

Q0

Q1

Q2

Q3

CARRY

OUT

PE
CARRY IN
RESET
UP/DOWN
CLOCK
P0
P1
P2
P3

1
5

9
10
15

4
12
13

3

TRUTH TABLE

Carry In Up/Down

Preset
Enable

Reset Clock Action

1 X 0 0 X No Count
0 1 0 0 Count Up
0 0 0 0 Count Down
X X 1 0 X Preset
X X X 1 X Reset

X = Don’t Care
NOTE: When counting up, the Carry Out

signal is normally high and is low only

when Q0 through Q3 are high and Carry In

is low. When counting down,

Carry Out

is low only when Q0 through Q3 and Carry In are low.

MC14516B

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C 25_C 125_C

Characteristic Symbol

V

DD

Vdc

Min Max Min Typ

(4.)

Max Min Max

Unit

Output Voltage “0” Level

V

in

= VDD or 0

V

OL

5.0
10
15

—
—
—

0.05

0.05

0.05

—
—
—

0
0
0

0.05

0.05

0.05

—
—
—

0.05

0.05

0.05

Vdc

“1” Level

V

in

= 0 or V

DD

V

OH

5.0
10
15

4.95

9.95

14.95

—
—
—

4.95

9.95

14.95

5.0
10
15

—
—
—

4.95

9.95

14.95

—
—
—

Vdc

Input Voltage “0” Level

(V

O

= 4.5 or 0.5 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

V

IL

5.0
10
15

—
—
—

1.5

3.0

4.0

—
—
—

2.25

4.50

6.75

1.5

3.0

4.0

—
—
—

1.5

3.0

4.0

Vdc

“1” Level

(V

O

= 0.5 or 4.5 Vdc)

(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

V

IH

5.0
10
15

3.5

7.0
11

—
—
—

3.5

7.0
11

2.75

5.50

8.25

—
—
—

3.5

7.0
11

—
—
—

Vdc

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

I

OH

5.0

5.0
10
15

– 3.0

– 0.64

– 1.6
– 4.2

—
—
—
—

– 2.4

– 0.51

– 1.3
– 3.4

– 4.2
– 0.88
– 2.25

– 8.8

—
—
—
—

– 1.7

– 0.36

– 0.9
– 2.4

—
—
—
—

mAdc

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

I

OL

5.0
10
15

0.64

1.6

4.2

—
—
—

0.51

1.3

3.4

0.88

2.25

8.8

—
—
—

0.36

0.9

2.4

—
—
—

mAdc

Input Current I

in

15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance

(V

in

= 0)

C

in

— — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package)

I

DD

5.0
10
15

—
—
—

5.0
10
20

—
—
—

0.005

0.010

0.015

5.0
10
20

—
—
—

150
300
600

µAdc

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

L

= 50 pF on all outputs, all

buffers switching)

I

T

5.0
10
15

IT = (0.58 µA/kHz) f + I

DD

IT = (1.20 µA/kHz) f + I

DD

IT = (1.70 µA/kHz) f + I

DD

µAdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MC14516B

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4

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, T

A

= 25_C)

All Types

Characteristic Symbol V

DD

Min Typ

(8.)

Max

Unit

Output Rise and Fall Time

t

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

t

TLH

,

t

THL

5.0
10
15

—
—
—

100

50
40

200
100

80

ns

Propagation Delay Time

Clock to Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

t

PLH

,

t

PHL

5.0
10
15

—
—
—

315
130
100

630
260
200

ns

Clock to Carry Out

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

t

PLH

,

t

PHL

5.0
10
15

—
—
—

315
130
100

630
260
200

ns

Carry In to Carry Out

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

t

PLH

,

t

PHL

5.0
10
15

—
—
—

180

80
60

360
160
120

ns

Preset or Reset to Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

t

PLH

,

t

PHL

5.0
10
15

—
—
—

315
130
100

630
360
200

ns

Preset or Reset to Carry Out

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 465 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 192 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 125 ns

t

PLH

,

t

PHL

5.0
10
15

—
—
—

550
225
150

1100

450
300

ns

Reset Pulse Width t

w

5.0
10
15

380
200
160

190
100

80

—
—
—

ns

Clock Pulse Width t

WH

5.0
10
15

350
170
140

200
100

75

—
—
—

ns

Clock Pulse Frequency f

cl

5.0
10
15

—
—
—

3.0

6.0

8.0

1.5

3.0

4.0

MHz

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.

MC14516B

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5

SWITCHING CHARACTERISTICS

(9.)

(C

L

= 50 pF, T

A

= 25_C) (continued)

All Types

Characteristic Symbol V

DD

Min Typ

(10.)

Max

Unit

Preset or Reset Removal Time

The Preset or Reset signal must be low prior to a
positive–going transition of the clock.

t

rem

5.0
10
15

650
230
180

325
115

90

—
—

ns

Clock Rise and Fall Time t

TLH

,

t

THL

5.0
10
15

—
—
—

—
—
—

15

5
4

µs

Setup Time

Carry In

to Clock

t

su

5.0
10
15

260
120
100

130

60
50

—
—
—

ns

Hold Time

Clock to Carry In

t

h

5.0
10
15

0
20
20

– 60
– 20

0

—
—
—

ns

Setup Time

Up/Down to Clock

t

su

5.0
10
15

500
200
150

250
100

75

—
—
—

ns

Hold Time

Clock to Up/Down

t

h

5.0
10
15

– 70
– 10

0

– 160

– 60
– 40

—
—
—

ns

Setup Time

Pn to PE

t

su

5.0
10
15

– 40
– 30
– 25

– 120

– 70
– 50

—
—
—

ns

Hold Time

PE to Pn

t

h

5.0
10
15

480
420
420

240
210
210

—
—
—

ns

Preset Enable Pulse Width t

WH

5.0
10
15

200
100

80

100

50
40

—
—
—

ns

9. The formulas given are for the typical characteristics only at 25_C.

10.Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’ s potential performance.

MC14516B

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6

Figure 1. Power Dissipation Test Circuit and Waveform

PULSE

GENERATOR

C

L

C

L

C

L

C

L

V

DD

VARIABLE

WIDTH

V

DD

V

SS

CLOCK

I

D

0.01 µF
CERAMIC

20 ns

20 ns

10%

50%

90%

500 pF

Q0

Q1

Q2

Q3

CARRY

OUT

PE
CARRY IN

R
UP/DOWN
CLOCK
P0
P1
P2

P3

C

L

LOGIC DIAGRAM

PE
C
T

Q

Q

P

PE
C
TQQ

P

PE
C
TQQ

P

PE
C
TQQ

P

Q2

14

P2
13

Q1

11

P33Q3

2

P04Q0

6

P1
12

CARRY OUT

CLOCK

PRESET
ENABLE

RESET

CARRY IN

UP/DOWN

9

1

15

7

5

10

MC14516B

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7

TOGGLE FLIP–FLOP

PE
C
T

Q

Q

P

PARALLEL IN

FLIP–FLOP FUNCTIONAL TRUTH TABLE

Preset

Enable

Clock T Q

n+1

1 X X Parallel In
0 0 Q

n

0 1 Q

n

0 X Q

n

X = Don’t Care

Figure 2. Switching Time Waveforms

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

OL

V

OH

RESET

PRESET ENABLE

CARRY IN

OR

UP/DOWN

CLOCK

Q

0

OR CARRY OUT

t

rem

t

su

t

rem

t

h

t

TLH

t

PLH

t

PHL

t

PLH

t

THL

50%

50%

90%

10%

50%

90%

10%

CARRY OUT

ONLY

t

w(H)

t

w(H)

t

w

1

f

cl

PIN DESCRIPTIONS

INPUTS

P0, P1, P2, P3, Preset Inputs (Pins 4, 12, 13, 3) — Data

on these inputs is loaded into the counter when PE is taken
high.

Carry In, (Pin 5) — This active–low input is used when

Cascading stages. Carry In

is usually connected to Carry Out

of the previous stage. While high, Clock is inhibited.

Clock, (Pin 15) — Binary data is incremented or

decremented, depending on the direction of count, on the
positive transition of this input.

OUTPUTS

Q0, Q1, Q2, Q3, Binary outputs (Pins 6, 11, 14, 2) —

Binary data is present on these outputs with Q0
corresponding to the least significant bit.

Carry Out,

(Pin 7) — Used when cascading stages, Carry

Out is usually connected to Carry In of the next stage. This
synchronous output is active low and may also be used to
indicate terminal count.

CONTROLS

PE, Preset Enable, (Pin 1) — Asynchronously loads data

on the Preset Inputs. This pin is active high and inhibits the
clock when high.

R, Reset, (Pin 9) — Asynchronously resets the Q out–

puts to a low state. This pin is active high and inhibits the
clock when high.

Up/Down, (Pin 10) — Controls the direction of count,

high for up count, low for down count.

SUPPLY PINS

VSS, Negative Supply Voltage, (Pin 8) — This pin is

usually connected to ground.

V

DD

, Positive Supply Voltage, (Pin 16) — This pin is

connected to a positive supply voltage ranging from 3.0
volts to 18.0 volts.

MC14516B

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8

Figure 3. Presettable Cascaded 8–Bit Up/Down Counter

NOTE: The Least Significant Digit (L.S.D.) counts from a preset value once Preset Enable (PE) goes low. The Most Significant

Digit (M.S.D.) is disabled while C

in

is high. When the count of the L.S.D. reaches 0 (count down mode) or reaches 15 (count

up mode), C

out

goes low for one complete clock cycle, thus allowing the next counter to decrement/increment one count.

(See Timing Diagram) The L.S.D. now counts through another cycle (15 clock pulses) and the above cycle is repeated.

L.S.D.

MC14516B

C

out

Q0 Q1 Q2 Q3

P0 P1 P2 P3

PE

R

U/D

CLOCK

C

in

M.S.D.

MC14516B

C

out

Q0 Q1 Q2 Q3

P0 P1 P2 P3

PE

R

U/D

CLOCK

C

in

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

TERMINAL COUNT
INDICATOR

P0 P1 P2 P3 P4 P5 P6 P7

THUMBWHEEL SWITCHES

(OPEN FOR “0”)

+V

DD

+V

DD

+V

DD

OPEN = COUNT

CLOCK

RESET

RESISTORS = 10 k

W

0 = COUNT
1 = PRESET

1 = UP
0 = DOWN

PRESET
ENABLE

MC14516B

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9

TIMING DIAGRAM FOR THE PRESETT ABLE CASCADED 8–BIT UP/DOWN COUNTER

CLOCK

UP/DOWN

CARRY IN

(MSD)

PE

P7

P6

P5

P4

P3

P2

P1

P0

CARRY OUT

(MSD)

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

CARRY OUT

(LSD)

RESET

COUNT

PRESET ENABLE

UP COUNT DOWN COUNT UP COUNT

DOWN

COUNT

PRESET

ENABLE

RESET

13 14 15 16 17 18 18 17 16 15 14 13

19 251 252 253 254 255 0 1 2 2 13 012

UP COUNT

MC14516B

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10

Figure 4. Programmable Cascaded Frequency Divider

NOTE: The programmable frequency divider can be set by applying the desired divide ratio, in binary, to the preset inputs. For example,

the maximum divide ratio of 255 may be obtained by applying a 11 1 1 1 1 1 1 to the preset inputs P0 to P7. For this divide operation,
both counters should be configured in the count down mode. The divide ratio of zero is an undefined state and should be avoided.

BUFFER

f

out

M.S.D.

MC14516B

L.S.D.

MC14516B

THUMBWHEEL SWITCHES

(OPEN FOR “0”)

+V

DD

+V

DD

C

out

+V

DD

OPEN = COUNT

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Q0 Q1 Q2 Q3

P0 P1 P2 P3

P0 P1 P2 P3

PE

R

U/D

CLOCK

C

in

C

out

Q0 Q1 Q2 Q3

P0 P1 P2 P3

PE

R

U/D

CLOCK

C

in

P4 P5 P6 P7

CLOCK (f

in

)

RESET

RESISTORS = 10 k

W

f

out

=

f

in

n

MC14516B

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11

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC

J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009

M 0 7 0 7

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

MC14516B

http://onsemi.com

12

P ACKAGE DIMENSIONS

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035

––– 0.78 ––– 0.031

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005)

0.10 (0.004)

1

16 9

8

D

Z

E

A

b
c
D
E
e

L

M

Z

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

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