Page 1
MC145151–2 through MC145158–2MOTOROLA
1
! !"
!
CMOS
The devices described in this document are typically used as low–power,
phase–locked loop frequency synthesizers. When combined with an external
low–pass filter and voltage–controlled oscillator, these devices can provide all
the remaining functions for a PLL frequency synthesizer operating up to the
device’s frequency limit. For higher VCO frequency operation, a down mixer or
a prescaler can be used between the VCO and the synthesizer IC.
These frequency synthesizer chips can be found in the following and other
applications:
CATV TV Tuning
AM/FM Radios Scanning Receivers
Two–Way Radios Amateur Radio
÷
R
OSC
CONTROL LOGIC
÷
N
÷
A
φ
÷
P/P + 1
VCO
OUTPUT
FREQUENCY
CONTENTS
Page
DEVICE DETAIL SHEETS
MC145151–2 Parallel–Input, Single–Modulus 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC145152–2 Parallel–Input, Dual–Modulus 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC145155–2 Serial–Input, Single–Modulus 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC145156–2 Serial–Input, Dual–Modulus 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC145157–2 Serial–Input, Single–Modulus 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC145158–2 Serial–Input, Dual–Modulus 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FAMILY CHARACTERISTICS
Maximum Ratings 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristics 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Electrical Characteristics 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Requirements 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Characteristics 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Detector/Lock Detector Output Waveforms 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DESIGN CONSIDERATIONS
Phase–Locked Loop — Low–Pass Filter Design 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Oscillator Considerations 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dual–Modulus Prescaling 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Order this document
by MC145151–2/D
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 1
8/95
Page 2
MC145151–2 through MC145158–2 MOTOROLA
2
Interfaces with Single–Modulus Prescalers
The MC145151–2 is programmed by 14 parallel–input data lines for the
N counter and three input lines for the R counter. The device features consist of
a reference oscillator, selectable–reference divider, digital–phase detector, and
14–bit programmable divide–by–N counter.
The MC145151–2 is an improved–performance drop–in replacement for the
MC145151–1. The power consumption has decreased and ESD and latch–up
performance have improved.
• Operating Temperature Range: – 40 to 85°C
• Low Power Consumption Through Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• On– or Off–Chip Reference Oscillator Operation
• Lock Detect Signal
• ÷ N Counter Output Available
• Single Modulus/Parallel Programming
• 8 User–Selectable ÷ R Values: 8, 128, 256, 512, 1024, 2048, 2410, 8192
• ÷ N Range = 3 to 16383
• “Linearized” Digital Phase Detector Enhances Transfer Function Linearity
• Two Error Signal Options: Single–Ended (Three–State) or Double–Ended
• Chip Complexity: 8000 FETs or 2000 Equivalent Gates
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 710
DW SUFFIX
SOG PACKAGE
CASE 751F
ORDERING INFORMATION
MC145151P2 Plastic DIP
MC145151DW2 SOG Package
5
4
3
2
1
10
9
8
7
6
11
12
13
14
20
21
22
23
24
25
26
19
27
28
18
17
16
15
RA2
PD
out
V
DD
V
SS
f
in
N0
φ
R
RA0
N3
N2
N1
RA1
φ
V
f
V
N10
N11
OSC
out
OSC
in
LD
N5
N6
N7
N4
N9
N12
N13
N8
T/R
PIN ASSIGNMENT
1
28
1
28
Motorola, Inc. 1995
REV 1
8/95
Page 3
MC145151–2 through MC145158–2MOTOROLA
3
14 x 8 ROM REFERENCE DECODER
14–BIT
÷
N COUNTER
φ
V
MC145151–2 BLOCK DIAGRAM
φ
R
14–BIT
÷
R COUNTER
TRANSMIT OFFSET ADDER
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT
LD
PD
out
RA2
f
in
V
DD
OSC
in
OSC
out
T/R
14
14
f
V
N13 N11 N9 N7 N6 N4 N2 N0
NOTE: N0 – N13 inputs and inputs RA0, RA1, and RA2 have pull–up resistors that are not shown.
RA0
RA1
PIN DESCRIPTIONS
INPUT PINS
f
in
Frequency Input (Pin 1)
Input to the ÷
N portion of the synthesizer. f
in
is typically
derived from loop VCO and is ac coupled into the device. For
larger amplitude signals (standard CMOS logic levels) dc
coupling may be used.
RA0 – RA2
Reference Address Inputs (Pins 5, 6, 7)
These three inputs establish a code defining one of eight
possible divide v alues for the total r eference divider, as
defined by the table below.
Pull–up resistors ensure that inputs left open remain at a
logic 1 and require only a SPST switch to alter data to the
zero state.
Reference Address Code
Total
RA2 RA1 RA0
Divide
Value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
128
256
512
1024
2048
2410
8192
N0 – N11
N Counter Programming Inputs (Pins 11 – 20, 22 – 25)
These inputs provide the data that is preset into the ÷
N
counter when it reaches the count of zero. N0 is the least significant and N13 is the most significant. Pull–up resistors en-
sure that inputs left open remain at a logic 1 and require only
an SPST switch to alter data to the zero state.
T/R
Transmit/Receive Offset Adder Input (Pin 21)
This input controls the offset added to the data provided at
the N inputs. This is normally used for offsetting the VCO
frequency by an amount equal to the IF frequency of the
transceiver. This offset is fixed at 856 when T/R is low and
gives no offset when T/R is high. A pull–up resistor ensures
that no connection will appear as a logic 1 causing no offset
addition.
OSCin, OSC
out
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on–chip reference oscillator when connected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSCin to ground and OSC
out
to ground.
OSCin may also serve as the input for an externally–generated reference signal. This signal is typically ac coupled to
OSCin, but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC
out
.
OUTPUT PINS
PD
out
Phase Detector A Output (Pin 4)
Three–state output of phase detector for use as loop–error
signal. Double–ended outputs are also available for this purpose (see φV and φR).
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High–Imped-
ance State
Page 4
MC145151–2 through MC145158–2 MOTOROLA
4
φR, φ
V
Phase Detector B Outputs (Pins 8, 9)
These phase detector outputs can be combined externally
for a loop–error signal. A single–ended output is also available for this purpose (see PD
out
).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by φR pulsing low.
φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both
φV and φR remain high except for a small minimum time
period when both pulse low in phase.
f
V
N Counter Output (Pin 10)
This is the buffered output of the ÷ N counter that is inter-
nally connected to the phase detector input. With this output
available, the ÷ N counter can be used independently.
LD
Lock Detector Output (Pin 28)
Essentially a high level when loop is locked (fR, fV of same
phase and frequency). Pulses low when loop is out of lock.
POWER SUPPLY
V
DD
Positive Power Supply (Pin 3)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.
V
SS
Negative Power Supply (Pin 2)
The most negative supply potential. This pin is usually
ground.
TYPICAL APPLICATIONS
Figure 1. 5 MHz to 5.5 MHz Local Oscillator Channel Spacing = 1 kHz
0 1 1 1 0 0 0 1 0 0 0 = 5 MHz
1 0 1 0 1 1 1 1 1 0 0 = 5.5 MHz
5 – 5.5 MHz
VOLTAGE
CONTROLLED
OSCILLATOR
NCNC
PD
out
RA0RA1RA2
N13 N0N1N2N3N4N5N6N7N8N9N10N11N12
MC145151–2
f
in
OSC
out
OSC
in
2.048 MHz
Figure 2. Synthesizer for Land Mobile Radio UHF Bands
NOTES:
1. fR = 4.1667 kHz; ÷ R = 2410; 21.4 MHz low side injection during receive.
2. Frequency values shown are for the 440 – 470 MHz band. Similar implementation applies to the 406 – 440 MHz band.
For 470 – 512 MHz, consider reference oscillator frequency X9 for mixer injection signal (90.3750 MHz).
60.2500 MHz
“0”“1”“1”
CHOICE OF
DETECTOR
ERROR
SIGNALS
LOCK DETECT SIGNAL
T: 13.0833 – 18.0833 MHz
R: 9.5167 – 14.5167 MHz
T: 73.3333 – 78.3333 MHz
R: 69.7667 – 74.7667 MHz
X6VCO
LOOP
FILTER
DOWN
MIXER
X6
T/R
V
SS
V
DD
CHANNEL PROGRAMMING
÷
N = 2284 TO 3484
TRANSMIT
(ADDS 856 TO
÷
N VALUE)
RECEIVE
REF. OSC.
10.0417 MHz
(ON–CHIP OSC.
OPTIONAL)
“1”“0”“0”
f
V
LDRA0RA1RA2
OSC
in
OSC
out
MC145151–2
+ V
TRANSMIT: 440.0 – 470.0 MHz
RECEIVE: 418.6 – 448.6 MHz
(25 kHz STEPS)
PD
out
φ
R
f
V
f
in
MC145151–2 Data Sheet Continued on Page 23
Page 5
MC145151–2 through MC145158–2MOTOROLA
5
Interfaces with Dual–Modulus Prescalers
The MC145152–2 is programmed by sixteen parallel inputs for the N and A
counters and three input lines for the R counter. The device features consist of
a reference oscillator, selectable–reference divider, two–output phase detector ,
10–bit p rogrammable divide–by–N counter, and 6–bit p rogrammable ÷ A
counter.
The MC145152–2 is an improved–performance drop–in replacement for the
MC145152–1. Power consumption has decreased and ESD and latch–up
performance have improved.
• Operating Temperature Range: – 40 to 85°C
• Low Power Consumption Through Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• On– or Off–Chip Reference Oscillator Operation
• Lock Detect Signal
• Dual Modulus/Parallel Programming
• 8 User–Selectable ÷ R Values: 8, 64, 128, 256, 512, 1024, 1160, 2048
• ÷ N Range = 3 to 1023, ÷ A Range = 0 to 63
• Chip Complexity: 8000 FETs or 2000 Equivalent Gates
• See Application Note AN980
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 710
DW SUFFIX
SOG PACKAGE
CASE 751F
ORDERING INFORMATION
MC145152P2 Plastic DIP
MC145152DW2 SOG Package
5
4
3
2
1
10
9
8
7
6
11
12
13
14
20
21
22
23
24
25
26
19
27
28
18
17
16
15
φ
R
RA0
V
DD
V
SS
f
in
N0
φ
V
RA1
N3
N2
N1
RA2
MC
A5
A3
A4
OSC
out
OSC
in
LD
N5
N6
N7
N4
N9
A2
A0
N8
A1
PIN ASSIGNMENT
1
28
1
28
Motorola, Inc. 1995
REV 1
8/95
Page 6
MC145151–2 through MC145158–2 MOTOROLA
6
12 x 8 ROM REFERENCE DECODER
φ
V
MC145152–2 BLOCK DIAGRAM
φ
R
12–BIT
÷
R COUNTER
PHASE
DETECTOR
LOCK
DETECT
LD
f
in
OSC
in
OSC
out
12
N0 N2 N4 N5 N7 N9
NOTE: N0 – N9, A0 – A5, and RA0 – RA2 have pull–up resistors that are not shown.
10–BIT
÷
N COUNTER
CONTROL
LOGIC
MC
6–BIT
÷
A COUNTER
A5 A3 A2
A0
RA2
RA0
RA1
PIN DESCRIPTIONS
INPUT PINS
f
in
Frequency Input (Pin 1)
Input to the positive edge triggered ÷ N and ÷ A counters.
fin is typically derived from a dual–modulus prescaler and is
ac coupled i nto the device. For larger amplitude signals
(standard CMOS logic levels) dc coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (Pins 4, 5, 6)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider. The
total reference divide values are as follows:
Reference Address Code
Total
RA2 RA1 RA0
Divide
Value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
64
128
256
512
1024
1160
2048
N0 – N9
N Counter Programming Inputs (Pins 11 – 20)
The N inputs provide the data that is preset into the ÷ N
counter when it reaches the count of 0. N0 is the least significant digit and N9 is the most significant. Pull–up resistors ensure that inputs left open remain at a logic 1 and require only
a SPST switch to alter data to the zero state.
A0 – A5
A Counter Programming Inputs
(Pins 23, 21, 22, 24, 25, 10)
The A inputs define the number of clock cycles of fin that
require a l ogic 0 on the MC output (see Dual–Modulus
Prescaling section). The A inputs all have internal pull–up
resistors that ensure that inputs left open will remain at a
logic 1.
OSCin, OSC
out
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on–chip reference oscillator when connected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSCin to ground and OSC
out
to ground.
OSCin may also serve as the input for an externally–generated reference signal. This signal is typically ac coupled to
OSCin, but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC
out
.
OUTPUT PINS
φR, φ
V
Phase Detector B Outputs (Pins 7, 8)
These phase detector outputs can be combined externally
for a loop–error signal.
If the frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by φR pulsing low.
φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both
φV and φR remain high except for a small minimum time
period when both pulse low in phase.
MC
Dual–Modulus Prescale Control Output (Pin 9)
Signal generated by the on–chip control logic circuitry for
controlling an external dual–modulus prescaler. The MC
level will be low at the beginning of a count cycle and will
remain low until the ÷ A counter has counted down from its
programmed value. At this time, MC goes high and remains
high until the ÷ N counter has counted the rest of the way
down from its programmed value (N – A additional counts
since both ÷ N and ÷ A are counting down during the first
Page 7
MC145151–2 through MC145158–2MOTOROLA
7
portion of the cycle). MC is then set back low, the counters
preset to their respective programmed values, and the above
sequence repeated. This provides for a total programmable
divide value (NT) =
N• P+A where P and P + 1 represent the
dual–modulus prescaler divide values respectively for high
and low MC levels, N the number programmed into the ÷ N
counter, and A the number programmed into the ÷ A counter.
LD
Lock Detector Output (Pin 28)
Essentially a high level when loop is locked (fR, fV of same
phase and frequency). Pulses low when loop is out of lock.
POWER SUPPLY
V
DD
Positive Power Supply (Pin 3)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.
V
SS
Negative Power Supply (Pin 2)
The most negative supply potential. This pin is usually
ground.
TYPICAL APPLICATIONS
Figure 1. Synthesizer for Land Mobile Radio VHF Bands
NOTES:
1. Off–chip oscillator optional.
2. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter
Design page for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful
not to exceed the common mode input range of the op amp used in the combiner/loop filter.
LOCK DETECT SIGNAL
10.24 MHz
NOTE 1
R1
MC33171
NOTE 2
+
150 – 175 MHz
5 kHz STEPS
MC12017
÷
64/65 PRESCALER
MC145152–2
MC
LD
A0A5N9
OSC
in
V
DD
V
SS
OSC
out
RA2 RA1
φ
R
φ
V
f
in
–
VCO
RA0
N0
+ V
R1
R2 C
R2
C
“1” “1” “1”
NO CONNECTS
CHANNEL PROGRAMMING
Page 8
MC145151–2 through MC145158–2 MOTOROLA
8
Figure 2. 666–Channel, Computer–Controlled, Mobile Radiotelephone Synthesizer
for 800 MHz Cellular Radio Systems
LOCK DETECT SIGNAL
R1
+
RECEIVER FIRST L.O.
825.030
→
844.980 MHz
(30 kHz STEPS)
MC12017
÷
64/65 PRESCALER
NOTE 6
MC145152–2
NOTE 5
MC
LD
A0A5N9
OSC
in
V
DD
V
SS
OSC
out
RA2 RA1
φ
R
φ
V
f
in
–
VCO
RA0
N0
+ V
R1
R2 C
R2
C
“1” “1” “1”
NO CONNECTS
CHANNEL PROGRAMMING
NOTES:
1. Receiver 1st I.F. = 45 MHz, low side injection; Receiver 2nd I.F. = 11.7 MHz, low side injection.
2. Duplex operation with 45 MHz receiver/transmit separation.
3. fR = 7.5 kHz; ÷ R = 2048.
4. N
total
= N
64 + A = 27501 to 28166; N = 429 to 440; A = 0 to 63.
5. MC145158–2 may be used where serial data entry is desired.
6. High frequency prescalers (e.g., MC12018 [520 MHz] and MC12022 [1 GHz]) may be used for higher frequency VCO and f
ref
implementations.
7. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page for
additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode
input range of the op amp used in the combiner/loop filter.
REF. OSC.
15.360 MHz
(ON–CHIP OSC.
OPTIONAL)
X2
X4
NOTE 6
X4
NOTE 6
TRANSMITTER
MODULATION
TRANSMITTER SIGNAL
825.030
→
844.980 MHz
(30 kHz STEPS)
RECEIVER 2ND L.O.
30.720 MHz
NOTE 7
MC145152–2 Data Sheet Continued on Page 23
Page 9
MC145151–2 through MC145158–2MOTOROLA
9
Interfaces with Single–Modulus Prescalers
The MC145155–2 is programmed by a clocked, serial input, 16–bit data
stream. The device features consist of a reference oscillator, selectable–reference divider, digital–phase d etector, 14–bit programmable divide–by–N
counter, and the necessary shift register and latch circuitry for accepting serial
input data.
The MC145155–2 is an improved–performance drop–in replacement for the
MC145155–1. Power consumption has decreased and ESD and latch–up
performance have improved.
• Operating Temperature Range: – 40 to 85°C
• Low Power Consumption Through Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• On– or Off–Chip Reference Oscillator Operation with Buffered Output
• Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
• Lock Detect Signal
• Two Open–Drain Switch Outputs
• 8 User–Selectable ÷ R Values: 16, 512, 1024, 2048, 3668, 4096, 6144,
8192
• Single Modulus/Serial Programming
• ÷ N Range = 3 to 16383
• “Linearized” Digital Phase Detector Enhances Transfer Function Linearity
• Two Error Signal Options: Single–Ended (Three–State) or Double–Ended
• Chip Complexity: 6504 FETs or 1626 Equivalent Gates
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 707
DW SUFFIX
SOG PACKAGE
CASE 751D
ORDERING INFORMATION
MC145155P2 Plastic DIP
MC145155DW2 SOG Package
PIN ASSIGNMENTS
V
DD
φ
V
RA2
RA1
f
in
LD
V
SS
PD
out
φ
R
REF
out
OSC
out
OSC
in
RA0
CLK
DATA
ENB
SW1
SW2
14
15
16
17
18
10
11
12
13
5
4
3
2
1
9
8
7
6
PLASTIC DIP
PD
out
φ
R
φ
V
RA2
RA1
f
in
LD
NC
V
SS
V
DD
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
NC
REF
out
OSC
out
OSC
in
RA0
CLK
DATA
ENB
SW1
SW2
SOG PACKAGE
NC = NO CONNECTION
1
18
20
1
Motorola, Inc. 1995
REV 1
8/95
Page 10
MC145151–2 through MC145158–2 MOTOROLA
10
14 x 8 ROM REFERENCE DECODER
14–BIT
÷
N COUNTER
φ
V
φ
R
14–BIT
÷
R COUNTER
LATCH
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT
LD
PD
out
f
in
V
DD
OSC
in
OSC
out
ENB
14
14
SW2
SW1
f
R
f
V
LATCH
14–BIT SHIFT REGISTER
DATA
2–BIT SHIFT
REGISTER
CLK
14
REF
out
MC145155–2 BLOCK DIAGRAM
RA2
RA0
RA1
PIN DESCRIPTIONS
INPUT PINS
f
in
Frequency Input (PDIP – Pin 9, SOG – Pin 10)
Input to the ÷ N portion of the synthesizer. fin is typically
derived from loop VCO and is ac coupled into the device. For
larger amplitude signals (standard CMOS logic levels) dc
coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (PDIP – Pins 18, 1, 2;
SOG – Pins 20, 1, 2)
These three inputs establish a code defining one of eight
possible divide v alues for the total r eference divider, as
defined by the table below:
Reference Address Code
Total
RA2 RA1 RA0
Divide
Value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
512
1024
2048
3668
4096
6144
8192
CLK, DATA
Shift Register Clock, Serial Data Inputs
(PDIP – Pins 10, 11; SOG – Pins 11, 12)
Each low–to–high transition clocks one bit into the on–chip
16–bit shift register. The Data input provides programming
information for the 14–bit ÷ N counter and the two switch signals SW1 and SW2. The entry format is as follows:
SW2
SW1
N MSB
÷
N LSB
÷
÷
N COUNTER BITS
LAST DATA BIT IN (BIT NO. 16)
FIRST DATA BIT IN (BIT NO. 1)
ENB
Latch Enable Input (PDIP – Pin 12, SOG – Pin 13)
When high (1), ENB transfers the contents of the shift register into the latches, and to the programmable counter inputs, and the switch outputs SW1 and SW2. When low (0),
ENB inhibits the above action and thus allows changes to be
made in the shift register data without affecting the counter
programming and switch outputs. An on–chip pull–up establishes a continuously high level for ENB when no external
signal is applied. ENB is normally low and is pulsed high to
transfer data to the latches.
OSCin, OSC
out
Reference Oscillator Input/Output (PDIP – Pins 17, 16;
SOG – Pins 19, 18)
These pins form an on–chip reference oscillator when connected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSCin to ground and OSC
out
to ground.
OSCin may also serve as the input for an externally–generated reference signal. This signal is typically ac coupled to
OSCin, but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC
out
.
Page 11
MC145151–2 through MC145158–2MOTOROLA
11
OUTPUT PINS
PD
out
Phase Detector A Output (PDIP, SOG – Pin 6)
Three–state output of phase detector for use as loop error
signal. Double–ended outputs are also available for this purpose (see φV and φR).
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High–Imped-
ance State
φR, φ
V
Phase Detector B Outputs (PDIP, SOG – Pins 4, 3)
These phase detector outputs can be combined externally
for a loop–error signal. A single–ended output is also available for this purpose (see PD
out
).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by φR pulsing low.
φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both
φV and φR remain high except for a small minimum time
period when both pulse low in phase.
LD
Lock Detector Output (PDIP – Pin 8, SOG – Pin 9)
Essentially a high level when loop is locked (fR, fV of same
phase and frequency). LD pulses low when loop is out of
lock.
SW1, SW2
Band Switch Outputs (PDIP – Pins 13, 14;
SOG – Pins 14, 15)
SW1 and SW2 provide latched open–drain outputs corresponding to data bits numbers one and two. These outputs
can be tied through external resistors to voltages as high as
15 V, independent of the VDD supply voltage. These are
typically used for band switch functions. A logic 1 causes the
output to assume a high–impedance state, while a logic 0
causes the output to be low.
REF
out
Buffered Reference Oscillator Output (PDIP, SOG –
Pin 15)
Buffered output of on–chip reference oscillator or externally provided reference–input signal.
POWER SUPPLY
V
DD
Positive Power Supply (PDIP, SOG – Pin 5)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.
V
SS
Negative Power Supply (PDIP, SOG – Pin 7)
The most negative supply potential. This pin is usually
ground.
TYPICAL APPLICATIONS
Figure 1. Microprocessor–Controlled TV/CATV Tuning System with Serial Interface
f
in
3
LED DISPLAY
MC14489
KEYBOARD
CMOS
MPU/MCU
ENBCLKDATA
1/2 MC1458*
MC145155–2
MC12073/74
PRESCALER
UHF/VHF
TUNER OR
CATV
FRONT END
4.0 MHz
φ
V
φ
R
+
–
*The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page
for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common
mode input range of the op amp used in the combiner/loop filter.
Page 12
MC145151–2 through MC145158–2 MOTOROLA
12
Figure 2. AM/FM Radio Synthesizer
TO
AM/FM
OSCILLATORS
TO DISPLAY
MC12019
÷
20 PRESCALER
AM
OSC
FM
OSC
f
in
KEYBOARD
CMOS
MPU/MCU
ENBCLKDATA
1/2 MC1458*
MC145155–2
2.56 MHz
φ
V
φ
R
+
–
*The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page
for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common
mode input range of the op amp used in the combiner/loop filter.
MC145155–2 Data Sheet Continued on Page 23
Page 13
MC145151–2 through MC145158–2MOTOROLA
13
!
Interfaces with Dual–Modulus Prescalers
The MC145156–2 is programmed by a clocked, serial input, 19–bit data
stream. The device features consist of a reference oscillator, selectable–reference divider, digital–phase d etector, 10–bit programmable divide–by–N
counter, 7–bit programmable divide–by–A counter, and the necessary shift
register and latch circuitry for accepting serial input data.
The MC145156–2 is an improved–performance drop–in replacement for the
MC145156–1. Power consumption has decreased and ESD and latch–up
performance have improved.
• Operating Temperature Range: – 40 to 85°C
• Low Power Consumption Through Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• On– or Off–Chip Reference Oscillator Operation with Buffered Output
• Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
• Lock Detect Signal
• Two Open–Drain Switch Outputs
• Dual Modulus/Serial Programming
• 8 User–Selectable ÷ R Values: 8, 64, 128, 256, 640, 1000, 1024, 2048
• ÷ N Range = 3 to 1023, ÷ A Range = 0 to 127
• “Linearized” Digital Phase Detector Enhances Transfer Function Linearity
• Two Error Signal Options: Single–Ended (Three–State) or Double–Ended
• Chip Complexity: 6504 FETs or 1626 Equivalent Gates
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 738
DW SUFFIX
SOG PACKAGE
CASE 751D
ORDERING INFORMATION
MC145156P2 Plastic DIP
MC145156DW2 SOG Package
PIN ASSIGNMENT
PD
out
φ
R
φ
V
RA2
RA1
f
in
LD
MC
V
SS
VDD5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
TEST
REF
out
OSC
out
OSC
in
RA0
CLK
DATA
ENB
SW1
SW2
1
20
1
20
Motorola, Inc. 1995
REV 1
8/95
Page 14
MC145151–2 through MC145158–2 MOTOROLA
14
12 x 8 ROM REFERENCE DECODER
φ
V
φ
R
12–BIT
÷
R COUNTER
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT
LD
PD
out
f
in
V
DD
OSC
in
OSC
out
ENB
12
10
SW2
SW1
f
R
f
V
LATCH
DATA
2–BIT SHIFT
REGISTER
CLK
10
REF
out
10–BIT SHIFT REGISTER7–BIT SHIFT REGISTER
÷
A COUNTER LATCH
÷
N COUNTER LATCH
7–BIT
÷
A COUNTER 10–BIT ÷ N COUNTER
CONTROL LOGIC
MC
7
7
MC145156–2 BLOCK DIAGRAM
RA2
RA0
RA1
PIN DESCRIPTIONS
INPUT PINS
f
in
Frequency Input (Pin 10)
Input to the positive edge triggered ÷ N and ÷ A counters.
fin is typically derived from a dual–modulus prescaler and is
ac coupled into the device. For larger amplitude signals
(standard CMOS logic levels), dc coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (Pins 20, 1, 2)
These three inputs establish a code defining one of eight
possible divide v alues for the total r eference divider, as
defined by the table below:
Reference Address Code
Total
RA2 RA1 RA0
Divide
Value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
64
128
256
640
1000
1024
2048
CLK, DATA
Shift Register Clock, Serial Data Inputs (Pins 11, 12)
Each low–to–high transition clocks one bit into the on–chip
19–bit shift register. The data input provides programming information for the 10–bit ÷ N counter, the 7–bit ÷ A counter,
and the two switch signals SW1 and SW2. The entry format
is as follows:
SW2
SW1
N MSB
÷
A LSB
÷
÷
N COUNTER BITS
LAST DATA BIT IN (BIT NO. 19)
FIRST DATA BIT IN (BIT NO. 1)
÷
A COUNTER BITS
N LSB
÷
A MSB
÷
ENB
Latch Enable Input (Pin 13)
When high (1), ENB transfers the contents of the shift register into the latches, and to the programmable counter inputs, and the switch outputs SW1 and SW2. When low (0),
ENB inhibits the above action and thus allows changes to be
made in the shift register data without affecting the counter
programming and switch outputs. An on–chip pull–up establishes a continuously high level for ENB when no external
signal is applied. ENB is normally low and is pulsed high to
transfer data to the latches.
OSCin, OSC
out
Reference Oscillator Input/Output (Pins 19, 18)
These pins form an on–chip reference oscillator when connected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSCin to ground and OSC
out
to ground.
OSCin may also serve as the input for an externally–generated reference signal. This signal is typically ac coupled to
OSCin, but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC
out
.
TEST
Factory Test Input (Pin 16)
Used in manufacturing. Must be left open or tied to VSS.
Page 15
MC145151–2 through MC145158–2MOTOROLA
15
OUTPUT PINS
PD
out
Phase Detector A Output (Pin 6)
Three–state output of phase detector for use as loop–error
signal. Double–ended outputs are also available for this purpose (see φV and φR).
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High–Imped-
ance State
φR, φ
V
Phase Detector B Outputs (Pins 4, 3)
These phase detector outputs can be combined externally
for a loop–error signal. A single–ended output is also available for this purpose (see PD
out
).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by φR pulsing low.
φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both
φV and φR remain high except for a small minimum time
period when both pulse low in phase.
MC
Dual–Modulus Prescale Control Output (Pin 8)
Signal generated by the on–chip control logic circuitry for
controlling an external dual–modulus prescaler. The MC
level will be low at the beginning of a count cycle and will
remain low until the ÷ A counter has counted down from its
programmed value. At this time, MC goes high and remains
high until the ÷ N counter has counted the rest of the way
down from its programmed value (N – A additional counts
since both ÷ N and ÷ A are counting down during the first por-
tion of the cycle). MC is then set back low, the counters
preset to their respective programmed values, and the above
sequence repeated. This provides for a total programmable
divide value (NT) = N
P + A where P and P + 1 represent the
dual–modulus prescaler divide values respectively for high
and low MC levels, N the number programmed into the ÷ N
counter, and A the number programmed into the ÷ A counter.
LD
Lock Detector Output (Pin 9)
Essentially a high level when loop is locked (fR, fV of same
phase and frequency). LD pulses low when loop is out of
lock.
SW1, SW2
Band Switch Outputs (Pins 14, 15)
SW1 and SW2 provide latched open–drain outputs corresponding to data bits numbers one and two. These outputs
can be tied through external resistors to voltages as high as
15 V, independent of the VDD supply voltage. These are
typically used for band switch functions. A logic 1 causes the
output to assume a high–impedance state, while a logic 0
causes the output to be low.
REF
out
Buffered Reference Oscillator Output (Pin 17)
Buffered output of on–chip reference oscillator or externally provided reference–input signal.
POWER SUPPLY
V
DD
Positive Power Supply (Pin 5)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.
V
SS
Negative Power Supply (Pin 7)
The most negative supply potential. This pin is usually
ground.
Page 16
MC145151–2 through MC145158–2 MOTOROLA
16
TYPICAL APPLICATIONS
Figure 1. AM/FM Radio Broadcast Synthesizer
SW2SW1
φ
V
φ
R
PD
out
MC
f
inENBDATACLK
REF
out
V
SS
V
DD
LDRA0RA1RA2OSCinOSC
out
NOTES 1
AND 2
OPTIONAL
LOOP
ERROR SIGNAL
MC12019
÷
20/21 DUAL MODULUS PRESCALER
VCO
AM B +
+ 12 V
FM B +
+ 12 V
LOCK DETECT SIGNAL
TO DISPLAY DRIVER (e.g., MC14489)
CMOS MPU/MCU
KEY–
BOARD
+ V
3.2 MHz
MC145156–2
1/2 MC1458
NOTE 3
+
–
NOTES:
1. For AM: channel spacing = 5 kHz, ÷ R = ÷ 640 (code 100).
2. For FM: channel spacing = 25 kHz, ÷ R = ÷ 128 (code 010).
3. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page
for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the
common mode input range of the op amp used in the combiner/loop filter.
Figure 2. Avionics Navigation or Communication Synthesizer
NAV = 01
COM = 10
CHANNEL
SELECTION
VCO
LOCK DETECT SIGNAL
TO DISPLAY DRIVER
(e.g., MC14489)
CMOS MPU/MCU
+ V
3.2 MHz (NOTE 3)
MC145156–2
MC33171
NOTE 5
SW2SW1
φ
V
φ
R
PD
out
MC
f
inENBDATACLK
REF
out
V
SS
V
DD
LDRA0RA1RA2OSCinOSC
out
MC12016 (NOTES 2 AND 4)
÷
40/41 DUAL MODULUS PRESCALER
+
–
VCO RANGE
NAV: 97.300 – 107.250 MHz
COM–T: 118.000 – 135.975 MHz
COM–R: 139.400 – 157.375 MHz
R/T
NOTES:
1. For NAV: fR = 50 kHz, ÷ R = 64 using 10.7 MHz lowside injection, N
total
= 1946 – 2145.
For COM–T: fR = 25 kHz, ÷ R = 128, N
total
= 4720 – 5439.
For COM–R: fR = 25 kHz, ÷ R = 128, using 21.4 MHz highside injection, N
total
= 5576 – 6295.
2. A ÷ 32/33 dual modulus approach is provided by substituting an MC12015 for the MC12016. The devices are pin equivalent.
3. A 6.4 MHz oscillator crystal can be used by selecting ÷ R = 128 (code 010) for NAV and ÷ R = 256 (code 011) for COM.
4. MC12013 + MC10131 combination may also be used to form the ÷ 40/41 prescaler.
5. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design
page for additional information. The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed
the common mode input range of the op amp used in the combiner/loop filter.
MC145156–2 Data Sheet Continued on Page 23
Page 17
MC145151–2 through MC145158–2MOTOROLA
17
!
Interfaces with Single–Modulus Prescalers
The MC145157–2 has a fully programmable 14–bit reference counter, as well
as a fully programmable ÷ N counter. The counters are programmed serially
through a common data input and latched into the appropriate counter latch,
according to the last data bit (control bit) entered.
The MC145157–2 is an improved–performance drop–in replacement for the
MC145157–1. Power consumption has decreased and ESD and latch–up
performance have improved.
• Operating Temperature Range: – 40 to 85°C
• Low Power Consumption Through Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• Fully Programmable Reference and ÷ N Counters
• ÷ R Range = 3 to 16383
• ÷ N Range = 3 to 16383
• fV and fR Outputs
• Lock Detect Signal
• Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
• “Linearized” Digital Phase Detector
• Single–Ended (Three–State) or Double–Ended Phase Detector Outputs
• Chip Complexity: 6504 FETs or 1626 Equivalent Gates
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 648
DW SUFFIX
SOG PACKAGE
CASE 751G
ORDERING INFORMATION
MC145157P2 Plastic DIP
MC145157DW2 SOG Package
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
S/R
out
f
R
REF
out
φ
V
φ
R
CLK
DATA
ENB
V
DD
f
V
OSC
out
OSC
in
f
in
LD
V
SS
PD
out
1
16
1
16
Motorola, Inc. 1995
REV 1
8/95
Page 18
MC145151–2 through MC145158–2 MOTOROLA
18
14–BIT SHIFT REGISTER
14–BIT
÷
N COUNTER
φ
V
MC145157–2 BLOCK DIAGRAM
φ
R
REFERENCE COUNTER LATCH
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT
LD
PD
out
f
in
OSC
in
OSC
out
ENB
14
14
14–BIT SHIFT REGISTER
DATA
CLK
14
REF
out
÷
N COUNTER LATCH
14–BIT
÷
R COUNTER
14
S/R
out
f
R
f
V
1–BIT
CONTROL
S/R
PIN DESCRIPTIONS
INPUT PINS
f
in
Frequency Input (Pin 8)
Input frequency from VCO output. A rising edge signal on
this input decrements the ÷ N counter. This input has an
inverter biased i n the linear region to allow use with ac
coupled signals as low as 500 mV p–p. For larger amplitude
signals (standard CMOS logic levels), dc coupling may be
used.
CLK, DATA
Shift Clock, Serial Data Inputs (Pins 9, 10)
Each low–to–high transition of the clock shifts one bit of
data into the on–chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic 1
selects the reference counter latch and a logic 0 selects the
÷ N counter latch. The entry format is as follows:
LSB
MSB
CONTROL
FIRST DATA BIT INTO SHIFT REGISTER
ENB
Latch Enable Input (Pin 11)
A logic high on this pin latches the data from the shift register into the reference divider or ÷ N latches depending on the
control bit. The reference divider latches are activated if the
control bit is at a logic high and the ÷ N latches are activated
if the control bit is at a logic low. A logic low on this pin allows
the user to c hange the data in the shift registers without
affecting the counters. ENB is normally low and is pulsed
high to transfer data to the latches.
OSCin, OSC
out
Reference Oscillator Input/Output (Pins 1, 2)
These pins form an on–chip reference oscillator when connected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSCin to ground and OSC
out
to ground.
OSCin may also serve as the input for an externally–generated reference signal. This signal is typically ac coupled to
OSCin, but for larger amplitude signals (standard CMOS
logic levels) dc coupling may also be used. In the external
reference mode, no connection is required to OSC
out
.
OUTPUT PINS
PD
out
Single–Ended Phase Detector A Output (Pin 5)
This single–ended (three–state) phase detector output
produces a loop–error signal that is used with a loop filter to
control a VCO.
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High–Imped-
ance State
φR, φ
V
Double–Ended Phase Detector B Outputs (Pins 16, 15)
These outputs can be combined externally for a loop–error
signal. A single–ended output is also available for this purpose (see PD
out
).
Page 19
MC145151–2 through MC145158–2MOTOROLA
19
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by φR pulsing low.
φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both
φV and φR remain high except for a small minimum time
period when both pulse low in phase.
fR, f
V
R Counter Output, N Counter Output (Pins 13, 3)
Buffered, divided reference and fin frequency outputs. The
fR and fV outputs are connected internally to the ÷ R and ÷ N
counter outputs respectively, allowing the counters to be
used independently , as well as monitoring the phase detector
inputs.
LD
Lock Detector Output (Pin 7)
This output is essentially at a high level when the loop is
locked (fR, fV of same phase and frequency), and pulses low
when loop is out of lock.
REF
out
Buffered Reference Oscillator Output (Pin 14)
This output can be used as a second local oscillator, reference oscillator to another frequency synthesizer, or as the
system clock to a microprocessor controller.
S/R
out
Shift Register Output (Pin 12)
This output can be connected to an external shift register
to provide band switching, control information, and counter
programming code checking.
POWER SUPPLY
V
DD
Positive Power Supply (Pin 4)
The positive power supply potential. This pin may range
from +3 to +9 V with respect to VSS.
V
SS
Negative Power Supply (Pin 6)
The most negative supply potential. This pin is usually
ground.
MC145157–2 Data Sheet Continued on Page 23
Page 20
MC145151–2 through MC145158–2 MOTOROLA
20
!
Interfaces with Dual–Modulus Prescalers
The MC145158–2 has a fully programmable 14–bit reference counter, as well
as fully programmable ÷ N and ÷ A counters. The counters are programmed
serially through a common data input and latched into the appropriate counter
latch, according to the last data bit (control bit) entered.
The MC145158–2 is an improved–performance drop–in replacement for the
MC145158–1. Power consumption has decreased and ESD and latch–up
performance have improved.
• Operating Temperature Range: – 40 to 85°C
• Low Power Consumption Through Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• Fully Programmable Reference and ÷ N Counters
• ÷ R Range = 3 to 16383
• ÷ N Range = 3 to 1023
• Dual Modulus Capability; ÷ A Range = 0 to 127
• fV and fR Outputs
• Lock Detect Signal
• Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
• “Linearized” Digital Phase Detector
• Single–Ended (Three–State) or Double–Ended Phase Detector Outputs
• Chip Complexity: 6504 FETs or 1626 Equivalent Gates
SEMICONDUCTOR TECHNICAL DATA
P SUFFIX
PLASTIC DIP
CASE 648
DW SUFFIX
SOG PACKAGE
CASE 751G
ORDERING INFORMATION
MC145158P2 Plastic DIP
MC145158DW2 SOG Package
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
MC
f
R
REF
out
φ
V
φ
R
CLK
DATA
ENB
V
DD
f
V
OSC
out
OSC
in
f
in
LD
V
SS
PD
out
1
16
1
16
Motorola, Inc. 1995
REV 1
8/95
Page 21
MC145151–2 through MC145158–2MOTOROLA
21
14–BIT SHIFT REGISTER
7–BIT
÷
A
COUNTER
φ
V
MC145158–2 BLOCK DIAGRAM
φ
R
REFERENCE COUNTER LATCH
PHASE
DETECTOR
B
PHASE
DETECTOR
A
LOCK
DETECT
LD
PD
out
f
in
OSC
in
OSC
out
ENB
14
10
7–BIT S/R
DATA
CLK
10
REF
out
÷
A COUNTER
LATCH
14–BIT
÷
R COUNTER
14
MC
f
R
f
V
1–BIT
CONTROL
S/R
10–BIT S/R
÷
N COUNTER
LATCH
10–BIT
÷
N
COUNTER
CONTROL LOGIC
7
7
PIN DESCRIPTIONS
INPUT PINS
f
in
Frequency Input (Pin 8)
Input frequency from VCO output. A rising edge signal on
this input decrements the ÷ A and ÷ N counters. This input
has an inverter biased in the linear region to allow use with
ac coupled signals as low as 500 mV p–p. For larger amplitude signals (standard CMOS logic levels), dc coupling may
be used.
CLK, DATA
Shift Clock, Serial Data Inputs (Pins 9, 10)
Each low–to–high transition of the CLK shifts one bit of
data into the on–chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic 1
selects the reference counter latch and a logic 0 selects the
÷ A, ÷ N counter latch. The data entry format is as follows:
LSB
MSB
CONTROL
FIRST DATA BIT INTO SHIFT REGISTER
÷
R
MSB
CONTROL
÷
N
FIRST DATA BIT INTO SHIFT REGISTER
÷
A
LSB
MSB
LSB
ENB
Latch Enable Input (Pin 11)
A logic high on this pin latches the data from the shift register into the reference divider or ÷ N, ÷ A latches depending on
the control bit. The reference divider latches are activated if
the control bit is at a logic high and the ÷ N, ÷ A latches are
activated if the control bit is at a logic low. A logic low on this
pin allows the user to change the data in the shift registers
without affecting the counters. ENB is normally low and is
pulsed high to transfer data to the latches.
OSCin, OSC
out
Reference Oscillator Input/Output (Pins 1, 2)
These pins form an on–chip reference oscillator when connected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSCin to ground and OSC
out
to ground.
OSCin may also serve as the input for an externally–generated reference signal. This signal is typically ac coupled to
OSCin, but for larger amplitude signals (standard CMOS logic levels) dc coupling may also be used. In the external reference mode, no connection is required to OSC
out
.
Page 22
MC145151–2 through MC145158–2 MOTOROLA
22
OUTPUT PINS
PD
out
Phase Detector A Output (Pin 5)
This single–ended (three–state) phase detector output
produces a loop–error signal that is used with a loop filter to
control a VCO.
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence: High–Imped-
ance State
φR, φ
V
Phase Detector B Outputs (Pins 16, 15)
Double–ended phase detector outputs. These outputs can
be combined externally for a loop–error signal. A single–
ended output is also available for this purpose (see PD
out
).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by φR pulsing low.
φV remains essentially high.
If the frequency of fV = fR and both are in phase, then both
φV and φR remain high except for a small minimum time
period when both pulse low in phase.
MC
Dual–Modulus Prescale Control Output (Pin 12)
This output generates a signal by the on–chip control logic
circuitry for controlling an external dual–modulus prescaler.
The MC level is low at the beginning of a count cycle and
remains low until the ÷ A counter has counted down from its
programmed value. At this time, MC goes high and remains
high until the ÷ N counter has counted the rest of the way
down from its programmed value (N – A additional counts
since both ÷ N and ÷ A are counting down during the first por-
tion of the cycle). MC is then set back low, the counters preset to their respective programmed values, and the above
sequence repeated. This provides for a total programmable
divide value (NT) = N
P + A where P and P + 1 represent the
dual–modulus prescaler divide values respectively for high
and low modulus control levels, N the number programmed
into the ÷ N counter, and A the number programmed into the
÷ A counter. Note that when a prescaler is needed, the dual–
modulus version o ffers a distinct advantage. The d ual–
modulus prescaler allows a higher reference frequency at
the phase detector input, increasing system performance capability, and simplifying the loop filter design.
fR, f
V
R Counter Output, N Counter Output (Pins 13, 3)
Buffered, divided reference and fin frequency outputs. The
fR and fV outputs are connected internally to the ÷ R and
÷ N counter outputs respectively, allowing the counters to be
used independently , as well as monitoring the phase detector
inputs.
LD
Lock Detector Output (Pin 7)
This output is essentially at a high level when the loop is
locked (fR, fV of same phase and frequency), and pulses low
when loop is out of lock.
REF
out
Buffered Reference Oscillator Output (Pin 14)
This output can be used as a second local oscillator, reference oscillator to another frequency synthesizer, or as the
system clock to a microprocessor controller.
POWER SUPPLY
V
DD
Positive Power Supply (Pin 4)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.
V
SS
Negative Power Supply (Pin 6)
The most negative supply potential. This pin is usually
ground.
Page 23
MC145151–2 through MC145158–2MOTOROLA
23
MC14515X–2 FAMILY CHARACTERISTICS AND DESCRIPTIONS
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 10.0 V
Vin, V
out
Input or Output Voltage (DC or Transient)
except SW1, SW2
– 0.5 to VDD + 0.5 V
V
out
Output Voltage (DC or Transient),
SW1, SW2 (R
pull–up
= 4.7 kΩ)
– 0.5 to + 15 V
Iin, I
out
Input or Output Current (DC or Transient),
per Pin
± 10 mA
IDD, ISSSupply Current, VDD or VSS Pins ± 30 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150 °C
T
L
Lead Temperature, 1 mm from Case for
10 seconds
260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
†Power Dissipation Temperature Derating:
Plastic DIP: – 12 mW/°C from 65 to 85°C
SOG Package: – 7 mW/°C from 65 to 85°C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 40°C 25°C 85°C
Symbol
Parameter
Test Condition
V
DD
V
Min Max Min Max Min Max
Unit
V
DD
Power Supply Voltage
Range
— 3 9 3 9 3 9 V
I
ss
Dynamic Supply Current fin = OSCin = 10 MHz,
1 V p–p ac coupled sine
wave
R = 128, A = 32, N = 128
3
5
9
—
—
—
3.5
10
30
—
—
—
3
7.5
24
—
—
—
3
7.5
24
mA
I
SS
Quiescent Supply Current
(not including pull–up
current component)
Vin = VDD or V
SS
I
out
= 0 µA
3
5
9
—
—
—
800
1200
1600
—
—
—
800
1200
1600
—
—
—
1600
2400
3200
µA
V
in
Input Voltage — fin, OSCinInput ac coupled sine wave — 500 — 500 — 500 — mV p–p
V
IL
Low–Level Input Voltage
— fin, OSC
in
V
out
≥ 2.1 V Input dc
V
out
≥ 3.5 V coupled
V
out
≥ 6.3 V square wave
3
5
9
—
—
—
0
0
0
—
—
—
0
0
0
—
—
—
0
0
0
V
V
IH
High–Level Input Voltage
— fin, OSC
in
V
out
≤ 0.9 V Input dc
V
out
≤ 1.5 V coupled
V
out
≤ 2.7 V square wave
3
5
9
3.0
5.0
9.0
—
—
—
3.0
5.0
9.0
—
—
—
3.0
5.0
9.0
—
—
—
V
V
IL
Low–Level Input Voltage
— except fin, OSC
in
3
5
9
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
V
V
IH
High–Level Input Voltage
— except fin, OSC
in
3
5
9
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
V
I
in
Input Current (fin, OSCin) Vin = VDD or V
SS
9 ± 2 ± 50 ± 2 ± 25 ± 2 ± 22 µA
I
IL
Input Leakage Current
(Data, CLK, ENB —
without pull–ups)
Vin = V
SS
9 — – 0.3 — – 0.1 — – 1.0 µA
I
IH
Input Leakage Current (all
inputs except fin, OSCin)
Vin = V
DD
9 — 0.3 — 0.1 — 1.0 µA
(continued)
These devices contain protection circuitry to
protect against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any
voltage higher than maximum rated voltages
to these high–impedance circuits. For proper
operation, Vin and V
out
should be constrained
to the range VSS ≤ (Vin or V
out
) ≤ V
DD
except for SW1 and SW2.
SW1 and SW2 can be tied through external
resistors to voltages as high as 15 V , independent of the supply voltage.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or VDD), except for inputs with pull–up devices.
Unused outputs must be left open.
Page 24
MC145151–2 through MC145158–2 MOTOROLA
24
DC ELECTRICAL CHARACTERISTICS (continued)
V
– 40°C 25°C 85°C
Symbol
Parameter
Test Condition
V
DD
V
Min Max Min Max Min Max
Unit
I
IL
Pull–up Current (all inputs
with pull–ups)
Vin = V
SS
9 – 20 – 400 – 20 – 200 – 20 – 170 µA
C
in
Input Capacitance — — 10 — 10 — 10 pF
V
OL
Low–Level Output
Voltage — OSC
out
I
out
≈ 0 µA
Vin = V
DD
3
5
9
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
—
—
—
0.9
1.5
2.7
V
V
OH
High–Level Output
Voltage — OSC
out
I
out
≈ 0 µA
Vin = V
SS
3
5
9
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
2.1
3.5
6.3
—
—
—
V
V
OL
Low–Level Output
Voltage — Other Outputs
I
out
≈ 0 µA 3
5
9
—
—
—
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
V
V
OH
High–Level Output
Voltage — Other Outputs
I
out
≈ 0 µA 3
5
9
2.95
4.95
8.95
—
—
—
2.95
4.95
8.95
—
—
—
2.95
4.95
8.95
—
—
—
V
V
(BR)DSS
Drain–to–Source
Breakdown Voltage —
SW1, SW2
R
pull–up
= 4.7 kΩ — 15 — 15 — 15 — V
I
OL
Low–Level Sinking
Current — MC
V
out
= 0.3 V
V
out
= 0.4 V
V
out
= 0.5 V
3
5
9
1.30
1.90
3.80
—
—
—
1.10
1.70
3.30
—
—
—
0.66
1.08
2.10
—
—
—
mA
I
OH
High–Level Sourcing
Current — MC
V
out
= 2.7 V
V
out
= 4.6 V
V
out
= 8.5 V
3
5
9
– 0.60
– 0.90
– 1.50
—
—
—
– 0.50
– 0.75
– 1.25
—
—
—
– 0.30
– 0.50
– 0.80
—
—
—
mA
I
OL
Low–Level Sinking
Current — LD
V
out
= 0.3 V
V
out
= 0.4 V
V
out
= 0.5 V
3
5
9
0.25
0.64
1.30
—
—
—
0.20
0.51
1.00
—
—
—
0.15
0.36
0.70
—
—
—
mA
I
OH
High–Level Sourcing
Current — LD
V
out
= 2.7 V
V
out
= 4.6 V
V
out
= 8.5 V
3
5
9
– 0.25
– 0.64
– 1.30
—
—
—
– 0.20
– 0.51
– 1.00
—
—
—
– 0.15
– 0.36
– 0.70
—
—
—
mA
I
OL
Low–Level Sinking
Current — SW1, SW2
V
out
= 0.3 V
V
out
= 0.4 V
V
out
= 0.5 V
3
5
9
0.80
1.50
3.50
—
—
—
0.48
0.90
2.10
—
—
—
0.24
0.45
1.05
—
—
—
mA
I
OL
Low–Level Sinking
Current — Other Outputs
V
out
= 0.3 V
V
out
= 0.4 V
V
out
= 0.5 V
3
5
9
0.44
0.64
1.30
—
—
—
0.35
0.51
1.00
—
—
—
0.22
0.36
0.70
—
—
—
mA
I
OH
High–Level Sourcing
Current — Other Outputs
V
out
= 2.7 V
V
out
= 4.6 V
V
out
= 8.5 V
3
5
9
– 0.44
– 0.64
– 1.30
—
—
—
– 0.35
– 0.51
– 1.00
—
—
—
– 0.22
– 0.36
– 0.70
—
—
—
mA
I
OZ
Output Leakage Current —
PD
out
V
out
= VDD or V
SS
Output in Off State
9 — ± 0.3 — ± 0.1 — ± 1.0 µA
I
OZ
Output Leakage Current —
SW1, SW2
V
out
= VDD or V
SS
Output in Off State
9 — ± 0.3 — ± 0.1 — ± 3.0 µA
C
out
Output Capacitance —
PD
out
PD
out
— Three–State — — 10 — 10 — 10 pF
Page 25
MC145151–2 through MC145158–2MOTOROLA
25
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 10 ns)
Symbol
Parameter
V
DD
V
Guaranteed Limit
25°C
Guaranteed Limit
– 40 to 85°C
Unit
t
PLH
, t
PHL
Maximum Propagation Delay, fin to MC
(Figures 1 and 4)
3
5
9
110
60
35
120
70
40
ns
t
PHL
Maximum Propagation Delay, ENB to SW1, SW2
(Figures 1 and 5)
3
5
9
160
80
50
180
95
60
ns
t
w
Output Pulse Width, φR, φV, and LD with fR in Phase with f
V
(Figures 2 and 4)
3
5
9
25 to 200
20 to 100
10 to 70
25 to 260
20 to 125
10 to 80
ns
t
TLH
Maximum Output Transition Time, MC
(Figures 3 and 4)
3
5
9
115
60
40
115
75
60
ns
t
THL
Maximum Output Transition Time, MC
(Figures 3 and 4)
3
5
9
60
34
30
70
45
38
ns
t
TLH
, t
THL
Maximum Output Transition Time, LD
(Figures 3 and 4)
3
5
9
180
90
70
200
120
90
ns
t
TLH
, t
THL
Maximum Output Transition Time, Other Outputs
(Figures 3 and 4)
3
5
9
160
80
60
175
100
65
ns
SWITCHING WAVEFORMS
TEST POINT
DEVICE
UNDER
TEST
CL*
*Includes all probe and fixture capacitance.
TEST POINT
DEVICE
UNDER
TEST
CL*
*Includes all probe and fixture capacitance.
V
DD
15 k
Ω
t
TLH
90%
10%
t
THL
ANY
OUTPUT
Figure 1.
Figure 2.
50%
OUTPUT
50%
INPUT
t
PLH
— V
SS
V
DD
t
PHL
50%
φ
R
,
φ
V
, LD*
*fR in phase with fV.
t
w
OUTPUTOUTPUT
Figure 3.
Figure 4. Test Circuit Figure 5. Test Circuit
Page 26
MC145151–2 through MC145158–2 MOTOROLA
26
TIMING REQUIREMENTS (Input t
r
= tf = 10 ns unless otherwise indicated)
Symbol
Parameter
V
DD
V
Guaranteed Limit
25°C
Guaranteed Limit
– 40 to 85°C
Unit
f
clk
Serial Data Clock Frequency, Assuming 25% Duty Cycle
NOTE: Refer to CLK t
w(H)
below
(Figure 6)
3
5
9
dc to 5.0
dc to 7.1
dc to 10
dc to 3.5
dc to 7.1
dc to 10
MHz
t
su
Minimum Setup Time, Data to CLK
(Figure 7)
3
5
9
30
20
18
30
20
18
ns
t
h
Minimum Hold Time, CLK to Data
(Figure 7)
3
5
9
40
20
15
40
20
15
ns
t
su
Minimum Setup Time, CLK to ENB
(Figure 7)
3
5
9
70
32
25
70
32
25
ns
t
rec
Minimum Recovery Time, ENB to CLK
(Figure 7)
3
5
9
5
10
20
5
10
20
ns
t
w(H)
Minimum Pulse Width, CLK and ENB
(Figure 6)
3
5
9
50
35
25
70
35
25
ns
tr, t
f
Maximum Input Rise and Fall Times — Any Input
(Figure 8)
3
5
9
5
4
2
5
4
2
µs
SWITCHING WAVEFORMS
Figure 6.
Figure 7.
V
SS
— V
DD
50%
50%
LAST
CLK
PREVIOUS
DATA
LATCHED
FIRST
CLK
ENB
CLK
DATA
50%
— V
DD
V
SS
— V
DD
V
SS
— V
DD
V
SS
t
su
t
su
t
rec
t
h
50%
CLK,
ENB
t
w(H)
— V
DD
V
SS
4 f
clk
1
*
*Assumes 25% Duty Cycle.
t
t
90%
10%
t
f
ANY
OUTPUT
Figure 8.
Page 27
MC145151–2 through MC145158–2MOTOROLA
27
FREQUENCY CHARACTERISTICS (Voltages References to V
SS
, CL = 50 pF, Input tr = tf =10 ns unless otherwise indicated)
V
– 40°C 25°C 85°C
Symbol
Parameter
Test Condition
V
DD
V
Min Max Min Max Min Max
Unit
R ≥ 8, A ≥ 0, N ≥ 8
Vin = 500 mV p–p
ac coupled sine wave
3
5
9
—
—
—
6
15
15
—
—
—
6
15
15
—
—
—
6
15
15
MHz
R ≥ 8, A ≥ 0, N ≥ 8
Vin = 1 V p–p ac coupled
sine wave
3
5
9
—
—
—
12
22
25
—
—
—
12
20
22
—
—
—
7
20
22
MHz
R ≥ 8, A ≥ 0, N ≥ 8
Vin = VDD to V
SS
dc coupled square wave
3
5
9
—
—
—
13
25
25
—
—
—
12
22
25
—
—
—
8
22
25
MHz
NOTE: Usually, the PLL ’s propagation delay from fin to MC plus the setup time of the prescaler determines the upper frequency limit of the system.
The upper frequency limit is found with the following formula: f = P/(tP + t
set
) where f is the upper frequency in Hz, P is the lower of the dual
modulus prescaler ratios, tP is the fin to MC propagation delay in seconds, and t
set
is the prescaler setup time in seconds.
For example, with a 5 V supply, the fin to MC delay is 70 ns. If the MC12028A prescaler is used, the setup time is 16 ns. Thus, if the 64/65
ratio is utilized, the upper frequency limit is f = P/(tP + t
set
) = 64/(70 + 16) = 744 MHz.
VH= High Voltage Level.
VL= Low Voltage Level.
*At this point, when both fR and fV are in phase, the output is forced to near mid–supply.
NOTE: The PD
out
generates error pulses during out–of–lock conditions. When locked in phase and frequency the output is high
and the voltage at this pin is determined by the low–pass filter capacitor.
f
R
REFERENCE
OSC ÷ R
f
V
FEEDBACK
(fin
÷
N)
PD
out
φ
R
φ
V
LD
*
V
H
V
L
V
H
V
L
V
H
HIGH IMPEDANCE
V
H
V
L
V
H
V
L
V
H
V
L
V
L
Figure 9. Phase Detector/Lock Detector Output Waveforms
f
Input Frequency
i
(fin, OSCin)
Page 28
MC145151–2 through MC145158–2 MOTOROLA
28
DESIGN CONSIDERATIONS
PHASE–LOCKED LOOP — LOW–PASS FILTER DESIGN
C)
_
+
A
C
R
2
C
VCO
C
VCO
R
2
B)
A)
C
VCO
PD
out
PD
out
φ
R
—
φ
V
—
PD
out
—
φ
R
φ
V
R
1
R
1
R
1
R
1
R
2
NOTE: Sometimes R1 is split into two series resistors, each R1 ÷ 2. A capacitor CC is then placed from the midpoint to ground to further
filter φV and φR. The value of CC should be such that the corner frequency of this network does not significantly affect ωn.
The φR and φV outputs swing rail–to–rail. Therefore, the user should be careful not to exceed the common mode input range of the
op amp used in the combiner/loop filter.
DEFINITIONS:
N = Total Division Ratio in feedback loop
Kφ (Phase Detector Gain) = VDD/4
π for PD
out
Kφ (Phase Detector Gain) = VDD/2π for φV and φ
R
K
VCO
(VCO Gain) =
2π∆f
VCO
∆V
VCO
for a typical design wn (Natural Frequency)
≈
2πfr
10
(at phase detector input).
Damping Factor:
ζ ≅ 1
RECOMMENDED READING:
Gardner, Floyd M.,
Phaselock Techniques (second edition).
New York, Wiley–Interscience, 1979.
Manassewitsch, Vadim,
Frequency Synthesizers: Theory and Design (second edition).
New York, Wiley–Interscience, 1980.
Blanchard, Alain,
Phase–Locked Loops: Application to Coherent Receiver Design.
New York, Wiley–Interscience, 1976.
Egan, William F.,
Frequency Synthesis by Phase Lock.
New York, Wiley–Interscience, 1981.
Rohde, Ulrich L.,
Digital PLL Frequency Synthesizers Theory and Design.
Englewood Cliffs, NJ, Prentice–Hall, 1983.
Berlin, Howard M.,
Design of Phase–Locked Loop Circuits, with Experiments.
Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold,
The PLL Synthesizer Cookbook.
Blue Ridge Summit, PA, Tab Books, 1980.
AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from
Electronic Design,
1987.
φ
R
—
φ
V
—
F(s) =
ASSUMING GAIN A IS VERY LARGE, THEN:
F(s) =
ζ
=
ω
n
=
NR1C
R1sC + 1
ω
n
=
ζ
=
ω
nR2
C
2
R2sC + 1
R1sC
1
N
ω
n
2K
φ
K
VCO
F(s) =
ζ
=
ω
n
=
(R1+ R2)sC + 1
R2sC + 1
NC(R1 + R2)
R2C +
N
K
φ
K
VCO
KφK
VCO
NCR
1
0.5
ω
n
Ǔ
ǒ
KφK
VCO
K
φ
K
VCO
Page 29
MC145151–2 through MC145158–2MOTOROLA
29
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a reference frequency to Motorola’s CMOS frequency synthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscillators provide very stable reference frequencies. An oscillator
capable of sinking and sourcing 50 µA at CMOS logic levels
may be direct or dc coupled to OSCin. In general, the highest
frequency capability is obtained utilizing a direct–coupled
square wave having a rail–to–rail (VDD to VSS) voltage
swing. If the oscillator does not have CMOS logic levels on
the outputs, capacitive or ac coupling to OSCin may be used.
OSC
out
, an unbuffered output, should be left floating.
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the
eem Elec-
tronic Engineers Master Catalog,
the
Gold Book,
or similar
publications.
Design an Off–Chip Reference
The user may design an off–chip crystal oscillator using
ICs specifically developed for crystal oscillator applications,
such as the MC12061 MECL device. The reference signal
from the MECL device is ac coupled to OSCin. For large amplitude signals (standard CMOS logic levels), dc coupling is
used. OSC
out
, an unbuffered output, should be left floating.
In general, the highest frequency capability is obtained with a
direct–coupled square wave having rail–to–rail v oltage
swing.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 10.
Figure 10. Pierce Crystal Oscillator Circuit
R1*
C2C1
FREQUENCY
SYNTHESIZER
OSC
out
OSC
in
*May be deleted in certain cases. See text.
R
f
For VDD = 5.0 V , the crystal should be specified for a loading capacitance, CL, which does not exceed 32 pF for frequencies to approximately 8.0 MHz, 20 pF for frequencies in
the area of 8.0 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic
CL values. T he shunt l oad capacitance, CL, presented
across the crystal can be estimated to be:
CL =
CinC
out
Cin + C
out
+ Ca + Co +
C1 • C2
C1 + C2
where
Cin= 5 pF (see Figure 11)
C
out
= 6 pF (see Figure 11)
Ca= 1 pF (see Figure 11)
CO= the crystal’s holder capacitance
(see Figure 12)
C1 and C2 = external capacitors (see Figure 10)
Figure 11. Parasitic Capacitances of the Amplifier
C
in
C
out
C
a
Figure 12. Equivalent Crystal Networks
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
2
1
2
121
R
S
L
S
C
S
R
e
X
e
C
O
The oscillator can be “trimmed” on–frequency by making a
portion or all of C1 variable. The crystal and associated components must be located as close as possible to the OSC
in
and OSC
out
pins to minimize distortion, stray capacitance,
stray inductance, and startup stabilization time. In some
cases, stray capacitance should be added to the value for C
in
and C
out
.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 12. The drive level specified by the crystal manufacturer is the maximum stress that a crystal can
withstand without damage or excessive shift in frequency . R1
in Figure 10 limits the drive level. The use of R1 may not be
necessary in some cases (i.e., R1 = 0 Ω).
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a function of voltage at OSC
out
. (Care should be taken to minimize
loading.) The frequency should increase very slightly as the
dc supply voltage is increased. An overdriven crystal will decrease in frequency or become unstable with an increase in
supply voltage. The operating supply voltage must be reduced or R1 must be increased in value if the overdriven
condition e xists. The user should n ote that the o scillator
start–up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can prove very helpful
(see Table 1).
Page 30
MC145151–2 through MC145158–2 MOTOROLA
30
Table 1. Partial List of Crystal Manufacturers
Name Address Phone
United States Crystal Corp.
Crystek Crystal
Statek Corp.
3605 McCart Ave., Ft. Worth, TX 76110
2351 Crystal Dr., Ft. Myers, FL 33907
512 N. Main St., Orange, CA 92668
(817) 921–3013
(813) 936–2109
(714) 639–7810
NOTE: Motorola cannot recommend one supplier over another and in no way suggests that this is a complete
listing of crystal manufacturers.
RECOMMENDED READING
Technical Note TN–24, Statek Corp.
Technical Note TN–7, Statek Corp.
E. Hafner, “The Piezoelectric Crystal Unit – Definitions and
Method of Measurement”,
Proc. IEEE,
Vol. 57, No. 2 Feb.,
1969.
D. Kemper, L. R osine, “Quartz Crystals for Frequency
Control”,
Electro–Technology
, June, 1969.
P. J. Ottowitz, “A Guide to Crystal Selection”,
Electronic
Design
, May, 1966.
DUAL–MODULUS PRESCALING
OVERVIEW
The technique of dual–modulus prescaling is well estab-
lished as a method of achieving high performance frequency
synthesizer operation at high frequencies. Basically, the
approach allows relatively low–frequency programmable
counters to b e used a s high–frequency programmable
counters with speed capability of several hundred MHz. This
is possible without the sacrifice in system resolution and performance that results if a fixed (single–modulus) divider is
used for the prescaler.
In dual–modulus prescaling, the lower speed counters
must be uniquely configured. Special control logic is necessary to select the divide value P or P + 1 in the prescaler for
the required amount of time (see modulus control definition).
Motorola’s dual–modulus frequency synthesizers contain
this feature and can be used with a variety of dual–modulus
prescalers to allow speed, complexity and cost to be tailored
to the system requirements. Prescalers having P, P + 1 divide values in the range of ÷ 3/÷ 4 to ÷ 128/÷ 129 can be con-
trolled by most Motorola frequency synthesizers.
Several dual–modulus prescaler approaches suitable for
use with the MC145152–2, MC145156–2, or MC145158–2
are:
MC12009
MC12011
MC12013
MC12015
MC12016
MC12017
MC12018
MC12022A
MC12032A
÷ 5/÷ 6
÷ 8/÷ 9
÷ 10/÷ 11
÷ 32/÷ 33
÷ 40/÷ 41
÷ 64/÷ 65
÷ 128/÷ 129
÷ 64/65 or ÷ 128/129
÷ 64/65 or ÷ 128/129
440 MHz
500 MHz
500 MHz
225 MHz
225 MHz
225 MHz
520 MHz
1.1 GHz
2.0 GHz
DESIGN GUIDELINES
The system total divide value, N
total
(NT) will be dictated by
the application:
NT=
frequency into the prescaler
frequency into the phase detector
= N P + A
N is the number programmed into the ÷ N counter, A is the
number programmed into the ÷ A counter, P and P + 1 are
the two selectable divide ratios available in the dual–modulus prescalers. To have a range of NT values in sequence,
the ÷ A counter is programmed from zero through P – 1 for a
particular value N in the ÷ N counter. N is then incremented to
N + 1 and the ÷ A is sequenced from 0 through P – 1 again.
There are m inimum a nd maximum values that c an be
achieved for NT. These values are a function of P and the
size of the ÷ N and ÷ A counters.
The constraint N ≥ A always applies. If A
max
= P – 1, then
N
min
≥ P – 1. Then N
Tmin
= (P – 1) P + A or (P – 1) P since A
is free to assume the value of 0.
N
Tmax
= N
max
P
+ A
max
To maximize system frequency capability, the dual–modulus prescaler output must g o from low to high after each
group of P or P + 1 input cycles. The prescaler should divide
by P when its modulus control line is high and by P + 1 when
its MC is low.
For the maximum frequency into the prescaler (f
VCOmax
),
the value used for P must be large enough such that:
1.f
VCOmax
divided by P may not exceed the frequency
capability of fin (input to the ÷ N and ÷ A counters).
2.The period of f
VCO
divided by P must be greater than
the sum of the times:
a. Propagation delay through the dual–modulus pre-
scaler.
b. Prescaler setup or release time relative to its MC
signal.
c. Propagation time from fin to the MC output for the
frequency synthesizer device.
A sometimes useful simplification in the programming
code can be achieved by choosing the values for P of 8, 16,
32, or 64. For these cases, the desired value of NT results
when NT in binary is used as the program code to the ÷ N and
÷ A counters treated in the following manner:
1.Assume the ÷ A counter contains “a” bits where 2a ≥ P.
2.Always program all higher order ÷ A counter bits above
“a” to 0.
3.Assume the ÷ N counter and the ÷ A counter (with all the
higher order bits above “a” ignored) combined into a
single binary counter of n + a bits in length (n = number
of divider stages in the ÷ N counter). The MSB of this “hypothetical” counter is to correspond to the MSB of ÷ N and
the LSB is to correspond to the LSB of ÷ A. The system
divide value, NT, now results when the value of NT in
binary is used to program the “new” n + a bit counter.
By using the two devices, several dual–modulus values
are achievable (shown in Figure 13).
Page 31
MC145151–2 through MC145158–2MOTOROLA
31
MC
DEVICE B
DEVICE A
DEVICE
B
MC12009 MC12011 MC12013DEVICE A
MC10131
MC10138
MC10154
÷
20/÷ 21
÷
50/÷ 51
÷
40/÷ 41
OR
÷
80/÷ 81
÷
64/÷ 65
OR
÷
128/÷ 129
÷
32/÷ 33
÷
80/÷ 81
÷
40/÷ 41
÷
100/÷ 101
÷
80/÷ 81
NOTE: MC12009, MC12011, and MC12013 are pin equivalent.
MC12015, MC12016, and MC12017 are pin equivalent.
Figure 13. Dual–Modulus Values
Page 32
MC145151–2 through MC145158–2 MOTOROLA
32
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP
CASE 648–08
(MC145157–2, MC145158–D)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
P SUFFIX
PLASTIC DIP
CASE 707–02
(MC145155–2)
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
22.22
6.10
3.56
0.36
1.27
1.02
0.20
2.92
23.24
6.60
4.57
0.56
1.78
1.52
0.30
3.43
0
°
0.51
0.875
0.240
0.140
0.014
0.050
0.040
0.008
0.115
0.915
0.260
0.180
0.022
0.070
0.060
0.012
0.135
15
°
1.02
2.54 BSC
7.62 BSC
0.100 BSC
0.300 BSC
0
°
0.020
15
°
0.040
A
B
C
D
F
G
H
J
K
L
M
N
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
1 9
1018
B
A
H
F
G
D
SEATING
PLANE
N
K
M
J
L
C
Page 33
MC145151–2 through MC145158–2MOTOROLA
33
P SUFFIX
PLASTIC DIP
CASE 710–02
(MC145151–2, MC145152–2)
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
36.45
13.72
3.94
0.36
1.02
1.65
0.20
2.92
0
°
0.51
37.21
14.22
5.08
0.56
1.52
2.16
0.38
3.43
15
°
1.02
1.435
0.540
0.155
0.014
0.040
0.065
0.008
0.115
0
°
0.020
1.465
0.560
0.200
0.022
0.060
0.085
0.015
0.135
15
°
0.040
A
B
C
D
F
G
H
J
K
L
M
N
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
1 14
1528
B
A
C
N
K
M
J
D
SEATING
PLANE
F
H G
L
P SUFFIX
PLASTIC DIP
CASE 738–03
(MC145156–2)
1.070
0.260
0.180
0.022
0.070
0.015
0.140
15
°
0.040
1.010
0.240
0.150
0.015
0.050
0.008
0.110
0
°
0.020
25.66
6.10
3.81
0.39
1.27
0.21
2.80
0
°
0.51
27.17
6.60
4.57
0.55
1.77
0.38
3.55
15
°
1.01
0.050 BSC
0.100 BSC
0.300 BSC
1.27 BSC
2.54 BSC
7.62 BSC
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A
B
C
D
E
F
G
J
K
L
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
-A-
C
K
N
E
G F
D
20 PL
J 20 PL
L
M
-T-
SEATING
PLANE
1 10
1120
0.25 (0.010) T A
M M
0.25 (0.010) T B
M M
B
Page 34
MC145151–2 through MC145158–2 MOTOROLA
34
DW SUFFIX
SOG PACKAGE
CASE 751D–04
(MC145155–2, MC145156–2)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
S
A
M
0.010 (0.25) B
S
T
D20X
M
B
M
0.010 (0.25)
P10X
J
F
G
18X
K
C
–T–
SEATING
PLANE
M
R
X 45
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
_ _
_ _
DW SUFFIX
SOG PACKAGE
CASE 751F–04
(MC145151–2, MC145152–2)
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
17.80
7.40
2.35
0.35
0.41
0.23
0.13
0
°
10.05
0.25
18.05
7.60
2.65
0.49
0.90
0.32
0.29
8°
10.55
0.75
0.701
0.292
0.093
0.014
0.016
0.009
0.005
0°
0.395
0.010
0.711
0.299
0.104
0.019
0.035
0.013
0.011
8°
0.415
0.029
1.27 BSC 0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION.
ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
-A-
-B-
1 14
1528
-T-
C
SEATING
PLANE
0.010 (0.25)
B
M M
M
J
-T-
K
26X G
28X D
14X P
R
X 45°
F
0.010 (0.25) T A B
M
S S
Page 35
MC145151–2 through MC145158–2MOTOROLA
35
DW SUFFIX
SOG PACKAGE
CASE 751G–02
(MC145157–2, MC145158–2)
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 10.15 10.45 0.400 0.411
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
M
B
M
0.010 (0.25)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
–A–
–B– P8X
G14X
D16X
SEATING
PLANE
–T–
S
A
M
0.010 (0.25) B
S
T
16 9
81
F
J
R
X 45
_
_ _ _ _
M
C
K
Page 36
MC145151–2 through MC145158–2 MOTOROLA
36
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different
applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
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MC145151–2/D
*MC145151-2/D*
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