Datasheet MC14512BCP, MC14512BD, MC14512BDR2, MC14512BF, MC14512BFEL Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14512B/D

MC14512B

8-Channel Data Selector

The MC14512B is an 8–channel data selector constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. This data selector finds primary
application in signal multiplexing functions. It may also be used for
data routing, digital signal switching, signal gating, and number
sequence generation.

• Diode Protection on All Inputs

• Single Supply Operation

• 3–State Output (Logic “1”, Logic “0”, High Impedance)

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

MAXIMUM RATINGS (Voltages Referenced to V

SS

) (Note 2.)

Symbol Parameter Value Unit

V

DD

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

P

D

Power Dissipation,

per Package (Note NO TAG)

500 mW

T

A

Ambient Temperature Range –55 to +125 °C

T

stg

Storage Temperature Range –65 to +150 °C

T

L

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V

in

and V

out

should be constrained

to the range V

SS

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V

SS

or VDD). Unused outputs must be left open.

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A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14512BCP PDIP–16 2000/Box
MC14512BD SOIC–16 48/Rail
MC14512BDR2 SOIC–16 2500/Tape & Reel

1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.

MARKING

DIAGRAMS

1

16

PDIP–16

P SUFFIX

CASE 648

MC14512BCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

1

16

14512B

AWLYWW

SOEIAJ–16

F SUFFIX

CASE 966

1

16

MC14512B

AWLYWW

MC14512BF SOEIAJ–16 See Note 1.
MC14512BFL1 SOEIAJ–16 See Note 1.

MC14512B

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2

TRUTH TABLE

C B A Inhibit Disable Z

0 0 0 0 0 X0
0 0 1 0 0 X1
0 1 0 0 0 X2
0 1 1 0 0 X3

1 0 0 0 0 X4
1 0 1 0 0 X5
1 1 0 0 0 X6
1 1 1 0 0 X7

X X X 1 0 0
X X X X 1 High

Impedance

X = Don’t Care

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

B

C

Z

DIS

V

DD

X7

INH

A

X3

X2

X1

X0

V

SS

X6

X5

X4

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3

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C 25_C 125_C

Characteristic Symbol

V

DD

Vdc

Min Max Min Typ

(4.)

Max Min Max

Unit

Output Voltage “0” Level

V

in

= VDD or 0

V

OL

5.0
10
15

—
—
—

0.05

0.05

0.05

—
—
—

0
0
0

0.05

0.05

0.05

—
—
—

0.05

0.05

0.05

Vdc

“1” Level

V

in

= 0 or V

DD

V

OH

5.0
10
15

4.95

9.95

14.95

—
—
—

4.95

9.95

14.95

5.0
10
15

—
—
—

4.95

9.95

14.95

—
—
—

Vdc

Input Voltage “0” Level

(V

O

= 4.5 or 0.5 Vdc)

(V

O

= 9.0 or 1.0 Vdc)

(V

O

= 13.5 or 1.5 Vdc)

V

IL

5.0
10
15

—
—
—

1.5

3.0

4.0

—
—
—

2.25

4.50

6.75

1.5

3.0

4.0

—
—
—

1.5

3.0

4.0

Vdc

“1” Level

(V

O

= 0.5 or 4.5 Vdc)

(V

O

= 1.0 or 9.0 Vdc)

(V

O

= 1.5 or 13.5 Vdc)

V

IH

5.0
10
15

3.5

7.0
11

—
—
—

3.5

7.0
11

2.75

5.50

8.25

—
—
—

3.5

7.0
11

—
—
—

Vdc

Output Drive Current

(V

OH

= 2.5 Vdc) Source

(V

OH

= 4.6 Vdc)

(V

OH

= 9.5 Vdc)

(V

OH

= 13.5 Vdc)

I

OH

5.0

5.0
10
15

– 3.0

– 0.64

– 1.6
– 4.2

—
—
—
—

– 2.4

– 0.51

– 1.3
– 3.4

– 4.2
– 0.88
– 2.25

– 8.8

—
—
—
—

– 1.7

– 0.36

– 0.9
– 2.4

—
—
—
—

mAdc

(VOL = 0.4 Vdc) Sink
(V

OL

= 0.5 Vdc)

(V

OL

= 1.5 Vdc)

I

OL

5.0
10
15

0.64

1.6

4.2

—
—
—

0.51

1.3

3.4

0.88

2.25

8.8

—
—
—

0.36

0.9

2.4

—
—
—

mAdc

Input Current I

in

15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance

(V

in

= 0)

C

in

— — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package)

I

DD

5.0
10
15

—
—
—

5.0
10
20

—
—
—

0.005

0.010

0.015

5.0
10
20

—
—
—

150
300
600

µAdc

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent,
Per Package)
(C

L

= 50 pF on all outputs, all

buffers switching)

I

T

5.0
10
15

IT = (0.8 µA/kHz) f + I

DD

IT = (1.6 µA/kHz) f + I

DD

IT = (2.4 µA/kHz) f + I

DD

µAdc

Three–State Leakage Current I

TL

15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF:
I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

T

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

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4

SWITCHING CHARACTERISTICS

(7.)

(C

L

= 50 pF, TA = 25_C, See Figure 1)

All Types

Characteristic Symbol V

DD

Typ

(8.)

Max Unit

Output Rise and Fall Time

t

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

t

TLH

,

t

THL

5.0
10
15

100

50
40

200
100

80

ns

Propagation Delay Time (Figure 2)

Inhibit, Control, or Data to Z

t

PLH

5.0
10
15

330
125

85

650
250
170

ns

Propagation Delay Time (Figure 2)

Inhibit, Control, or Data to Z

t

PHL

5.0
10
15

330
125

85

650
250
170

ns

3–State Output Delay Times (Figure 3)

“1” or “0” to High Z, and
High Z to “1” or “0”

t

PHZ

, t

PLZ

,

t

PZH

, t

PZL

5.0
10
15

60
35
30

150
100

75

ns

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Power Dissipation Test Circuit and Waveform

V

DD

I

D

C

L

Z

DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7

V

SS

PULSE

GENERATOR

50%V

in

50%

DUTY

CYCLE

MC14512B

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5

Parameter T est Conditions

Inhibit to Z A, B, C = V

SS

, XO = V

DD

A, B, C to Z Inh = VSS, XO = V

DD

Figure 2. AC Test Circuit and Waveforms

V

DD

V

SS

V

OH

V

OL

V

DD

V

SS

V

OH

V

OL

V

DD

C

L

Z

DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7

V

SS

PULSE

GENERATOR

20 ns

20 ns

90%

50%

10%

t

PLH

t

PHL

90%

10%

50%

DATA

Z

t

TLH

t

THL

TEST CONDITIONS:
INHIBIT = V

SS

A, B, C = V

SS

20 ns 20 ns

t

PHL

t

PLH

50%

90%

10%

t

THL

t

TLH

Z

INHIBIT,
A, B, OR C

90%

50%

10%

Figure 3. 3–State AC Test Circuit and Waveform

Test S1 S2 S3 S4

t

PHZ

Open Closed Closed Open

t

PLZ

Closed Open Open Closed

t

PZL

Closed Open Open Closed

t

PZH

Open Closed Closed Open

Switch Positions for 3–State Test

Z

DISABLE
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7

V

SS

PULSE

GENERATOR

V

DD

V

DD

C

L

1k

S1

S2

V

SS

V

DD

S3

S4

V

SS

V

DD

V

OH

V

OL

20 ns

90%

50%

10%

t

PLZ

t

PZL

20 ns

DISABLE

INPUT

OUTPUT

OUTPUT

V

SS

V

OH

V

OL

10%

90%

90%

10%

t

PHZ

t

PZH

≈ 2.5 V @ VDD = 5 V,

10 V, AND 15 V

≈ 2 V @ V

DD

= 5 V

≈ 6 V @ V

DD

= 10 V

≈ 10 V @ V

DD

= 15 V

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6

LOGIC DIAGRAM

13
12

11

1

2

3

4

5

6

7

9

X7

X6

X5

X4

X3

X2

X1

X0

B

C

A

15

10

14

DISABLE

INHIBIT

V

DD

Z

V

SS

1

1

IN

OUT

IN

2

OUT

2

TRANSMISSION

GATE

SELECTED

DEVICE

MC14512B

MC14512B

MC14512B

I

OD

I

TL

I

TL

I

L

LOAD

DATA

BUS

3–STA TE MODE OF OPERATION

Output terminals of several MC14512B 8–Bit Data
Selectors can be connected to a single date bus as shown.
One MC14512B is selected by the 3–state control, and the
remaining devices are disabled into a high–impedance “off”
state. The number of 8–bit data selectors, N, that may be
connected to a bus line is determined from the output drive
current, I

OD

, 3–state or disable output leakage current, ITL,

and the load current, I

L

, required to drive the bus line

(including fanout to other device inputs), and can be
calculated by:

I

TL

N = + 1

I

OD

– I

L

N must be calculated for both high and low logic state of the
bus line.

MC14512B

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7

P ACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

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8

P ACKAGE DIMENSIONS

H

E

A

1

DIM MIN MAX MIN MAX

INCHES

––– 2.05 ––– 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059
0

0.70 0.90 0.028 0.035

––– 0.78 ––– 0.031

A

1

H

E

Q

1

L

E

_

10

_

0

_

10

_

L

E

Q

1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005)

0.10 (0.004)

1

16 9

8

D

Z

E

A

b
c

D

E
e

L

M

Z

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

ISSUE O

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