Datasheet MC14511BDWR2, MC14511BF, MC14511BFEL, MC14511BFR1, MC14511BCP Datasheet (MOTOROLA)

...
Page 1
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1 Publication Order Number:
MC14511B/D
MC14511B
BCD-To-Seven Segment Latch/Decoder/Driver
The MC14511B BCD–to–seven segment latch/decoder/driver is constructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides the functions of a 4–bit storage latch, an 8421 BCD–to–seven segment decoder, and an output drive capability. Lamp test (L T
), blanking (BI), and latch enable (LE) inputs are used to test the display, to turn–off or pulse modulate the brightness of the display, and to store a BCD code, respectively. It can be used with seven–segment light–emitting diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display driver, computer/calculator display driver, cockpit display driver, and various clock, watch, and timer uses.
Low Logic Circuit Power Dissipation
High–Current Sourcing Outputs (Up to 25 mA)
Latch Storage of Code
Blanking Input
Lamp Test Provision
Readout Blanking on all Illegal Input Combinations
Lamp Intensity Modulation Capability
Time Share (Multiplexing) Facility
Supply Voltage Range = 3.0 V to 18 V
Capable of Driving Two Low–power TTL Loads, One Low–power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range
Chip Complexity: 216 FETs or 54 Equivalent Gates
Triple Diode Protection on all Inputs
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
(2.)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage Range –0.5 to +18.0 V
V
in
Input Voltage Range, All Inputs –0.5 to VDD + 0.5 V
I DC Current Drain per Input Pin 10 mA
P
D
Power Dissipation,
per Package
(3.)
500 mW
T
A
Operating Temperature Range –55 to +125 °C
T
stg
Storage Temperature Range –65 to +150 °C
I
OHmax
Maximum Output Drive Current
(Source) per Output
25 mA
P
OHmax
Maximum Continuous Output
Power (Source) per Output
(4.)
50 mA
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C
4. P
OHmax
= IOH (VDD – VOH)
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A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14511BCP PDIP–16 2000/Box MC14511BD SOIC–16 48/Rail MC14511BDW SOIC–16 47/Rail
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC1451 1BCP
AWLYYWW
MC1451 1BDWR2 SOIC–16 1000/Tape & Reel
SOIC–16 DW SUFFIX CASE 751G
1
16
14511B
AWLYYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14511B
AWLYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
14511B
AWLYWW
MC1451 1BF SOEIAJ–16 See Note 1. MC1451 1BFEL SOEIAJ–16 See Note 1.
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This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. A destructive high current mode may occur if V
in
and V
out
are not constrained to the range VSS v (Vin or V
out
) v VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if V
DD
is applied, and the outputs are shorted to VSS and are at a
logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V
SS
or VDD).
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
b
a
g
f
V
DD
e
d
c
BI
LT
C
B
V
SS
A
D
LE
0123456789
DISPLAY
a
b
c
d
e
fg
Inputs Outputs
LE BI LT D C B A a b c d e f g Display
XX0XXXX1111111 8 X 0 1 X X X X 0 0 0 0 0 0 0 Blank 01100001111110 0
01100010110000 1 01100111111001 2 01100111111001 3
01101000110011 4 01101011011011 5 01101100011111 6 01101111110000 7
01110001111111 8 01110011110011 9 0 1 1 1 0 1 0 0 0 0 0 0 0 0 Blank 0 1 1 1 0 1 1 0 0 0 0 0 0 0 Blank
0 1 1 1 1 0 0 0 0 0 0 0 0 0 Blank 0 1 1 1 1 0 1 0 0 0 0 0 0 0 Blank 0 1 1 1 1 1 0 0 0 0 0 0 0 0 Blank 0 1 1 1 1 1 1 0 0 0 0 0 0 0 Blank
111XXXX * *
X = Don’t Care *Depends upon the BCD code previously applied when LE = 0
TRUTH TABLE
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C 25_C 125_C
Characteristic Symbol
V
DD
Vdc
Min Max Min Typ
(5.)
Max Min Max
Unit
Output Voltage “0” Level
V
in
= VDD or 0
V
OL
5.0 10 15
— — —
0.05
0.05
0.05
— — —
0 0 0
0.05
0.05
0.05
— — —
0.05
0.05
0.05
Vdc
“1” Level
V
in
= 0 or V
DD
V
OH
5.0 10 15
4.1
9.1
14.1
— — —
4.1
9.1
14.1
4.57
9.58
14.59
— — —
4.1
9.1
14.1
— — —
Vdc
Input Voltage # “0” Level
(V
O
= 3.8 or 0.5 Vdc)
(V
O
= 8.8 or 1.0 Vdc)
(V
O
= 13.8 or 1.5 Vdc)
V
IL
5.0 10 15
— — —
1.5
3.0
4.0
— — —
2.25
4.50
6.75
1.5
3.0
4.0
— — —
1.5
3.0
4.0
Vdc
“1” Level
(V
O
= 0.5 or 3.8 Vdc)
(V
O
= 1.0 or 8.8 Vdc)
(V
O
= 1.5 or 13.8 Vdc)
V
IH
5.0 10 15
3.5
7.0 11
— — —
3.5
7.0 11
2.75
5.50
8.25
— — —
3.5
7.0 11
— — —
Vdc
Output Drive Voltage
(I
OH
= 0 mA) Source
(I
OH
= 5.0 mA)
(I
OH
= 10 mA)
(I
OH
= 15 mA)
(I
OH
= 20 mA)
(I
OH
= 25 mA)
V
OH
5.0 4.1 —
3.9 —
3.4 —
— — — — — —
4.1 —
3.9 —
3.4 —
4.57
4.24
4.12
3.94
3.70
3.54
— — — — — —
4.1 —
3.5 —
3.0 —
— — — — — —
Vdc
(IOH = 0 mA) (I
OH
= 5.0 mA)
(I
OH
= 10 mA)
(I
OH
= 15 mA)
(I
OH
= 20 mA)
(I
OH
= 25 mA)
10 9.1
9.0 —
8.6 —
— — — — — —
9.1 —
9.0 —
8.6 —
9.58
9.26
9.17
9.04
8.90
8.70
— — — — — —
9.1 —
8.6 —
8.2 —
— — — — — —
Vdc
(IOH = 0 mA) (I
OH
= 5.0 mA)
(I
OH
= 10 mA)
(I
OH
= 15 mA)
(I
OH
= 20 mA)
(I
OH
= 25 mA)
15 14.1
— 14 —
13.6 —
— — — — — —
14.1 — 14 —
13.6 —
14.59
14.27
14.18
14.07
13.95
13.70
— — — — — —
14.1 —
13.6 —
13.2 —
— — — — — —
Vdc
Output Drive Current
(V
OL
= 0.4 V) Sink
(V
OL
= 0.5 V)
(V
OL
= 1.5 V)
I
OL
5.0 10 15
0.64
1.6
4.2
— — —
0.51
1.3
3.4
0.88
2.25
8.8
— — —
0.36
0.9
2.4
— — —
mAdc
Input Current I
in
15 ± 0.1 ±0.00001 ± 0.1 ± 1.0 µAdc
Input Capacitance C
in
5.0 7.5 pF
Quiescent Current
(Per Package) V
in
= 0 or VDD,
I
out
= 0 µA
I
DD
5.0 10 15
— — —
5.0 10 20
— — —
0.005
0.010
0.015
5.0 10 20
— — —
150 300 600
µAdc
Total Supply Current
(6.) (7.)
(Dynamic plus Quiescent, Per Package) (C
L
= 50 pF on all outputs, all
buffers switching)
I
T
5.0 10 15
IT = (1.9 µA/kHz) f + I
DD
IT = (3.8 µA/kHz) f + I
DD
IT = (5.7 µA/kHz) f + I
DD
µAdc
5. Noise immunity specified for worst–case input combination. Noise Margin for both “1” and “0” level =
1.0 Vdc min @ V
DD
= 5.0 Vdc
2.0 Vdc min @ V
DD
= 10 Vdc
2.5 Vdc min @ V
DD
= 15 Vdc
6. The formulas given are for the typical characteristics only at 25_C.
7. To calculate total supply current at loads other than 50 pF:
I
T(CL
) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf
where: I
T
is in µA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
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SWITCHING CHARACTERISTICS
(8.)
(C
L
= 50 pF, T
A
= 25_C)
Characteristic
Symbol
V
DD
Vdc
Min Typ Max Unit
Output Rise Time
t
TLH
= (0.40 ns/pF) CL + 20 ns
t
TLH
= (0.25 ns/pF) CL + 17.5 ns
t
TLH
= (0.20 ns/pF) CL + 15 ns
t
TLH
5.0 10 15
— — —
40 30 25
80 60 50
ns
Output Fall Time
t
THL
= (1.5 ns/pF) CL + 50 ns
t
THL
= (0.75 ns/pF) CL + 37.5 ns
t
THL
= (0.55 ns/pF) CL + 37.5 ns
t
THL
5.0 10 15
— — —
125
75 65
250 150 130
ns
Data Propagation Delay Time
t
PLH
= (0.40 ns/pF) CL + 620 ns
t
PLH
= (0.25 ns/pF) CL + 237.5 ns
t
PLH
= (0.20 ns/pF) CL + 165 ns
t
PLH
5.0 10 15
— — —
640 250 175
1280
500 350
ns
t
PHL
= (1.3 ns/pF) CL + 655 ns
t
PHL
= (0.60 ns/pF) CL + 260 ns
t
PHL
= (0.35 ns/pF) CL + 182.5 ns
t
PHL
5.0 10 15
— — —
720 290 200
1440
580 400
Blank Propagation Delay Time
t
PLH
= (0.30 ns/pF) CL + 585 ns
t
PLH
= (0.25 ns/pF) CL + 187.5 ns
t
PLH
= (0.15 ns/pF) CL + 142.5 ns
t
PLH
5.0
I0
15
— — —
600 200 150
750 300 220
ns
t
PHL
= (0.85 ns/pF) CL + 442.5 ns
t
PHL
= (0.45 ns/pF) CL + 177.5 ns
t
PHL
= (0.35 ns/pF) CL + 142.5 ns
t
PHL
5.0 10 15
— — —
485 200 160
970 400 320
Lamp Test Propagation Delay Time
t
PLH
= (0.45 ns/pF) CL + 290.5 ns
t
PLH
= (0.25 ns/pF) CL + 112.5 ns
t
PLH
= (0.20 ns/pF) CL + 80 ns
t
PLH
5.0 10 15
— — —
313 125
90
625 250 180
ns
t
PHL
= (1.3 ns/pF) CL + 248 ns
t
PHL
= (0.45 ns/pF) CL + 102.5 ns
t
PHL
= (0.35 ns/pF) CL + 72.5 ns
t
PHL
5.0 10 15
— — —
313 125
90
625 250 180
Setup Time t
su
5.0 10 15
100
40 30
— — —
— — —
ns
Hold Time t
h
5.0 10 15
60 40 30
— — —
— — —
ns
Latch Enable Pulse Width t
WL
5.0 10 15
520 220 130
260 110
65
— — —
ns
8. The formulas given are for the typical characteristics only.
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MC14511B
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Figure 1. Dynamic Power Dissipation Signal Waveforms
Input LE low, and Inputs D, BI and LT high. f in respect to a system clock. All outputs connected to respective C
L
loads.
20 ns 20 ns
V
DD
V
SS
V
OH
V
OL
90%
50%
10%
50%
A, B, AND C
ANY OUTPUT
50% DUTY CYCLE
1
2f
Figure 2. Dynamic Signal Waveforms
20 ns 20 ns
V
DD
90%
INPUT C
(a) Inputs D and LE low, and Inputs A, B, BI and LT high.
V
SS
V
OH
V
OL
50% 10%
OUTPUT g
t
PLH
t
PHL
90%
10%
50%
t
TLH
t
THL
(b) Input D low, Inputs A, B, BI and LT high.
20 ns
10%
90%
50%
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
t
h
t
su
50%
INPUT C
OUTPUT g
LE
(c) Data DCBA strobed into latches.
20 ns
20 ns
V
DD
V
SS
LE
90%
50%
10%
t
WL
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CONNECTIONS TO VARIOUS DISPLAY READOUTS
COMMON
CATHODE LED
1.7 V
V
DD
V
SS
V
DD
COMMON
ANODE LED
V
SS
1.7 V
LIGHT EMITTING DIODE (LED) READOUT
INCANDESCENT READOUT FLUORESCENT READOUT
GAS DISCHARGE READOUT LIQUID CRYSTAL (LCD) READOUT
V
DD
V
DD
**
V
SS
V
DD
V
SS
FILAMENT SUPPLY
DIRECT (LOW BRIGHTNESS)
V
SS
OR APPROPRIATE
VOLTAGE BELOW V
SS
.
(CAUTION: Maximum working voltage = 18.0 V)
V
DD
APPROPRIATE
VOLTAGE
V
SS
V
SS
V
DD
EXCITATION
(SQUARE WAVE,
V
SS
TO VDD)
1/4 OF MC14070B
**A filament pre–warm resistor is recommended to reduce filament
thermal shock and increase the effective cold resistance of the filament.
Direct dc drive of LCD’s not recommended for life of LCD readouts.
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LOGIC DIAGRAM
LE 5
D6
C2
B1
A7
V
DD
= PIN 16
V
SS
= PIN 8
BI
4
LT 3
14 g
15 f
9e
10 d
11 c
12 b
13 a
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P ACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01
____
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P ACKAGE DIMENSIONS
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019
____
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P ACKAGE DIMENSIONS
SOIC–16
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–03
ISSUE B
D
14X
B16X
SEATING PLANE
S
A
M
0.25 B
S
T
16 9
81
h X 45
_
M
B
M
0.25
H8X
E
B
A
e
T
A1
A
L
C
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION.
DIM MIN MAX
MILLIMETERS
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90
q
0 7
__
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P ACKAGE DIMENSIONS
H
E
A
1
DIM MIN MAX MIN MAX
INCHES
––– 2.05 ––– 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.18 0.27 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059 0
0.70 0.90 0.028 0.035
––– 0.78 ––– 0.031
A
1
H
E
Q
1
L
E
_
10
_
0
_
10
_
L
E
Q
1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005)
0.10 (0.004)
1
16 9
8
D
Z
E
A
b c D E e
L
M
Z
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
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12
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Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 T oll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: ONlit@hibbertco.com
Fax Response Line: 303–675–2167 or 800–344–3810 T oll Free USA/Canada
N. American Technical Support: 800–282–9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor – European Support
German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)
Email: ONlit–german@hibbertco.com
French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse T ime)
Email: ONlit–french@hibbertco.com
English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)
Email: ONlit@hibbertco.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
*Available from Germany, France, Italy , England, Ireland
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